2 * ARM mach-virt emulation
4 * Copyright (c) 2013 Linaro Limited
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
18 * Emulate a virtual board which works by passing Linux all the information
19 * it needs about what devices are present via the device tree.
20 * There are some restrictions about what we can do here:
21 * + we can only present devices whose Linux drivers will work based
22 * purely on the device tree with no platform data at all
23 * + we want to present a very stripped-down minimalist platform,
24 * both because this reduces the security attack surface from the guest
25 * and also because it reduces our exposure to being broken when
26 * the kernel updates its device tree bindings and requires further
27 * information in a device binding that we aren't providing.
28 * This is essentially the same approach kvmtool uses.
31 #include "qemu/osdep.h"
32 #include "qemu/datadir.h"
33 #include "qemu/units.h"
34 #include "qemu/option.h"
35 #include "monitor/qdev.h"
36 #include "qapi/error.h"
37 #include "hw/sysbus.h"
38 #include "hw/arm/boot.h"
39 #include "hw/arm/primecell.h"
40 #include "hw/arm/virt.h"
41 #include "hw/block/flash.h"
42 #include "hw/vfio/vfio-calxeda-xgmac.h"
43 #include "hw/vfio/vfio-amd-xgbe.h"
44 #include "hw/display/ramfb.h"
46 #include "sysemu/device_tree.h"
47 #include "sysemu/numa.h"
48 #include "sysemu/runstate.h"
49 #include "sysemu/tpm.h"
50 #include "sysemu/kvm.h"
51 #include "sysemu/hvf.h"
52 #include "hw/loader.h"
53 #include "qapi/error.h"
54 #include "qemu/bitops.h"
55 #include "qemu/error-report.h"
56 #include "qemu/module.h"
57 #include "hw/pci-host/gpex.h"
58 #include "hw/virtio/virtio-pci.h"
59 #include "hw/arm/sysbus-fdt.h"
60 #include "hw/platform-bus.h"
61 #include "hw/qdev-properties.h"
62 #include "hw/arm/fdt.h"
63 #include "hw/intc/arm_gic.h"
64 #include "hw/intc/arm_gicv3_common.h"
67 #include "hw/firmware/smbios.h"
68 #include "qapi/visitor.h"
69 #include "qapi/qapi-visit-common.h"
70 #include "standard-headers/linux/input.h"
71 #include "hw/arm/smmuv3.h"
72 #include "hw/acpi/acpi.h"
73 #include "target/arm/internals.h"
74 #include "hw/mem/memory-device.h"
75 #include "hw/mem/pc-dimm.h"
76 #include "hw/mem/nvdimm.h"
77 #include "hw/acpi/generic_event_device.h"
78 #include "hw/virtio/virtio-mem-pci.h"
79 #include "hw/virtio/virtio-iommu.h"
80 #include "hw/char/pl011.h"
81 #include "qemu/guest-random.h"
83 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
84 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
87 MachineClass *mc = MACHINE_CLASS(oc); \
88 virt_machine_##major##_##minor##_options(mc); \
89 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \
94 static const TypeInfo machvirt_##major##_##minor##_info = { \
95 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \
96 .parent = TYPE_VIRT_MACHINE, \
97 .class_init = virt_##major##_##minor##_class_init, \
99 static void machvirt_machine_##major##_##minor##_init(void) \
101 type_register_static(&machvirt_##major##_##minor##_info); \
103 type_init(machvirt_machine_##major##_##minor##_init);
105 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
106 DEFINE_VIRT_MACHINE_LATEST(major, minor, true)
107 #define DEFINE_VIRT_MACHINE(major, minor) \
108 DEFINE_VIRT_MACHINE_LATEST(major, minor, false)
111 /* Number of external interrupt lines to configure the GIC with */
114 #define PLATFORM_BUS_NUM_IRQS 64
116 /* Legacy RAM limit in GB (< version 4.0) */
117 #define LEGACY_RAMLIMIT_GB 255
118 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB)
120 /* Addresses and sizes of our components.
121 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
122 * 128MB..256MB is used for miscellaneous device I/O.
123 * 256MB..1GB is reserved for possible future PCI support (ie where the
124 * PCI memory window will go if we add a PCI host controller).
125 * 1GB and up is RAM (which may happily spill over into the
126 * high memory region beyond 4GB).
127 * This represents a compromise between how much RAM can be given to
128 * a 32 bit VM and leaving space for expansion and in particular for PCI.
129 * Note that devices should generally be placed at multiples of 0x10000,
130 * to accommodate guests using 64K pages.
132 static const MemMapEntry base_memmap
[] = {
133 /* Space up to 0x8000000 is reserved for a boot ROM */
134 [VIRT_FLASH
] = { 0, 0x08000000 },
135 [VIRT_CPUPERIPHS
] = { 0x08000000, 0x00020000 },
136 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
137 [VIRT_GIC_DIST
] = { 0x08000000, 0x00010000 },
138 [VIRT_GIC_CPU
] = { 0x08010000, 0x00010000 },
139 [VIRT_GIC_V2M
] = { 0x08020000, 0x00001000 },
140 [VIRT_GIC_HYP
] = { 0x08030000, 0x00010000 },
141 [VIRT_GIC_VCPU
] = { 0x08040000, 0x00010000 },
142 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */
143 [VIRT_GIC_ITS
] = { 0x08080000, 0x00020000 },
144 /* This redistributor space allows up to 2*64kB*123 CPUs */
145 [VIRT_GIC_REDIST
] = { 0x080A0000, 0x00F60000 },
146 [VIRT_UART
] = { 0x09000000, 0x00001000 },
147 [VIRT_RTC
] = { 0x09010000, 0x00001000 },
148 [VIRT_FW_CFG
] = { 0x09020000, 0x00000018 },
149 [VIRT_GPIO
] = { 0x09030000, 0x00001000 },
150 [VIRT_SECURE_UART
] = { 0x09040000, 0x00001000 },
151 [VIRT_SMMU
] = { 0x09050000, 0x00020000 },
152 [VIRT_PCDIMM_ACPI
] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN
},
153 [VIRT_ACPI_GED
] = { 0x09080000, ACPI_GED_EVT_SEL_LEN
},
154 [VIRT_NVDIMM_ACPI
] = { 0x09090000, NVDIMM_ACPI_IO_LEN
},
155 [VIRT_PVTIME
] = { 0x090a0000, 0x00010000 },
156 [VIRT_SECURE_GPIO
] = { 0x090b0000, 0x00001000 },
157 [VIRT_MMIO
] = { 0x0a000000, 0x00000200 },
158 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
159 [VIRT_PLATFORM_BUS
] = { 0x0c000000, 0x02000000 },
160 [VIRT_SECURE_MEM
] = { 0x0e000000, 0x01000000 },
161 [VIRT_PCIE_MMIO
] = { 0x10000000, 0x2eff0000 },
162 [VIRT_PCIE_PIO
] = { 0x3eff0000, 0x00010000 },
163 [VIRT_PCIE_ECAM
] = { 0x3f000000, 0x01000000 },
164 /* Actual RAM size depends on initial RAM and device memory settings */
165 [VIRT_MEM
] = { GiB
, LEGACY_RAMLIMIT_BYTES
},
169 * Highmem IO Regions: This memory map is floating, located after the RAM.
170 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the
171 * top of the RAM, so that its base get the same alignment as the size,
172 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is
173 * less than 256GiB of RAM, the floating area starts at the 256GiB mark.
174 * Note the extended_memmap is sized so that it eventually also includes the
175 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last
176 * index of base_memmap).
178 static MemMapEntry extended_memmap
[] = {
179 /* Additional 64 MB redist region (can contain up to 512 redistributors) */
180 [VIRT_HIGH_GIC_REDIST2
] = { 0x0, 64 * MiB
},
181 [VIRT_HIGH_PCIE_ECAM
] = { 0x0, 256 * MiB
},
182 /* Second PCIe window */
183 [VIRT_HIGH_PCIE_MMIO
] = { 0x0, 512 * GiB
},
186 static const int a15irqmap
[] = {
189 [VIRT_PCIE
] = 3, /* ... to 6 */
191 [VIRT_SECURE_UART
] = 8,
193 [VIRT_MMIO
] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
194 [VIRT_GIC_V2M
] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
195 [VIRT_SMMU
] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */
196 [VIRT_PLATFORM_BUS
] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
199 static const char *valid_cpus
[] = {
200 ARM_CPU_TYPE_NAME("cortex-a7"),
201 ARM_CPU_TYPE_NAME("cortex-a15"),
202 ARM_CPU_TYPE_NAME("cortex-a53"),
203 ARM_CPU_TYPE_NAME("cortex-a57"),
204 ARM_CPU_TYPE_NAME("cortex-a72"),
205 ARM_CPU_TYPE_NAME("a64fx"),
206 ARM_CPU_TYPE_NAME("host"),
207 ARM_CPU_TYPE_NAME("max"),
210 static bool cpu_type_valid(const char *cpu
)
214 for (i
= 0; i
< ARRAY_SIZE(valid_cpus
); i
++) {
215 if (strcmp(cpu
, valid_cpus
[i
]) == 0) {
222 static void create_kaslr_seed(MachineState
*ms
, const char *node
)
226 if (qemu_guest_getrandom(&seed
, sizeof(seed
), NULL
)) {
229 qemu_fdt_setprop_u64(ms
->fdt
, node
, "kaslr-seed", seed
);
232 static void create_fdt(VirtMachineState
*vms
)
234 MachineState
*ms
= MACHINE(vms
);
235 int nb_numa_nodes
= ms
->numa_state
->num_nodes
;
236 void *fdt
= create_device_tree(&vms
->fdt_size
);
239 error_report("create_device_tree() failed");
246 qemu_fdt_setprop_string(fdt
, "/", "compatible", "linux,dummy-virt");
247 qemu_fdt_setprop_cell(fdt
, "/", "#address-cells", 0x2);
248 qemu_fdt_setprop_cell(fdt
, "/", "#size-cells", 0x2);
250 /* /chosen must exist for load_dtb to fill in necessary properties later */
251 qemu_fdt_add_subnode(fdt
, "/chosen");
252 if (vms
->dtb_kaslr_seed
) {
253 create_kaslr_seed(ms
, "/chosen");
257 qemu_fdt_add_subnode(fdt
, "/secure-chosen");
258 if (vms
->dtb_kaslr_seed
) {
259 create_kaslr_seed(ms
, "/secure-chosen");
263 /* Clock node, for the benefit of the UART. The kernel device tree
264 * binding documentation claims the PL011 node clock properties are
265 * optional but in practice if you omit them the kernel refuses to
266 * probe for the device.
268 vms
->clock_phandle
= qemu_fdt_alloc_phandle(fdt
);
269 qemu_fdt_add_subnode(fdt
, "/apb-pclk");
270 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "compatible", "fixed-clock");
271 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "#clock-cells", 0x0);
272 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "clock-frequency", 24000000);
273 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "clock-output-names",
275 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "phandle", vms
->clock_phandle
);
277 if (nb_numa_nodes
> 0 && ms
->numa_state
->have_numa_distance
) {
278 int size
= nb_numa_nodes
* nb_numa_nodes
* 3 * sizeof(uint32_t);
279 uint32_t *matrix
= g_malloc0(size
);
282 for (i
= 0; i
< nb_numa_nodes
; i
++) {
283 for (j
= 0; j
< nb_numa_nodes
; j
++) {
284 idx
= (i
* nb_numa_nodes
+ j
) * 3;
285 matrix
[idx
+ 0] = cpu_to_be32(i
);
286 matrix
[idx
+ 1] = cpu_to_be32(j
);
288 cpu_to_be32(ms
->numa_state
->nodes
[i
].distance
[j
]);
292 qemu_fdt_add_subnode(fdt
, "/distance-map");
293 qemu_fdt_setprop_string(fdt
, "/distance-map", "compatible",
294 "numa-distance-map-v1");
295 qemu_fdt_setprop(fdt
, "/distance-map", "distance-matrix",
301 static void fdt_add_timer_nodes(const VirtMachineState
*vms
)
303 /* On real hardware these interrupts are level-triggered.
304 * On KVM they were edge-triggered before host kernel version 4.4,
305 * and level-triggered afterwards.
306 * On emulated QEMU they are level-triggered.
308 * Getting the DTB info about them wrong is awkward for some
310 * pre-4.8 ignore the DT and leave the interrupt configured
311 * with whatever the GIC reset value (or the bootloader) left it at
312 * 4.8 before rc6 honour the incorrect data by programming it back
313 * into the GIC, causing problems
314 * 4.8rc6 and later ignore the DT and always write "level triggered"
317 * For backwards-compatibility, virt-2.8 and earlier will continue
318 * to say these are edge-triggered, but later machines will report
319 * the correct information.
322 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
323 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
324 MachineState
*ms
= MACHINE(vms
);
326 if (vmc
->claim_edge_triggered_timers
) {
327 irqflags
= GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
;
330 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
331 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
332 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
333 (1 << MACHINE(vms
)->smp
.cpus
) - 1);
336 qemu_fdt_add_subnode(ms
->fdt
, "/timer");
338 armcpu
= ARM_CPU(qemu_get_cpu(0));
339 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
340 const char compat
[] = "arm,armv8-timer\0arm,armv7-timer";
341 qemu_fdt_setprop(ms
->fdt
, "/timer", "compatible",
342 compat
, sizeof(compat
));
344 qemu_fdt_setprop_string(ms
->fdt
, "/timer", "compatible",
347 qemu_fdt_setprop(ms
->fdt
, "/timer", "always-on", NULL
, 0);
348 qemu_fdt_setprop_cells(ms
->fdt
, "/timer", "interrupts",
349 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_S_EL1_IRQ
, irqflags
,
350 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_NS_EL1_IRQ
, irqflags
,
351 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_VIRT_IRQ
, irqflags
,
352 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_NS_EL2_IRQ
, irqflags
);
355 static void fdt_add_cpu_nodes(const VirtMachineState
*vms
)
359 const MachineState
*ms
= MACHINE(vms
);
360 const VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
361 int smp_cpus
= ms
->smp
.cpus
;
364 * See Linux Documentation/devicetree/bindings/arm/cpus.yaml
365 * On ARM v8 64-bit systems value should be set to 2,
366 * that corresponds to the MPIDR_EL1 register size.
367 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
368 * in the system, #address-cells can be set to 1, since
369 * MPIDR_EL1[63:32] bits are not used for CPUs
372 * Here we actually don't know whether our system is 32- or 64-bit one.
373 * The simplest way to go is to examine affinity IDs of all our CPUs. If
374 * at least one of them has Aff3 populated, we set #address-cells to 2.
376 for (cpu
= 0; cpu
< smp_cpus
; cpu
++) {
377 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
379 if (armcpu
->mp_affinity
& ARM_AFF3_MASK
) {
385 qemu_fdt_add_subnode(ms
->fdt
, "/cpus");
386 qemu_fdt_setprop_cell(ms
->fdt
, "/cpus", "#address-cells", addr_cells
);
387 qemu_fdt_setprop_cell(ms
->fdt
, "/cpus", "#size-cells", 0x0);
389 for (cpu
= smp_cpus
- 1; cpu
>= 0; cpu
--) {
390 char *nodename
= g_strdup_printf("/cpus/cpu@%d", cpu
);
391 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
392 CPUState
*cs
= CPU(armcpu
);
394 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
395 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "device_type", "cpu");
396 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
397 armcpu
->dtb_compatible
);
399 if (vms
->psci_conduit
!= QEMU_PSCI_CONDUIT_DISABLED
&& smp_cpus
> 1) {
400 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
401 "enable-method", "psci");
404 if (addr_cells
== 2) {
405 qemu_fdt_setprop_u64(ms
->fdt
, nodename
, "reg",
406 armcpu
->mp_affinity
);
408 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "reg",
409 armcpu
->mp_affinity
);
412 if (ms
->possible_cpus
->cpus
[cs
->cpu_index
].props
.has_node_id
) {
413 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "numa-node-id",
414 ms
->possible_cpus
->cpus
[cs
->cpu_index
].props
.node_id
);
417 if (!vmc
->no_cpu_topology
) {
418 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle",
419 qemu_fdt_alloc_phandle(ms
->fdt
));
425 if (!vmc
->no_cpu_topology
) {
427 * Add vCPU topology description through fdt node cpu-map.
429 * See Linux Documentation/devicetree/bindings/cpu/cpu-topology.txt
430 * In a SMP system, the hierarchy of CPUs can be defined through
431 * four entities that are used to describe the layout of CPUs in
432 * the system: socket/cluster/core/thread.
434 * A socket node represents the boundary of system physical package
435 * and its child nodes must be one or more cluster nodes. A system
436 * can contain several layers of clustering within a single physical
437 * package and cluster nodes can be contained in parent cluster nodes.
439 * Note: currently we only support one layer of clustering within
440 * each physical package.
442 qemu_fdt_add_subnode(ms
->fdt
, "/cpus/cpu-map");
444 for (cpu
= smp_cpus
- 1; cpu
>= 0; cpu
--) {
445 char *cpu_path
= g_strdup_printf("/cpus/cpu@%d", cpu
);
448 if (ms
->smp
.threads
> 1) {
449 map_path
= g_strdup_printf(
450 "/cpus/cpu-map/socket%d/cluster%d/core%d/thread%d",
451 cpu
/ (ms
->smp
.clusters
* ms
->smp
.cores
* ms
->smp
.threads
),
452 (cpu
/ (ms
->smp
.cores
* ms
->smp
.threads
)) % ms
->smp
.clusters
,
453 (cpu
/ ms
->smp
.threads
) % ms
->smp
.cores
,
454 cpu
% ms
->smp
.threads
);
456 map_path
= g_strdup_printf(
457 "/cpus/cpu-map/socket%d/cluster%d/core%d",
458 cpu
/ (ms
->smp
.clusters
* ms
->smp
.cores
),
459 (cpu
/ ms
->smp
.cores
) % ms
->smp
.clusters
,
460 cpu
% ms
->smp
.cores
);
462 qemu_fdt_add_path(ms
->fdt
, map_path
);
463 qemu_fdt_setprop_phandle(ms
->fdt
, map_path
, "cpu", cpu_path
);
471 static void fdt_add_its_gic_node(VirtMachineState
*vms
)
474 MachineState
*ms
= MACHINE(vms
);
476 vms
->msi_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
477 nodename
= g_strdup_printf("/intc/its@%" PRIx64
,
478 vms
->memmap
[VIRT_GIC_ITS
].base
);
479 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
480 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
482 qemu_fdt_setprop(ms
->fdt
, nodename
, "msi-controller", NULL
, 0);
483 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
484 2, vms
->memmap
[VIRT_GIC_ITS
].base
,
485 2, vms
->memmap
[VIRT_GIC_ITS
].size
);
486 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle", vms
->msi_phandle
);
490 static void fdt_add_v2m_gic_node(VirtMachineState
*vms
)
492 MachineState
*ms
= MACHINE(vms
);
495 nodename
= g_strdup_printf("/intc/v2m@%" PRIx64
,
496 vms
->memmap
[VIRT_GIC_V2M
].base
);
497 vms
->msi_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
498 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
499 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
500 "arm,gic-v2m-frame");
501 qemu_fdt_setprop(ms
->fdt
, nodename
, "msi-controller", NULL
, 0);
502 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
503 2, vms
->memmap
[VIRT_GIC_V2M
].base
,
504 2, vms
->memmap
[VIRT_GIC_V2M
].size
);
505 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle", vms
->msi_phandle
);
509 static void fdt_add_gic_node(VirtMachineState
*vms
)
511 MachineState
*ms
= MACHINE(vms
);
514 vms
->gic_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
515 qemu_fdt_setprop_cell(ms
->fdt
, "/", "interrupt-parent", vms
->gic_phandle
);
517 nodename
= g_strdup_printf("/intc@%" PRIx64
,
518 vms
->memmap
[VIRT_GIC_DIST
].base
);
519 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
520 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#interrupt-cells", 3);
521 qemu_fdt_setprop(ms
->fdt
, nodename
, "interrupt-controller", NULL
, 0);
522 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#address-cells", 0x2);
523 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#size-cells", 0x2);
524 qemu_fdt_setprop(ms
->fdt
, nodename
, "ranges", NULL
, 0);
525 if (vms
->gic_version
== VIRT_GIC_VERSION_3
) {
526 int nb_redist_regions
= virt_gicv3_redist_region_count(vms
);
528 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
531 qemu_fdt_setprop_cell(ms
->fdt
, nodename
,
532 "#redistributor-regions", nb_redist_regions
);
534 if (nb_redist_regions
== 1) {
535 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
536 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
537 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
538 2, vms
->memmap
[VIRT_GIC_REDIST
].base
,
539 2, vms
->memmap
[VIRT_GIC_REDIST
].size
);
541 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
542 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
543 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
544 2, vms
->memmap
[VIRT_GIC_REDIST
].base
,
545 2, vms
->memmap
[VIRT_GIC_REDIST
].size
,
546 2, vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].base
,
547 2, vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].size
);
551 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
552 GIC_FDT_IRQ_TYPE_PPI
, ARCH_GIC_MAINT_IRQ
,
553 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
556 /* 'cortex-a15-gic' means 'GIC v2' */
557 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
558 "arm,cortex-a15-gic");
560 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
561 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
562 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
563 2, vms
->memmap
[VIRT_GIC_CPU
].base
,
564 2, vms
->memmap
[VIRT_GIC_CPU
].size
);
566 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
567 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
568 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
569 2, vms
->memmap
[VIRT_GIC_CPU
].base
,
570 2, vms
->memmap
[VIRT_GIC_CPU
].size
,
571 2, vms
->memmap
[VIRT_GIC_HYP
].base
,
572 2, vms
->memmap
[VIRT_GIC_HYP
].size
,
573 2, vms
->memmap
[VIRT_GIC_VCPU
].base
,
574 2, vms
->memmap
[VIRT_GIC_VCPU
].size
);
575 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
576 GIC_FDT_IRQ_TYPE_PPI
, ARCH_GIC_MAINT_IRQ
,
577 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
581 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle", vms
->gic_phandle
);
585 static void fdt_add_pmu_nodes(const VirtMachineState
*vms
)
587 ARMCPU
*armcpu
= ARM_CPU(first_cpu
);
588 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
589 MachineState
*ms
= MACHINE(vms
);
591 if (!arm_feature(&armcpu
->env
, ARM_FEATURE_PMU
)) {
592 assert(!object_property_get_bool(OBJECT(armcpu
), "pmu", NULL
));
596 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
597 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
598 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
599 (1 << MACHINE(vms
)->smp
.cpus
) - 1);
602 qemu_fdt_add_subnode(ms
->fdt
, "/pmu");
603 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
604 const char compat
[] = "arm,armv8-pmuv3";
605 qemu_fdt_setprop(ms
->fdt
, "/pmu", "compatible",
606 compat
, sizeof(compat
));
607 qemu_fdt_setprop_cells(ms
->fdt
, "/pmu", "interrupts",
608 GIC_FDT_IRQ_TYPE_PPI
, VIRTUAL_PMU_IRQ
, irqflags
);
612 static inline DeviceState
*create_acpi_ged(VirtMachineState
*vms
)
615 MachineState
*ms
= MACHINE(vms
);
616 int irq
= vms
->irqmap
[VIRT_ACPI_GED
];
617 uint32_t event
= ACPI_GED_PWR_DOWN_EVT
;
620 event
|= ACPI_GED_MEM_HOTPLUG_EVT
;
623 if (ms
->nvdimms_state
->is_enabled
) {
624 event
|= ACPI_GED_NVDIMM_HOTPLUG_EVT
;
627 dev
= qdev_new(TYPE_ACPI_GED
);
628 qdev_prop_set_uint32(dev
, "ged-event", event
);
630 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_ACPI_GED
].base
);
631 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 1, vms
->memmap
[VIRT_PCDIMM_ACPI
].base
);
632 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0, qdev_get_gpio_in(vms
->gic
, irq
));
634 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
639 static void create_its(VirtMachineState
*vms
)
641 const char *itsclass
= its_class_name();
644 if (!strcmp(itsclass
, "arm-gicv3-its")) {
651 /* Do nothing if not supported */
655 dev
= qdev_new(itsclass
);
657 object_property_set_link(OBJECT(dev
), "parent-gicv3", OBJECT(vms
->gic
),
659 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
660 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_GIC_ITS
].base
);
662 fdt_add_its_gic_node(vms
);
663 vms
->msi_controller
= VIRT_MSI_CTRL_ITS
;
666 static void create_v2m(VirtMachineState
*vms
)
669 int irq
= vms
->irqmap
[VIRT_GIC_V2M
];
672 dev
= qdev_new("arm-gicv2m");
673 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_GIC_V2M
].base
);
674 qdev_prop_set_uint32(dev
, "base-spi", irq
);
675 qdev_prop_set_uint32(dev
, "num-spi", NUM_GICV2M_SPIS
);
676 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
678 for (i
= 0; i
< NUM_GICV2M_SPIS
; i
++) {
679 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
680 qdev_get_gpio_in(vms
->gic
, irq
+ i
));
683 fdt_add_v2m_gic_node(vms
);
684 vms
->msi_controller
= VIRT_MSI_CTRL_GICV2M
;
687 static void create_gic(VirtMachineState
*vms
, MemoryRegion
*mem
)
689 MachineState
*ms
= MACHINE(vms
);
690 /* We create a standalone GIC */
691 SysBusDevice
*gicbusdev
;
693 int type
= vms
->gic_version
, i
;
694 unsigned int smp_cpus
= ms
->smp
.cpus
;
695 uint32_t nb_redist_regions
= 0;
697 gictype
= (type
== 3) ? gicv3_class_name() : gic_class_name();
699 vms
->gic
= qdev_new(gictype
);
700 qdev_prop_set_uint32(vms
->gic
, "revision", type
);
701 qdev_prop_set_uint32(vms
->gic
, "num-cpu", smp_cpus
);
702 /* Note that the num-irq property counts both internal and external
703 * interrupts; there are always 32 of the former (mandated by GIC spec).
705 qdev_prop_set_uint32(vms
->gic
, "num-irq", NUM_IRQS
+ 32);
706 if (!kvm_irqchip_in_kernel()) {
707 qdev_prop_set_bit(vms
->gic
, "has-security-extensions", vms
->secure
);
711 uint32_t redist0_capacity
=
712 vms
->memmap
[VIRT_GIC_REDIST
].size
/ GICV3_REDIST_SIZE
;
713 uint32_t redist0_count
= MIN(smp_cpus
, redist0_capacity
);
715 nb_redist_regions
= virt_gicv3_redist_region_count(vms
);
717 qdev_prop_set_uint32(vms
->gic
, "len-redist-region-count",
719 qdev_prop_set_uint32(vms
->gic
, "redist-region-count[0]", redist0_count
);
721 if (!kvm_irqchip_in_kernel()) {
723 object_property_set_link(OBJECT(vms
->gic
), "sysmem",
724 OBJECT(mem
), &error_fatal
);
725 qdev_prop_set_bit(vms
->gic
, "has-lpi", true);
729 if (nb_redist_regions
== 2) {
730 uint32_t redist1_capacity
=
731 vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].size
/ GICV3_REDIST_SIZE
;
733 qdev_prop_set_uint32(vms
->gic
, "redist-region-count[1]",
734 MIN(smp_cpus
- redist0_count
, redist1_capacity
));
737 if (!kvm_irqchip_in_kernel()) {
738 qdev_prop_set_bit(vms
->gic
, "has-virtualization-extensions",
742 gicbusdev
= SYS_BUS_DEVICE(vms
->gic
);
743 sysbus_realize_and_unref(gicbusdev
, &error_fatal
);
744 sysbus_mmio_map(gicbusdev
, 0, vms
->memmap
[VIRT_GIC_DIST
].base
);
746 sysbus_mmio_map(gicbusdev
, 1, vms
->memmap
[VIRT_GIC_REDIST
].base
);
747 if (nb_redist_regions
== 2) {
748 sysbus_mmio_map(gicbusdev
, 2,
749 vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].base
);
752 sysbus_mmio_map(gicbusdev
, 1, vms
->memmap
[VIRT_GIC_CPU
].base
);
754 sysbus_mmio_map(gicbusdev
, 2, vms
->memmap
[VIRT_GIC_HYP
].base
);
755 sysbus_mmio_map(gicbusdev
, 3, vms
->memmap
[VIRT_GIC_VCPU
].base
);
759 /* Wire the outputs from each CPU's generic timer and the GICv3
760 * maintenance interrupt signal to the appropriate GIC PPI inputs,
761 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
763 for (i
= 0; i
< smp_cpus
; i
++) {
764 DeviceState
*cpudev
= DEVICE(qemu_get_cpu(i
));
765 int ppibase
= NUM_IRQS
+ i
* GIC_INTERNAL
+ GIC_NR_SGIS
;
767 /* Mapping from the output timer irq lines from the CPU to the
768 * GIC PPI inputs we use for the virt board.
770 const int timer_irq
[] = {
771 [GTIMER_PHYS
] = ARCH_TIMER_NS_EL1_IRQ
,
772 [GTIMER_VIRT
] = ARCH_TIMER_VIRT_IRQ
,
773 [GTIMER_HYP
] = ARCH_TIMER_NS_EL2_IRQ
,
774 [GTIMER_SEC
] = ARCH_TIMER_S_EL1_IRQ
,
777 for (irq
= 0; irq
< ARRAY_SIZE(timer_irq
); irq
++) {
778 qdev_connect_gpio_out(cpudev
, irq
,
779 qdev_get_gpio_in(vms
->gic
,
780 ppibase
+ timer_irq
[irq
]));
784 qemu_irq irq
= qdev_get_gpio_in(vms
->gic
,
785 ppibase
+ ARCH_GIC_MAINT_IRQ
);
786 qdev_connect_gpio_out_named(cpudev
, "gicv3-maintenance-interrupt",
788 } else if (vms
->virt
) {
789 qemu_irq irq
= qdev_get_gpio_in(vms
->gic
,
790 ppibase
+ ARCH_GIC_MAINT_IRQ
);
791 sysbus_connect_irq(gicbusdev
, i
+ 4 * smp_cpus
, irq
);
794 qdev_connect_gpio_out_named(cpudev
, "pmu-interrupt", 0,
795 qdev_get_gpio_in(vms
->gic
, ppibase
798 sysbus_connect_irq(gicbusdev
, i
, qdev_get_gpio_in(cpudev
, ARM_CPU_IRQ
));
799 sysbus_connect_irq(gicbusdev
, i
+ smp_cpus
,
800 qdev_get_gpio_in(cpudev
, ARM_CPU_FIQ
));
801 sysbus_connect_irq(gicbusdev
, i
+ 2 * smp_cpus
,
802 qdev_get_gpio_in(cpudev
, ARM_CPU_VIRQ
));
803 sysbus_connect_irq(gicbusdev
, i
+ 3 * smp_cpus
,
804 qdev_get_gpio_in(cpudev
, ARM_CPU_VFIQ
));
807 fdt_add_gic_node(vms
);
809 if (type
== 3 && vms
->its
) {
811 } else if (type
== 2) {
816 static void create_uart(const VirtMachineState
*vms
, int uart
,
817 MemoryRegion
*mem
, Chardev
*chr
)
820 hwaddr base
= vms
->memmap
[uart
].base
;
821 hwaddr size
= vms
->memmap
[uart
].size
;
822 int irq
= vms
->irqmap
[uart
];
823 const char compat
[] = "arm,pl011\0arm,primecell";
824 const char clocknames
[] = "uartclk\0apb_pclk";
825 DeviceState
*dev
= qdev_new(TYPE_PL011
);
826 SysBusDevice
*s
= SYS_BUS_DEVICE(dev
);
827 MachineState
*ms
= MACHINE(vms
);
829 qdev_prop_set_chr(dev
, "chardev", chr
);
830 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
831 memory_region_add_subregion(mem
, base
,
832 sysbus_mmio_get_region(s
, 0));
833 sysbus_connect_irq(s
, 0, qdev_get_gpio_in(vms
->gic
, irq
));
835 nodename
= g_strdup_printf("/pl011@%" PRIx64
, base
);
836 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
837 /* Note that we can't use setprop_string because of the embedded NUL */
838 qemu_fdt_setprop(ms
->fdt
, nodename
, "compatible",
839 compat
, sizeof(compat
));
840 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
842 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
843 GIC_FDT_IRQ_TYPE_SPI
, irq
,
844 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
845 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "clocks",
846 vms
->clock_phandle
, vms
->clock_phandle
);
847 qemu_fdt_setprop(ms
->fdt
, nodename
, "clock-names",
848 clocknames
, sizeof(clocknames
));
850 if (uart
== VIRT_UART
) {
851 qemu_fdt_setprop_string(ms
->fdt
, "/chosen", "stdout-path", nodename
);
853 /* Mark as not usable by the normal world */
854 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "status", "disabled");
855 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "secure-status", "okay");
857 qemu_fdt_setprop_string(ms
->fdt
, "/secure-chosen", "stdout-path",
864 static void create_rtc(const VirtMachineState
*vms
)
867 hwaddr base
= vms
->memmap
[VIRT_RTC
].base
;
868 hwaddr size
= vms
->memmap
[VIRT_RTC
].size
;
869 int irq
= vms
->irqmap
[VIRT_RTC
];
870 const char compat
[] = "arm,pl031\0arm,primecell";
871 MachineState
*ms
= MACHINE(vms
);
873 sysbus_create_simple("pl031", base
, qdev_get_gpio_in(vms
->gic
, irq
));
875 nodename
= g_strdup_printf("/pl031@%" PRIx64
, base
);
876 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
877 qemu_fdt_setprop(ms
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
878 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
880 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
881 GIC_FDT_IRQ_TYPE_SPI
, irq
,
882 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
883 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "clocks", vms
->clock_phandle
);
884 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "clock-names", "apb_pclk");
888 static DeviceState
*gpio_key_dev
;
889 static void virt_powerdown_req(Notifier
*n
, void *opaque
)
891 VirtMachineState
*s
= container_of(n
, VirtMachineState
, powerdown_notifier
);
894 acpi_send_event(s
->acpi_dev
, ACPI_POWER_DOWN_STATUS
);
896 /* use gpio Pin 3 for power button event */
897 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev
, 0), 1);
901 static void create_gpio_keys(char *fdt
, DeviceState
*pl061_dev
,
904 gpio_key_dev
= sysbus_create_simple("gpio-key", -1,
905 qdev_get_gpio_in(pl061_dev
, 3));
907 qemu_fdt_add_subnode(fdt
, "/gpio-keys");
908 qemu_fdt_setprop_string(fdt
, "/gpio-keys", "compatible", "gpio-keys");
909 qemu_fdt_setprop_cell(fdt
, "/gpio-keys", "#size-cells", 0);
910 qemu_fdt_setprop_cell(fdt
, "/gpio-keys", "#address-cells", 1);
912 qemu_fdt_add_subnode(fdt
, "/gpio-keys/poweroff");
913 qemu_fdt_setprop_string(fdt
, "/gpio-keys/poweroff",
914 "label", "GPIO Key Poweroff");
915 qemu_fdt_setprop_cell(fdt
, "/gpio-keys/poweroff", "linux,code",
917 qemu_fdt_setprop_cells(fdt
, "/gpio-keys/poweroff",
918 "gpios", phandle
, 3, 0);
921 #define SECURE_GPIO_POWEROFF 0
922 #define SECURE_GPIO_RESET 1
924 static void create_secure_gpio_pwr(char *fdt
, DeviceState
*pl061_dev
,
927 DeviceState
*gpio_pwr_dev
;
930 gpio_pwr_dev
= sysbus_create_simple("gpio-pwr", -1, NULL
);
932 /* connect secure pl061 to gpio-pwr */
933 qdev_connect_gpio_out(pl061_dev
, SECURE_GPIO_RESET
,
934 qdev_get_gpio_in_named(gpio_pwr_dev
, "reset", 0));
935 qdev_connect_gpio_out(pl061_dev
, SECURE_GPIO_POWEROFF
,
936 qdev_get_gpio_in_named(gpio_pwr_dev
, "shutdown", 0));
938 qemu_fdt_add_subnode(fdt
, "/gpio-poweroff");
939 qemu_fdt_setprop_string(fdt
, "/gpio-poweroff", "compatible",
941 qemu_fdt_setprop_cells(fdt
, "/gpio-poweroff",
942 "gpios", phandle
, SECURE_GPIO_POWEROFF
, 0);
943 qemu_fdt_setprop_string(fdt
, "/gpio-poweroff", "status", "disabled");
944 qemu_fdt_setprop_string(fdt
, "/gpio-poweroff", "secure-status",
947 qemu_fdt_add_subnode(fdt
, "/gpio-restart");
948 qemu_fdt_setprop_string(fdt
, "/gpio-restart", "compatible",
950 qemu_fdt_setprop_cells(fdt
, "/gpio-restart",
951 "gpios", phandle
, SECURE_GPIO_RESET
, 0);
952 qemu_fdt_setprop_string(fdt
, "/gpio-restart", "status", "disabled");
953 qemu_fdt_setprop_string(fdt
, "/gpio-restart", "secure-status",
957 static void create_gpio_devices(const VirtMachineState
*vms
, int gpio
,
961 DeviceState
*pl061_dev
;
962 hwaddr base
= vms
->memmap
[gpio
].base
;
963 hwaddr size
= vms
->memmap
[gpio
].size
;
964 int irq
= vms
->irqmap
[gpio
];
965 const char compat
[] = "arm,pl061\0arm,primecell";
967 MachineState
*ms
= MACHINE(vms
);
969 pl061_dev
= qdev_new("pl061");
970 /* Pull lines down to 0 if not driven by the PL061 */
971 qdev_prop_set_uint32(pl061_dev
, "pullups", 0);
972 qdev_prop_set_uint32(pl061_dev
, "pulldowns", 0xff);
973 s
= SYS_BUS_DEVICE(pl061_dev
);
974 sysbus_realize_and_unref(s
, &error_fatal
);
975 memory_region_add_subregion(mem
, base
, sysbus_mmio_get_region(s
, 0));
976 sysbus_connect_irq(s
, 0, qdev_get_gpio_in(vms
->gic
, irq
));
978 uint32_t phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
979 nodename
= g_strdup_printf("/pl061@%" PRIx64
, base
);
980 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
981 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
983 qemu_fdt_setprop(ms
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
984 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#gpio-cells", 2);
985 qemu_fdt_setprop(ms
->fdt
, nodename
, "gpio-controller", NULL
, 0);
986 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
987 GIC_FDT_IRQ_TYPE_SPI
, irq
,
988 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
989 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "clocks", vms
->clock_phandle
);
990 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "clock-names", "apb_pclk");
991 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle", phandle
);
993 if (gpio
!= VIRT_GPIO
) {
994 /* Mark as not usable by the normal world */
995 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "status", "disabled");
996 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "secure-status", "okay");
1000 /* Child gpio devices */
1001 if (gpio
== VIRT_GPIO
) {
1002 create_gpio_keys(ms
->fdt
, pl061_dev
, phandle
);
1004 create_secure_gpio_pwr(ms
->fdt
, pl061_dev
, phandle
);
1008 static void create_virtio_devices(const VirtMachineState
*vms
)
1011 hwaddr size
= vms
->memmap
[VIRT_MMIO
].size
;
1012 MachineState
*ms
= MACHINE(vms
);
1014 /* We create the transports in forwards order. Since qbus_realize()
1015 * prepends (not appends) new child buses, the incrementing loop below will
1016 * create a list of virtio-mmio buses with decreasing base addresses.
1018 * When a -device option is processed from the command line,
1019 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards
1020 * order. The upshot is that -device options in increasing command line
1021 * order are mapped to virtio-mmio buses with decreasing base addresses.
1023 * When this code was originally written, that arrangement ensured that the
1024 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to
1025 * the first -device on the command line. (The end-to-end order is a
1026 * function of this loop, qbus_realize(), qbus_find_recursive(), and the
1027 * guest kernel's name-to-address assignment strategy.)
1029 * Meanwhile, the kernel's traversal seems to have been reversed; see eg.
1030 * the message, if not necessarily the code, of commit 70161ff336.
1031 * Therefore the loop now establishes the inverse of the original intent.
1033 * Unfortunately, we can't counteract the kernel change by reversing the
1034 * loop; it would break existing command lines.
1036 * In any case, the kernel makes no guarantee about the stability of
1037 * enumeration order of virtio devices (as demonstrated by it changing
1038 * between kernel versions). For reliable and stable identification
1039 * of disks users must use UUIDs or similar mechanisms.
1041 for (i
= 0; i
< NUM_VIRTIO_TRANSPORTS
; i
++) {
1042 int irq
= vms
->irqmap
[VIRT_MMIO
] + i
;
1043 hwaddr base
= vms
->memmap
[VIRT_MMIO
].base
+ i
* size
;
1045 sysbus_create_simple("virtio-mmio", base
,
1046 qdev_get_gpio_in(vms
->gic
, irq
));
1049 /* We add dtb nodes in reverse order so that they appear in the finished
1050 * device tree lowest address first.
1052 * Note that this mapping is independent of the loop above. The previous
1053 * loop influences virtio device to virtio transport assignment, whereas
1054 * this loop controls how virtio transports are laid out in the dtb.
1056 for (i
= NUM_VIRTIO_TRANSPORTS
- 1; i
>= 0; i
--) {
1058 int irq
= vms
->irqmap
[VIRT_MMIO
] + i
;
1059 hwaddr base
= vms
->memmap
[VIRT_MMIO
].base
+ i
* size
;
1061 nodename
= g_strdup_printf("/virtio_mmio@%" PRIx64
, base
);
1062 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1063 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
1064 "compatible", "virtio,mmio");
1065 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1067 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
1068 GIC_FDT_IRQ_TYPE_SPI
, irq
,
1069 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
);
1070 qemu_fdt_setprop(ms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1075 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
1077 static PFlashCFI01
*virt_flash_create1(VirtMachineState
*vms
,
1079 const char *alias_prop_name
)
1082 * Create a single flash device. We use the same parameters as
1083 * the flash devices on the Versatile Express board.
1085 DeviceState
*dev
= qdev_new(TYPE_PFLASH_CFI01
);
1087 qdev_prop_set_uint64(dev
, "sector-length", VIRT_FLASH_SECTOR_SIZE
);
1088 qdev_prop_set_uint8(dev
, "width", 4);
1089 qdev_prop_set_uint8(dev
, "device-width", 2);
1090 qdev_prop_set_bit(dev
, "big-endian", false);
1091 qdev_prop_set_uint16(dev
, "id0", 0x89);
1092 qdev_prop_set_uint16(dev
, "id1", 0x18);
1093 qdev_prop_set_uint16(dev
, "id2", 0x00);
1094 qdev_prop_set_uint16(dev
, "id3", 0x00);
1095 qdev_prop_set_string(dev
, "name", name
);
1096 object_property_add_child(OBJECT(vms
), name
, OBJECT(dev
));
1097 object_property_add_alias(OBJECT(vms
), alias_prop_name
,
1098 OBJECT(dev
), "drive");
1099 return PFLASH_CFI01(dev
);
1102 static void virt_flash_create(VirtMachineState
*vms
)
1104 vms
->flash
[0] = virt_flash_create1(vms
, "virt.flash0", "pflash0");
1105 vms
->flash
[1] = virt_flash_create1(vms
, "virt.flash1", "pflash1");
1108 static void virt_flash_map1(PFlashCFI01
*flash
,
1109 hwaddr base
, hwaddr size
,
1110 MemoryRegion
*sysmem
)
1112 DeviceState
*dev
= DEVICE(flash
);
1114 assert(QEMU_IS_ALIGNED(size
, VIRT_FLASH_SECTOR_SIZE
));
1115 assert(size
/ VIRT_FLASH_SECTOR_SIZE
<= UINT32_MAX
);
1116 qdev_prop_set_uint32(dev
, "num-blocks", size
/ VIRT_FLASH_SECTOR_SIZE
);
1117 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1119 memory_region_add_subregion(sysmem
, base
,
1120 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
),
1124 static void virt_flash_map(VirtMachineState
*vms
,
1125 MemoryRegion
*sysmem
,
1126 MemoryRegion
*secure_sysmem
)
1129 * Map two flash devices to fill the VIRT_FLASH space in the memmap.
1130 * sysmem is the system memory space. secure_sysmem is the secure view
1131 * of the system, and the first flash device should be made visible only
1132 * there. The second flash device is visible to both secure and nonsecure.
1133 * If sysmem == secure_sysmem this means there is no separate Secure
1134 * address space and both flash devices are generally visible.
1136 hwaddr flashsize
= vms
->memmap
[VIRT_FLASH
].size
/ 2;
1137 hwaddr flashbase
= vms
->memmap
[VIRT_FLASH
].base
;
1139 virt_flash_map1(vms
->flash
[0], flashbase
, flashsize
,
1141 virt_flash_map1(vms
->flash
[1], flashbase
+ flashsize
, flashsize
,
1145 static void virt_flash_fdt(VirtMachineState
*vms
,
1146 MemoryRegion
*sysmem
,
1147 MemoryRegion
*secure_sysmem
)
1149 hwaddr flashsize
= vms
->memmap
[VIRT_FLASH
].size
/ 2;
1150 hwaddr flashbase
= vms
->memmap
[VIRT_FLASH
].base
;
1151 MachineState
*ms
= MACHINE(vms
);
1154 if (sysmem
== secure_sysmem
) {
1155 /* Report both flash devices as a single node in the DT */
1156 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
1157 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1158 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible", "cfi-flash");
1159 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1160 2, flashbase
, 2, flashsize
,
1161 2, flashbase
+ flashsize
, 2, flashsize
);
1162 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "bank-width", 4);
1166 * Report the devices as separate nodes so we can mark one as
1167 * only visible to the secure world.
1169 nodename
= g_strdup_printf("/secflash@%" PRIx64
, flashbase
);
1170 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1171 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible", "cfi-flash");
1172 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1173 2, flashbase
, 2, flashsize
);
1174 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "bank-width", 4);
1175 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "status", "disabled");
1176 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "secure-status", "okay");
1179 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
1180 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1181 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible", "cfi-flash");
1182 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1183 2, flashbase
+ flashsize
, 2, flashsize
);
1184 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "bank-width", 4);
1189 static bool virt_firmware_init(VirtMachineState
*vms
,
1190 MemoryRegion
*sysmem
,
1191 MemoryRegion
*secure_sysmem
)
1194 const char *bios_name
;
1195 BlockBackend
*pflash_blk0
;
1197 /* Map legacy -drive if=pflash to machine properties */
1198 for (i
= 0; i
< ARRAY_SIZE(vms
->flash
); i
++) {
1199 pflash_cfi01_legacy_drive(vms
->flash
[i
],
1200 drive_get(IF_PFLASH
, 0, i
));
1203 virt_flash_map(vms
, sysmem
, secure_sysmem
);
1205 pflash_blk0
= pflash_cfi01_get_blk(vms
->flash
[0]);
1207 bios_name
= MACHINE(vms
)->firmware
;
1214 error_report("The contents of the first flash device may be "
1215 "specified with -bios or with -drive if=pflash... "
1216 "but you cannot use both options at once");
1220 /* Fall back to -bios */
1222 fname
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
1224 error_report("Could not find ROM image '%s'", bios_name
);
1227 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(vms
->flash
[0]), 0);
1228 image_size
= load_image_mr(fname
, mr
);
1230 if (image_size
< 0) {
1231 error_report("Could not load ROM image '%s'", bios_name
);
1236 return pflash_blk0
|| bios_name
;
1239 static FWCfgState
*create_fw_cfg(const VirtMachineState
*vms
, AddressSpace
*as
)
1241 MachineState
*ms
= MACHINE(vms
);
1242 hwaddr base
= vms
->memmap
[VIRT_FW_CFG
].base
;
1243 hwaddr size
= vms
->memmap
[VIRT_FW_CFG
].size
;
1247 fw_cfg
= fw_cfg_init_mem_wide(base
+ 8, base
, 8, base
+ 16, as
);
1248 fw_cfg_add_i16(fw_cfg
, FW_CFG_NB_CPUS
, (uint16_t)ms
->smp
.cpus
);
1250 nodename
= g_strdup_printf("/fw-cfg@%" PRIx64
, base
);
1251 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1252 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
1253 "compatible", "qemu,fw-cfg-mmio");
1254 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1256 qemu_fdt_setprop(ms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1261 static void create_pcie_irq_map(const MachineState
*ms
,
1262 uint32_t gic_phandle
,
1263 int first_irq
, const char *nodename
)
1266 uint32_t full_irq_map
[4 * 4 * 10] = { 0 };
1267 uint32_t *irq_map
= full_irq_map
;
1269 for (devfn
= 0; devfn
<= 0x18; devfn
+= 0x8) {
1270 for (pin
= 0; pin
< 4; pin
++) {
1271 int irq_type
= GIC_FDT_IRQ_TYPE_SPI
;
1272 int irq_nr
= first_irq
+ ((pin
+ PCI_SLOT(devfn
)) % PCI_NUM_PINS
);
1273 int irq_level
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
1277 devfn
<< 8, 0, 0, /* devfn */
1278 pin
+ 1, /* PCI pin */
1279 gic_phandle
, 0, 0, irq_type
, irq_nr
, irq_level
}; /* GIC irq */
1281 /* Convert map to big endian */
1282 for (i
= 0; i
< 10; i
++) {
1283 irq_map
[i
] = cpu_to_be32(map
[i
]);
1289 qemu_fdt_setprop(ms
->fdt
, nodename
, "interrupt-map",
1290 full_irq_map
, sizeof(full_irq_map
));
1292 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupt-map-mask",
1293 cpu_to_be16(PCI_DEVFN(3, 0)), /* Slot 3 */
1298 static void create_smmu(const VirtMachineState
*vms
,
1302 const char compat
[] = "arm,smmu-v3";
1303 int irq
= vms
->irqmap
[VIRT_SMMU
];
1305 hwaddr base
= vms
->memmap
[VIRT_SMMU
].base
;
1306 hwaddr size
= vms
->memmap
[VIRT_SMMU
].size
;
1307 const char irq_names
[] = "eventq\0priq\0cmdq-sync\0gerror";
1309 MachineState
*ms
= MACHINE(vms
);
1311 if (vms
->iommu
!= VIRT_IOMMU_SMMUV3
|| !vms
->iommu_phandle
) {
1315 dev
= qdev_new("arm-smmuv3");
1317 object_property_set_link(OBJECT(dev
), "primary-bus", OBJECT(bus
),
1319 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1320 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, base
);
1321 for (i
= 0; i
< NUM_SMMU_IRQS
; i
++) {
1322 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
1323 qdev_get_gpio_in(vms
->gic
, irq
+ i
));
1326 node
= g_strdup_printf("/smmuv3@%" PRIx64
, base
);
1327 qemu_fdt_add_subnode(ms
->fdt
, node
);
1328 qemu_fdt_setprop(ms
->fdt
, node
, "compatible", compat
, sizeof(compat
));
1329 qemu_fdt_setprop_sized_cells(ms
->fdt
, node
, "reg", 2, base
, 2, size
);
1331 qemu_fdt_setprop_cells(ms
->fdt
, node
, "interrupts",
1332 GIC_FDT_IRQ_TYPE_SPI
, irq
, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1333 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1334 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1335 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
);
1337 qemu_fdt_setprop(ms
->fdt
, node
, "interrupt-names", irq_names
,
1340 qemu_fdt_setprop_cell(ms
->fdt
, node
, "clocks", vms
->clock_phandle
);
1341 qemu_fdt_setprop_string(ms
->fdt
, node
, "clock-names", "apb_pclk");
1342 qemu_fdt_setprop(ms
->fdt
, node
, "dma-coherent", NULL
, 0);
1344 qemu_fdt_setprop_cell(ms
->fdt
, node
, "#iommu-cells", 1);
1346 qemu_fdt_setprop_cell(ms
->fdt
, node
, "phandle", vms
->iommu_phandle
);
1350 static void create_virtio_iommu_dt_bindings(VirtMachineState
*vms
)
1352 const char compat
[] = "virtio,pci-iommu";
1353 uint16_t bdf
= vms
->virtio_iommu_bdf
;
1354 MachineState
*ms
= MACHINE(vms
);
1357 vms
->iommu_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
1359 node
= g_strdup_printf("%s/virtio_iommu@%d", vms
->pciehb_nodename
, bdf
);
1360 qemu_fdt_add_subnode(ms
->fdt
, node
);
1361 qemu_fdt_setprop(ms
->fdt
, node
, "compatible", compat
, sizeof(compat
));
1362 qemu_fdt_setprop_sized_cells(ms
->fdt
, node
, "reg",
1363 1, bdf
<< 8, 1, 0, 1, 0,
1366 qemu_fdt_setprop_cell(ms
->fdt
, node
, "#iommu-cells", 1);
1367 qemu_fdt_setprop_cell(ms
->fdt
, node
, "phandle", vms
->iommu_phandle
);
1370 qemu_fdt_setprop_cells(ms
->fdt
, vms
->pciehb_nodename
, "iommu-map",
1371 0x0, vms
->iommu_phandle
, 0x0, bdf
,
1372 bdf
+ 1, vms
->iommu_phandle
, bdf
+ 1, 0xffff - bdf
);
1375 static void create_pcie(VirtMachineState
*vms
)
1377 hwaddr base_mmio
= vms
->memmap
[VIRT_PCIE_MMIO
].base
;
1378 hwaddr size_mmio
= vms
->memmap
[VIRT_PCIE_MMIO
].size
;
1379 hwaddr base_mmio_high
= vms
->memmap
[VIRT_HIGH_PCIE_MMIO
].base
;
1380 hwaddr size_mmio_high
= vms
->memmap
[VIRT_HIGH_PCIE_MMIO
].size
;
1381 hwaddr base_pio
= vms
->memmap
[VIRT_PCIE_PIO
].base
;
1382 hwaddr size_pio
= vms
->memmap
[VIRT_PCIE_PIO
].size
;
1383 hwaddr base_ecam
, size_ecam
;
1384 hwaddr base
= base_mmio
;
1386 int irq
= vms
->irqmap
[VIRT_PCIE
];
1387 MemoryRegion
*mmio_alias
;
1388 MemoryRegion
*mmio_reg
;
1389 MemoryRegion
*ecam_alias
;
1390 MemoryRegion
*ecam_reg
;
1395 MachineState
*ms
= MACHINE(vms
);
1397 dev
= qdev_new(TYPE_GPEX_HOST
);
1398 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1400 ecam_id
= VIRT_ECAM_ID(vms
->highmem_ecam
);
1401 base_ecam
= vms
->memmap
[ecam_id
].base
;
1402 size_ecam
= vms
->memmap
[ecam_id
].size
;
1403 nr_pcie_buses
= size_ecam
/ PCIE_MMCFG_SIZE_MIN
;
1404 /* Map only the first size_ecam bytes of ECAM space */
1405 ecam_alias
= g_new0(MemoryRegion
, 1);
1406 ecam_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0);
1407 memory_region_init_alias(ecam_alias
, OBJECT(dev
), "pcie-ecam",
1408 ecam_reg
, 0, size_ecam
);
1409 memory_region_add_subregion(get_system_memory(), base_ecam
, ecam_alias
);
1411 /* Map the MMIO window into system address space so as to expose
1412 * the section of PCI MMIO space which starts at the same base address
1413 * (ie 1:1 mapping for that part of PCI MMIO space visible through
1416 mmio_alias
= g_new0(MemoryRegion
, 1);
1417 mmio_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 1);
1418 memory_region_init_alias(mmio_alias
, OBJECT(dev
), "pcie-mmio",
1419 mmio_reg
, base_mmio
, size_mmio
);
1420 memory_region_add_subregion(get_system_memory(), base_mmio
, mmio_alias
);
1422 if (vms
->highmem_mmio
) {
1423 /* Map high MMIO space */
1424 MemoryRegion
*high_mmio_alias
= g_new0(MemoryRegion
, 1);
1426 memory_region_init_alias(high_mmio_alias
, OBJECT(dev
), "pcie-mmio-high",
1427 mmio_reg
, base_mmio_high
, size_mmio_high
);
1428 memory_region_add_subregion(get_system_memory(), base_mmio_high
,
1432 /* Map IO port space */
1433 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 2, base_pio
);
1435 for (i
= 0; i
< GPEX_NUM_IRQS
; i
++) {
1436 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
1437 qdev_get_gpio_in(vms
->gic
, irq
+ i
));
1438 gpex_set_irq_num(GPEX_HOST(dev
), i
, irq
+ i
);
1441 pci
= PCI_HOST_BRIDGE(dev
);
1442 pci
->bypass_iommu
= vms
->default_bus_bypass_iommu
;
1443 vms
->bus
= pci
->bus
;
1445 for (i
= 0; i
< nb_nics
; i
++) {
1446 NICInfo
*nd
= &nd_table
[i
];
1449 nd
->model
= g_strdup("virtio");
1452 pci_nic_init_nofail(nd
, pci
->bus
, nd
->model
, NULL
);
1456 nodename
= vms
->pciehb_nodename
= g_strdup_printf("/pcie@%" PRIx64
, base
);
1457 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1458 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
1459 "compatible", "pci-host-ecam-generic");
1460 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "device_type", "pci");
1461 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#address-cells", 3);
1462 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#size-cells", 2);
1463 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "linux,pci-domain", 0);
1464 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "bus-range", 0,
1466 qemu_fdt_setprop(ms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1468 if (vms
->msi_phandle
) {
1469 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "msi-parent",
1473 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1474 2, base_ecam
, 2, size_ecam
);
1476 if (vms
->highmem_mmio
) {
1477 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "ranges",
1478 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
1479 2, base_pio
, 2, size_pio
,
1480 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
1481 2, base_mmio
, 2, size_mmio
,
1482 1, FDT_PCI_RANGE_MMIO_64BIT
,
1484 2, base_mmio_high
, 2, size_mmio_high
);
1486 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "ranges",
1487 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
1488 2, base_pio
, 2, size_pio
,
1489 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
1490 2, base_mmio
, 2, size_mmio
);
1493 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#interrupt-cells", 1);
1494 create_pcie_irq_map(ms
, vms
->gic_phandle
, irq
, nodename
);
1497 vms
->iommu_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
1499 switch (vms
->iommu
) {
1500 case VIRT_IOMMU_SMMUV3
:
1501 create_smmu(vms
, vms
->bus
);
1502 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "iommu-map",
1503 0x0, vms
->iommu_phandle
, 0x0, 0x10000);
1506 g_assert_not_reached();
1511 static void create_platform_bus(VirtMachineState
*vms
)
1516 MemoryRegion
*sysmem
= get_system_memory();
1518 dev
= qdev_new(TYPE_PLATFORM_BUS_DEVICE
);
1519 dev
->id
= g_strdup(TYPE_PLATFORM_BUS_DEVICE
);
1520 qdev_prop_set_uint32(dev
, "num_irqs", PLATFORM_BUS_NUM_IRQS
);
1521 qdev_prop_set_uint32(dev
, "mmio_size", vms
->memmap
[VIRT_PLATFORM_BUS
].size
);
1522 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1523 vms
->platform_bus_dev
= dev
;
1525 s
= SYS_BUS_DEVICE(dev
);
1526 for (i
= 0; i
< PLATFORM_BUS_NUM_IRQS
; i
++) {
1527 int irq
= vms
->irqmap
[VIRT_PLATFORM_BUS
] + i
;
1528 sysbus_connect_irq(s
, i
, qdev_get_gpio_in(vms
->gic
, irq
));
1531 memory_region_add_subregion(sysmem
,
1532 vms
->memmap
[VIRT_PLATFORM_BUS
].base
,
1533 sysbus_mmio_get_region(s
, 0));
1536 static void create_tag_ram(MemoryRegion
*tag_sysmem
,
1537 hwaddr base
, hwaddr size
,
1540 MemoryRegion
*tagram
= g_new(MemoryRegion
, 1);
1542 memory_region_init_ram(tagram
, NULL
, name
, size
/ 32, &error_fatal
);
1543 memory_region_add_subregion(tag_sysmem
, base
/ 32, tagram
);
1546 static void create_secure_ram(VirtMachineState
*vms
,
1547 MemoryRegion
*secure_sysmem
,
1548 MemoryRegion
*secure_tag_sysmem
)
1550 MemoryRegion
*secram
= g_new(MemoryRegion
, 1);
1552 hwaddr base
= vms
->memmap
[VIRT_SECURE_MEM
].base
;
1553 hwaddr size
= vms
->memmap
[VIRT_SECURE_MEM
].size
;
1554 MachineState
*ms
= MACHINE(vms
);
1556 memory_region_init_ram(secram
, NULL
, "virt.secure-ram", size
,
1558 memory_region_add_subregion(secure_sysmem
, base
, secram
);
1560 nodename
= g_strdup_printf("/secram@%" PRIx64
, base
);
1561 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1562 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "device_type", "memory");
1563 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg", 2, base
, 2, size
);
1564 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "status", "disabled");
1565 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "secure-status", "okay");
1567 if (secure_tag_sysmem
) {
1568 create_tag_ram(secure_tag_sysmem
, base
, size
, "mach-virt.secure-tag");
1574 static void *machvirt_dtb(const struct arm_boot_info
*binfo
, int *fdt_size
)
1576 const VirtMachineState
*board
= container_of(binfo
, VirtMachineState
,
1578 MachineState
*ms
= MACHINE(board
);
1581 *fdt_size
= board
->fdt_size
;
1585 static void virt_build_smbios(VirtMachineState
*vms
)
1587 MachineClass
*mc
= MACHINE_GET_CLASS(vms
);
1588 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
1589 uint8_t *smbios_tables
, *smbios_anchor
;
1590 size_t smbios_tables_len
, smbios_anchor_len
;
1591 const char *product
= "QEMU Virtual Machine";
1593 if (kvm_enabled()) {
1594 product
= "KVM Virtual Machine";
1597 smbios_set_defaults("QEMU", product
,
1598 vmc
->smbios_old_sys_ver
? "1.0" : mc
->name
, false,
1599 true, SMBIOS_ENTRY_POINT_TYPE_64
);
1601 smbios_get_tables(MACHINE(vms
), NULL
, 0,
1602 &smbios_tables
, &smbios_tables_len
,
1603 &smbios_anchor
, &smbios_anchor_len
,
1606 if (smbios_anchor
) {
1607 fw_cfg_add_file(vms
->fw_cfg
, "etc/smbios/smbios-tables",
1608 smbios_tables
, smbios_tables_len
);
1609 fw_cfg_add_file(vms
->fw_cfg
, "etc/smbios/smbios-anchor",
1610 smbios_anchor
, smbios_anchor_len
);
1615 void virt_machine_done(Notifier
*notifier
, void *data
)
1617 VirtMachineState
*vms
= container_of(notifier
, VirtMachineState
,
1619 MachineState
*ms
= MACHINE(vms
);
1620 ARMCPU
*cpu
= ARM_CPU(first_cpu
);
1621 struct arm_boot_info
*info
= &vms
->bootinfo
;
1622 AddressSpace
*as
= arm_boot_address_space(cpu
, info
);
1625 * If the user provided a dtb, we assume the dynamic sysbus nodes
1626 * already are integrated there. This corresponds to a use case where
1627 * the dynamic sysbus nodes are complex and their generation is not yet
1628 * supported. In that case the user can take charge of the guest dt
1629 * while qemu takes charge of the qom stuff.
1631 if (info
->dtb_filename
== NULL
) {
1632 platform_bus_add_all_fdt_nodes(ms
->fdt
, "/intc",
1633 vms
->memmap
[VIRT_PLATFORM_BUS
].base
,
1634 vms
->memmap
[VIRT_PLATFORM_BUS
].size
,
1635 vms
->irqmap
[VIRT_PLATFORM_BUS
]);
1637 if (arm_load_dtb(info
->dtb_start
, info
, info
->dtb_limit
, as
, ms
) < 0) {
1641 fw_cfg_add_extra_pci_roots(vms
->bus
, vms
->fw_cfg
);
1643 virt_acpi_setup(vms
);
1644 virt_build_smbios(vms
);
1647 static uint64_t virt_cpu_mp_affinity(VirtMachineState
*vms
, int idx
)
1649 uint8_t clustersz
= ARM_DEFAULT_CPUS_PER_CLUSTER
;
1650 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
1652 if (!vmc
->disallow_affinity_adjustment
) {
1653 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the
1654 * GIC's target-list limitations. 32-bit KVM hosts currently
1655 * always create clusters of 4 CPUs, but that is expected to
1656 * change when they gain support for gicv3. When KVM is enabled
1657 * it will override the changes we make here, therefore our
1658 * purposes are to make TCG consistent (with 64-bit KVM hosts)
1659 * and to improve SGI efficiency.
1661 if (vms
->gic_version
== VIRT_GIC_VERSION_3
) {
1662 clustersz
= GICV3_TARGETLIST_BITS
;
1664 clustersz
= GIC_TARGETLIST_BITS
;
1667 return arm_cpu_mp_affinity(idx
, clustersz
);
1670 static void virt_set_memmap(VirtMachineState
*vms
, int pa_bits
)
1672 MachineState
*ms
= MACHINE(vms
);
1673 hwaddr base
, device_memory_base
, device_memory_size
, memtop
;
1676 vms
->memmap
= extended_memmap
;
1678 for (i
= 0; i
< ARRAY_SIZE(base_memmap
); i
++) {
1679 vms
->memmap
[i
] = base_memmap
[i
];
1682 if (ms
->ram_slots
> ACPI_MAX_RAM_SLOTS
) {
1683 error_report("unsupported number of memory slots: %"PRIu64
,
1689 * !highmem is exactly the same as limiting the PA space to 32bit,
1690 * irrespective of the underlying capabilities of the HW.
1692 if (!vms
->highmem
) {
1697 * We compute the base of the high IO region depending on the
1698 * amount of initial and device memory. The device memory start/size
1699 * is aligned on 1GiB. We never put the high IO region below 256GiB
1700 * so that if maxram_size is < 255GiB we keep the legacy memory map.
1701 * The device region size assumes 1GiB page max alignment per slot.
1703 device_memory_base
=
1704 ROUND_UP(vms
->memmap
[VIRT_MEM
].base
+ ms
->ram_size
, GiB
);
1705 device_memory_size
= ms
->maxram_size
- ms
->ram_size
+ ms
->ram_slots
* GiB
;
1707 /* Base address of the high IO region */
1708 memtop
= base
= device_memory_base
+ ROUND_UP(device_memory_size
, GiB
);
1709 if (memtop
> BIT_ULL(pa_bits
)) {
1710 error_report("Addressing limited to %d bits, but memory exceeds it by %llu bytes\n",
1711 pa_bits
, memtop
- BIT_ULL(pa_bits
));
1714 if (base
< device_memory_base
) {
1715 error_report("maxmem/slots too huge");
1718 if (base
< vms
->memmap
[VIRT_MEM
].base
+ LEGACY_RAMLIMIT_BYTES
) {
1719 base
= vms
->memmap
[VIRT_MEM
].base
+ LEGACY_RAMLIMIT_BYTES
;
1722 /* We know for sure that at least the memory fits in the PA space */
1723 vms
->highest_gpa
= memtop
- 1;
1725 for (i
= VIRT_LOWMEMMAP_LAST
; i
< ARRAY_SIZE(extended_memmap
); i
++) {
1726 hwaddr size
= extended_memmap
[i
].size
;
1729 base
= ROUND_UP(base
, size
);
1730 vms
->memmap
[i
].base
= base
;
1731 vms
->memmap
[i
].size
= size
;
1734 * Check each device to see if they fit in the PA space,
1735 * moving highest_gpa as we go.
1737 * For each device that doesn't fit, disable it.
1739 fits
= (base
+ size
) <= BIT_ULL(pa_bits
);
1741 vms
->highest_gpa
= base
+ size
- 1;
1745 case VIRT_HIGH_GIC_REDIST2
:
1746 vms
->highmem_redists
&= fits
;
1748 case VIRT_HIGH_PCIE_ECAM
:
1749 vms
->highmem_ecam
&= fits
;
1751 case VIRT_HIGH_PCIE_MMIO
:
1752 vms
->highmem_mmio
&= fits
;
1759 if (device_memory_size
> 0) {
1760 ms
->device_memory
= g_malloc0(sizeof(*ms
->device_memory
));
1761 ms
->device_memory
->base
= device_memory_base
;
1762 memory_region_init(&ms
->device_memory
->mr
, OBJECT(vms
),
1763 "device-memory", device_memory_size
);
1768 * finalize_gic_version - Determines the final gic_version
1769 * according to the gic-version property
1771 * Default GIC type is v2
1773 static void finalize_gic_version(VirtMachineState
*vms
)
1775 unsigned int max_cpus
= MACHINE(vms
)->smp
.max_cpus
;
1777 if (kvm_enabled()) {
1780 if (!kvm_irqchip_in_kernel()) {
1781 switch (vms
->gic_version
) {
1782 case VIRT_GIC_VERSION_HOST
:
1784 "gic-version=host not relevant with kernel-irqchip=off "
1785 "as only userspace GICv2 is supported. Using v2 ...");
1787 case VIRT_GIC_VERSION_MAX
:
1788 case VIRT_GIC_VERSION_NOSEL
:
1789 vms
->gic_version
= VIRT_GIC_VERSION_2
;
1791 case VIRT_GIC_VERSION_2
:
1793 case VIRT_GIC_VERSION_3
:
1795 "gic-version=3 is not supported with kernel-irqchip=off");
1800 probe_bitmap
= kvm_arm_vgic_probe();
1801 if (!probe_bitmap
) {
1802 error_report("Unable to determine GIC version supported by host");
1806 switch (vms
->gic_version
) {
1807 case VIRT_GIC_VERSION_HOST
:
1808 case VIRT_GIC_VERSION_MAX
:
1809 if (probe_bitmap
& KVM_ARM_VGIC_V3
) {
1810 vms
->gic_version
= VIRT_GIC_VERSION_3
;
1812 vms
->gic_version
= VIRT_GIC_VERSION_2
;
1815 case VIRT_GIC_VERSION_NOSEL
:
1816 if ((probe_bitmap
& KVM_ARM_VGIC_V2
) && max_cpus
<= GIC_NCPU
) {
1817 vms
->gic_version
= VIRT_GIC_VERSION_2
;
1818 } else if (probe_bitmap
& KVM_ARM_VGIC_V3
) {
1820 * in case the host does not support v2 in-kernel emulation or
1821 * the end-user requested more than 8 VCPUs we now default
1822 * to v3. In any case defaulting to v2 would be broken.
1824 vms
->gic_version
= VIRT_GIC_VERSION_3
;
1825 } else if (max_cpus
> GIC_NCPU
) {
1826 error_report("host only supports in-kernel GICv2 emulation "
1827 "but more than 8 vcpus are requested");
1831 case VIRT_GIC_VERSION_2
:
1832 case VIRT_GIC_VERSION_3
:
1836 /* Check chosen version is effectively supported by the host */
1837 if (vms
->gic_version
== VIRT_GIC_VERSION_2
&&
1838 !(probe_bitmap
& KVM_ARM_VGIC_V2
)) {
1839 error_report("host does not support in-kernel GICv2 emulation");
1841 } else if (vms
->gic_version
== VIRT_GIC_VERSION_3
&&
1842 !(probe_bitmap
& KVM_ARM_VGIC_V3
)) {
1843 error_report("host does not support in-kernel GICv3 emulation");
1850 switch (vms
->gic_version
) {
1851 case VIRT_GIC_VERSION_NOSEL
:
1852 vms
->gic_version
= VIRT_GIC_VERSION_2
;
1854 case VIRT_GIC_VERSION_MAX
:
1855 vms
->gic_version
= VIRT_GIC_VERSION_3
;
1857 case VIRT_GIC_VERSION_HOST
:
1858 error_report("gic-version=host requires KVM");
1860 case VIRT_GIC_VERSION_2
:
1861 case VIRT_GIC_VERSION_3
:
1867 * virt_cpu_post_init() must be called after the CPUs have
1868 * been realized and the GIC has been created.
1870 static void virt_cpu_post_init(VirtMachineState
*vms
, MemoryRegion
*sysmem
)
1872 int max_cpus
= MACHINE(vms
)->smp
.max_cpus
;
1873 bool aarch64
, pmu
, steal_time
;
1876 aarch64
= object_property_get_bool(OBJECT(first_cpu
), "aarch64", NULL
);
1877 pmu
= object_property_get_bool(OBJECT(first_cpu
), "pmu", NULL
);
1878 steal_time
= object_property_get_bool(OBJECT(first_cpu
),
1879 "kvm-steal-time", NULL
);
1881 if (kvm_enabled()) {
1882 hwaddr pvtime_reg_base
= vms
->memmap
[VIRT_PVTIME
].base
;
1883 hwaddr pvtime_reg_size
= vms
->memmap
[VIRT_PVTIME
].size
;
1886 MemoryRegion
*pvtime
= g_new(MemoryRegion
, 1);
1887 hwaddr pvtime_size
= max_cpus
* PVTIME_SIZE_PER_CPU
;
1889 /* The memory region size must be a multiple of host page size. */
1890 pvtime_size
= REAL_HOST_PAGE_ALIGN(pvtime_size
);
1892 if (pvtime_size
> pvtime_reg_size
) {
1893 error_report("pvtime requires a %" HWADDR_PRId
1894 " byte memory region for %d CPUs,"
1895 " but only %" HWADDR_PRId
" has been reserved",
1896 pvtime_size
, max_cpus
, pvtime_reg_size
);
1900 memory_region_init_ram(pvtime
, NULL
, "pvtime", pvtime_size
, NULL
);
1901 memory_region_add_subregion(sysmem
, pvtime_reg_base
, pvtime
);
1906 assert(arm_feature(&ARM_CPU(cpu
)->env
, ARM_FEATURE_PMU
));
1907 if (kvm_irqchip_in_kernel()) {
1908 kvm_arm_pmu_set_irq(cpu
, PPI(VIRTUAL_PMU_IRQ
));
1910 kvm_arm_pmu_init(cpu
);
1913 kvm_arm_pvtime_init(cpu
, pvtime_reg_base
+
1914 cpu
->cpu_index
* PVTIME_SIZE_PER_CPU
);
1918 if (aarch64
&& vms
->highmem
) {
1919 int requested_pa_size
= 64 - clz64(vms
->highest_gpa
);
1920 int pamax
= arm_pamax(ARM_CPU(first_cpu
));
1922 if (pamax
< requested_pa_size
) {
1923 error_report("VCPU supports less PA bits (%d) than "
1924 "requested by the memory map (%d)",
1925 pamax
, requested_pa_size
);
1932 static void machvirt_init(MachineState
*machine
)
1934 VirtMachineState
*vms
= VIRT_MACHINE(machine
);
1935 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(machine
);
1936 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
1937 const CPUArchIdList
*possible_cpus
;
1938 MemoryRegion
*sysmem
= get_system_memory();
1939 MemoryRegion
*secure_sysmem
= NULL
;
1940 MemoryRegion
*tag_sysmem
= NULL
;
1941 MemoryRegion
*secure_tag_sysmem
= NULL
;
1942 int n
, virt_max_cpus
;
1943 bool firmware_loaded
;
1944 bool aarch64
= true;
1945 bool has_ged
= !vmc
->no_ged
;
1946 unsigned int smp_cpus
= machine
->smp
.cpus
;
1947 unsigned int max_cpus
= machine
->smp
.max_cpus
;
1949 if (!cpu_type_valid(machine
->cpu_type
)) {
1950 error_report("mach-virt: CPU type %s not supported", machine
->cpu_type
);
1954 possible_cpus
= mc
->possible_cpu_arch_ids(machine
);
1957 * In accelerated mode, the memory map is computed earlier in kvm_type()
1958 * to create a VM with the right number of IPA bits.
1966 * Instanciate a temporary CPU object to find out about what
1967 * we are about to deal with. Once this is done, get rid of
1970 cpuobj
= object_new(possible_cpus
->cpus
[0].type
);
1971 armcpu
= ARM_CPU(cpuobj
);
1973 if (object_property_get_bool(cpuobj
, "aarch64", NULL
)) {
1974 pa_bits
= arm_pamax(armcpu
);
1975 } else if (arm_feature(&armcpu
->env
, ARM_FEATURE_LPAE
)) {
1983 object_unref(cpuobj
);
1985 virt_set_memmap(vms
, pa_bits
);
1988 /* We can probe only here because during property set
1989 * KVM is not available yet
1991 finalize_gic_version(vms
);
1995 * The Secure view of the world is the same as the NonSecure,
1996 * but with a few extra devices. Create it as a container region
1997 * containing the system memory at low priority; any secure-only
1998 * devices go in at higher priority and take precedence.
2000 secure_sysmem
= g_new(MemoryRegion
, 1);
2001 memory_region_init(secure_sysmem
, OBJECT(machine
), "secure-memory",
2003 memory_region_add_subregion_overlap(secure_sysmem
, 0, sysmem
, -1);
2006 firmware_loaded
= virt_firmware_init(vms
, sysmem
,
2007 secure_sysmem
?: sysmem
);
2009 /* If we have an EL3 boot ROM then the assumption is that it will
2010 * implement PSCI itself, so disable QEMU's internal implementation
2011 * so it doesn't get in the way. Instead of starting secondary
2012 * CPUs in PSCI powerdown state we will start them all running and
2013 * let the boot ROM sort them out.
2014 * The usual case is that we do use QEMU's PSCI implementation;
2015 * if the guest has EL2 then we will use SMC as the conduit,
2016 * and otherwise we will use HVC (for backwards compatibility and
2017 * because if we're using KVM then we must use HVC).
2019 if (vms
->secure
&& firmware_loaded
) {
2020 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_DISABLED
;
2021 } else if (vms
->virt
) {
2022 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_SMC
;
2024 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_HVC
;
2027 /* The maximum number of CPUs depends on the GIC version, or on how
2028 * many redistributors we can fit into the memory map.
2030 if (vms
->gic_version
== VIRT_GIC_VERSION_3
) {
2032 vms
->memmap
[VIRT_GIC_REDIST
].size
/ GICV3_REDIST_SIZE
;
2034 vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].size
/ GICV3_REDIST_SIZE
;
2036 virt_max_cpus
= GIC_NCPU
;
2039 if (max_cpus
> virt_max_cpus
) {
2040 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
2041 "supported by machine 'mach-virt' (%d)",
2042 max_cpus
, virt_max_cpus
);
2046 if (vms
->virt
&& (kvm_enabled() || hvf_enabled())) {
2047 error_report("mach-virt: %s does not support providing "
2048 "Virtualization extensions to the guest CPU",
2049 kvm_enabled() ? "KVM" : "HVF");
2053 if (vms
->mte
&& (kvm_enabled() || hvf_enabled())) {
2054 error_report("mach-virt: %s does not support providing "
2055 "MTE to the guest CPU",
2056 kvm_enabled() ? "KVM" : "HVF");
2062 assert(possible_cpus
->len
== max_cpus
);
2063 for (n
= 0; n
< possible_cpus
->len
; n
++) {
2067 if (n
>= smp_cpus
) {
2071 cpuobj
= object_new(possible_cpus
->cpus
[n
].type
);
2072 object_property_set_int(cpuobj
, "mp-affinity",
2073 possible_cpus
->cpus
[n
].arch_id
, NULL
);
2078 numa_cpu_pre_plug(&possible_cpus
->cpus
[cs
->cpu_index
], DEVICE(cpuobj
),
2081 aarch64
&= object_property_get_bool(cpuobj
, "aarch64", NULL
);
2084 object_property_set_bool(cpuobj
, "has_el3", false, NULL
);
2087 if (!vms
->virt
&& object_property_find(cpuobj
, "has_el2")) {
2088 object_property_set_bool(cpuobj
, "has_el2", false, NULL
);
2091 if (vmc
->kvm_no_adjvtime
&&
2092 object_property_find(cpuobj
, "kvm-no-adjvtime")) {
2093 object_property_set_bool(cpuobj
, "kvm-no-adjvtime", true, NULL
);
2096 if (vmc
->no_kvm_steal_time
&&
2097 object_property_find(cpuobj
, "kvm-steal-time")) {
2098 object_property_set_bool(cpuobj
, "kvm-steal-time", false, NULL
);
2101 if (vmc
->no_pmu
&& object_property_find(cpuobj
, "pmu")) {
2102 object_property_set_bool(cpuobj
, "pmu", false, NULL
);
2105 if (object_property_find(cpuobj
, "reset-cbar")) {
2106 object_property_set_int(cpuobj
, "reset-cbar",
2107 vms
->memmap
[VIRT_CPUPERIPHS
].base
,
2111 object_property_set_link(cpuobj
, "memory", OBJECT(sysmem
),
2114 object_property_set_link(cpuobj
, "secure-memory",
2115 OBJECT(secure_sysmem
), &error_abort
);
2119 /* Create the memory region only once, but link to all cpus. */
2122 * The property exists only if MemTag is supported.
2123 * If it is, we must allocate the ram to back that up.
2125 if (!object_property_find(cpuobj
, "tag-memory")) {
2126 error_report("MTE requested, but not supported "
2127 "by the guest CPU");
2131 tag_sysmem
= g_new(MemoryRegion
, 1);
2132 memory_region_init(tag_sysmem
, OBJECT(machine
),
2133 "tag-memory", UINT64_MAX
/ 32);
2136 secure_tag_sysmem
= g_new(MemoryRegion
, 1);
2137 memory_region_init(secure_tag_sysmem
, OBJECT(machine
),
2138 "secure-tag-memory", UINT64_MAX
/ 32);
2140 /* As with ram, secure-tag takes precedence over tag. */
2141 memory_region_add_subregion_overlap(secure_tag_sysmem
, 0,
2146 object_property_set_link(cpuobj
, "tag-memory", OBJECT(tag_sysmem
),
2149 object_property_set_link(cpuobj
, "secure-tag-memory",
2150 OBJECT(secure_tag_sysmem
),
2155 qdev_realize(DEVICE(cpuobj
), NULL
, &error_fatal
);
2156 object_unref(cpuobj
);
2158 fdt_add_timer_nodes(vms
);
2159 fdt_add_cpu_nodes(vms
);
2161 memory_region_add_subregion(sysmem
, vms
->memmap
[VIRT_MEM
].base
,
2163 if (machine
->device_memory
) {
2164 memory_region_add_subregion(sysmem
, machine
->device_memory
->base
,
2165 &machine
->device_memory
->mr
);
2168 virt_flash_fdt(vms
, sysmem
, secure_sysmem
?: sysmem
);
2170 create_gic(vms
, sysmem
);
2172 virt_cpu_post_init(vms
, sysmem
);
2174 fdt_add_pmu_nodes(vms
);
2176 create_uart(vms
, VIRT_UART
, sysmem
, serial_hd(0));
2179 create_secure_ram(vms
, secure_sysmem
, secure_tag_sysmem
);
2180 create_uart(vms
, VIRT_SECURE_UART
, secure_sysmem
, serial_hd(1));
2184 create_tag_ram(tag_sysmem
, vms
->memmap
[VIRT_MEM
].base
,
2185 machine
->ram_size
, "mach-virt.tag");
2188 vms
->highmem_ecam
&= (!firmware_loaded
|| aarch64
);
2194 if (has_ged
&& aarch64
&& firmware_loaded
&& virt_is_acpi_enabled(vms
)) {
2195 vms
->acpi_dev
= create_acpi_ged(vms
);
2197 create_gpio_devices(vms
, VIRT_GPIO
, sysmem
);
2200 if (vms
->secure
&& !vmc
->no_secure_gpio
) {
2201 create_gpio_devices(vms
, VIRT_SECURE_GPIO
, secure_sysmem
);
2204 /* connect powerdown request */
2205 vms
->powerdown_notifier
.notify
= virt_powerdown_req
;
2206 qemu_register_powerdown_notifier(&vms
->powerdown_notifier
);
2208 /* Create mmio transports, so the user can create virtio backends
2209 * (which will be automatically plugged in to the transports). If
2210 * no backend is created the transport will just sit harmlessly idle.
2212 create_virtio_devices(vms
);
2214 vms
->fw_cfg
= create_fw_cfg(vms
, &address_space_memory
);
2215 rom_set_fw(vms
->fw_cfg
);
2217 create_platform_bus(vms
);
2219 if (machine
->nvdimms_state
->is_enabled
) {
2220 const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio
= {
2221 .space_id
= AML_AS_SYSTEM_MEMORY
,
2222 .address
= vms
->memmap
[VIRT_NVDIMM_ACPI
].base
,
2223 .bit_width
= NVDIMM_ACPI_IO_LEN
<< 3
2226 nvdimm_init_acpi_state(machine
->nvdimms_state
, sysmem
,
2227 arm_virt_nvdimm_acpi_dsmio
,
2228 vms
->fw_cfg
, OBJECT(vms
));
2231 vms
->bootinfo
.ram_size
= machine
->ram_size
;
2232 vms
->bootinfo
.board_id
= -1;
2233 vms
->bootinfo
.loader_start
= vms
->memmap
[VIRT_MEM
].base
;
2234 vms
->bootinfo
.get_dtb
= machvirt_dtb
;
2235 vms
->bootinfo
.skip_dtb_autoload
= true;
2236 vms
->bootinfo
.firmware_loaded
= firmware_loaded
;
2237 vms
->bootinfo
.psci_conduit
= vms
->psci_conduit
;
2238 arm_load_kernel(ARM_CPU(first_cpu
), machine
, &vms
->bootinfo
);
2240 vms
->machine_done
.notify
= virt_machine_done
;
2241 qemu_add_machine_init_done_notifier(&vms
->machine_done
);
2244 static bool virt_get_secure(Object
*obj
, Error
**errp
)
2246 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2251 static void virt_set_secure(Object
*obj
, bool value
, Error
**errp
)
2253 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2255 vms
->secure
= value
;
2258 static bool virt_get_virt(Object
*obj
, Error
**errp
)
2260 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2265 static void virt_set_virt(Object
*obj
, bool value
, Error
**errp
)
2267 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2272 static bool virt_get_highmem(Object
*obj
, Error
**errp
)
2274 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2276 return vms
->highmem
;
2279 static void virt_set_highmem(Object
*obj
, bool value
, Error
**errp
)
2281 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2283 vms
->highmem
= value
;
2286 static bool virt_get_its(Object
*obj
, Error
**errp
)
2288 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2293 static void virt_set_its(Object
*obj
, bool value
, Error
**errp
)
2295 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2300 static bool virt_get_dtb_kaslr_seed(Object
*obj
, Error
**errp
)
2302 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2304 return vms
->dtb_kaslr_seed
;
2307 static void virt_set_dtb_kaslr_seed(Object
*obj
, bool value
, Error
**errp
)
2309 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2311 vms
->dtb_kaslr_seed
= value
;
2314 static char *virt_get_oem_id(Object
*obj
, Error
**errp
)
2316 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2318 return g_strdup(vms
->oem_id
);
2321 static void virt_set_oem_id(Object
*obj
, const char *value
, Error
**errp
)
2323 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2324 size_t len
= strlen(value
);
2328 "User specified oem-id value is bigger than 6 bytes in size");
2332 strncpy(vms
->oem_id
, value
, 6);
2335 static char *virt_get_oem_table_id(Object
*obj
, Error
**errp
)
2337 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2339 return g_strdup(vms
->oem_table_id
);
2342 static void virt_set_oem_table_id(Object
*obj
, const char *value
,
2345 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2346 size_t len
= strlen(value
);
2350 "User specified oem-table-id value is bigger than 8 bytes in size");
2353 strncpy(vms
->oem_table_id
, value
, 8);
2357 bool virt_is_acpi_enabled(VirtMachineState
*vms
)
2359 if (vms
->acpi
== ON_OFF_AUTO_OFF
) {
2365 static void virt_get_acpi(Object
*obj
, Visitor
*v
, const char *name
,
2366 void *opaque
, Error
**errp
)
2368 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2369 OnOffAuto acpi
= vms
->acpi
;
2371 visit_type_OnOffAuto(v
, name
, &acpi
, errp
);
2374 static void virt_set_acpi(Object
*obj
, Visitor
*v
, const char *name
,
2375 void *opaque
, Error
**errp
)
2377 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2379 visit_type_OnOffAuto(v
, name
, &vms
->acpi
, errp
);
2382 static bool virt_get_ras(Object
*obj
, Error
**errp
)
2384 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2389 static void virt_set_ras(Object
*obj
, bool value
, Error
**errp
)
2391 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2396 static bool virt_get_mte(Object
*obj
, Error
**errp
)
2398 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2403 static void virt_set_mte(Object
*obj
, bool value
, Error
**errp
)
2405 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2410 static char *virt_get_gic_version(Object
*obj
, Error
**errp
)
2412 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2413 const char *val
= vms
->gic_version
== VIRT_GIC_VERSION_3
? "3" : "2";
2415 return g_strdup(val
);
2418 static void virt_set_gic_version(Object
*obj
, const char *value
, Error
**errp
)
2420 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2422 if (!strcmp(value
, "3")) {
2423 vms
->gic_version
= VIRT_GIC_VERSION_3
;
2424 } else if (!strcmp(value
, "2")) {
2425 vms
->gic_version
= VIRT_GIC_VERSION_2
;
2426 } else if (!strcmp(value
, "host")) {
2427 vms
->gic_version
= VIRT_GIC_VERSION_HOST
; /* Will probe later */
2428 } else if (!strcmp(value
, "max")) {
2429 vms
->gic_version
= VIRT_GIC_VERSION_MAX
; /* Will probe later */
2431 error_setg(errp
, "Invalid gic-version value");
2432 error_append_hint(errp
, "Valid values are 3, 2, host, max.\n");
2436 static char *virt_get_iommu(Object
*obj
, Error
**errp
)
2438 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2440 switch (vms
->iommu
) {
2441 case VIRT_IOMMU_NONE
:
2442 return g_strdup("none");
2443 case VIRT_IOMMU_SMMUV3
:
2444 return g_strdup("smmuv3");
2446 g_assert_not_reached();
2450 static void virt_set_iommu(Object
*obj
, const char *value
, Error
**errp
)
2452 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2454 if (!strcmp(value
, "smmuv3")) {
2455 vms
->iommu
= VIRT_IOMMU_SMMUV3
;
2456 } else if (!strcmp(value
, "none")) {
2457 vms
->iommu
= VIRT_IOMMU_NONE
;
2459 error_setg(errp
, "Invalid iommu value");
2460 error_append_hint(errp
, "Valid values are none, smmuv3.\n");
2464 static bool virt_get_default_bus_bypass_iommu(Object
*obj
, Error
**errp
)
2466 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2468 return vms
->default_bus_bypass_iommu
;
2471 static void virt_set_default_bus_bypass_iommu(Object
*obj
, bool value
,
2474 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2476 vms
->default_bus_bypass_iommu
= value
;
2479 static CpuInstanceProperties
2480 virt_cpu_index_to_props(MachineState
*ms
, unsigned cpu_index
)
2482 MachineClass
*mc
= MACHINE_GET_CLASS(ms
);
2483 const CPUArchIdList
*possible_cpus
= mc
->possible_cpu_arch_ids(ms
);
2485 assert(cpu_index
< possible_cpus
->len
);
2486 return possible_cpus
->cpus
[cpu_index
].props
;
2489 static int64_t virt_get_default_cpu_node_id(const MachineState
*ms
, int idx
)
2491 return idx
% ms
->numa_state
->num_nodes
;
2494 static const CPUArchIdList
*virt_possible_cpu_arch_ids(MachineState
*ms
)
2497 unsigned int max_cpus
= ms
->smp
.max_cpus
;
2498 VirtMachineState
*vms
= VIRT_MACHINE(ms
);
2500 if (ms
->possible_cpus
) {
2501 assert(ms
->possible_cpus
->len
== max_cpus
);
2502 return ms
->possible_cpus
;
2505 ms
->possible_cpus
= g_malloc0(sizeof(CPUArchIdList
) +
2506 sizeof(CPUArchId
) * max_cpus
);
2507 ms
->possible_cpus
->len
= max_cpus
;
2508 for (n
= 0; n
< ms
->possible_cpus
->len
; n
++) {
2509 ms
->possible_cpus
->cpus
[n
].type
= ms
->cpu_type
;
2510 ms
->possible_cpus
->cpus
[n
].arch_id
=
2511 virt_cpu_mp_affinity(vms
, n
);
2512 ms
->possible_cpus
->cpus
[n
].props
.has_thread_id
= true;
2513 ms
->possible_cpus
->cpus
[n
].props
.thread_id
= n
;
2515 return ms
->possible_cpus
;
2518 static void virt_memory_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
2521 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2522 const MachineState
*ms
= MACHINE(hotplug_dev
);
2523 const bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
2525 if (!vms
->acpi_dev
) {
2527 "memory hotplug is not enabled: missing acpi-ged device");
2532 error_setg(errp
, "memory hotplug is not enabled: MTE is enabled");
2536 if (is_nvdimm
&& !ms
->nvdimms_state
->is_enabled
) {
2537 error_setg(errp
, "nvdimm is not enabled: add 'nvdimm=on' to '-M'");
2541 pc_dimm_pre_plug(PC_DIMM(dev
), MACHINE(hotplug_dev
), NULL
, errp
);
2544 static void virt_memory_plug(HotplugHandler
*hotplug_dev
,
2545 DeviceState
*dev
, Error
**errp
)
2547 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2548 MachineState
*ms
= MACHINE(hotplug_dev
);
2549 bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
2551 pc_dimm_plug(PC_DIMM(dev
), MACHINE(vms
));
2554 nvdimm_plug(ms
->nvdimms_state
);
2557 hotplug_handler_plug(HOTPLUG_HANDLER(vms
->acpi_dev
),
2561 static void virt_virtio_md_pci_pre_plug(HotplugHandler
*hotplug_dev
,
2562 DeviceState
*dev
, Error
**errp
)
2564 HotplugHandler
*hotplug_dev2
= qdev_get_bus_hotplug_handler(dev
);
2565 Error
*local_err
= NULL
;
2567 if (!hotplug_dev2
&& dev
->hotplugged
) {
2569 * Without a bus hotplug handler, we cannot control the plug/unplug
2570 * order. We should never reach this point when hotplugging on ARM.
2571 * However, it's nice to add a safety net, similar to what we have
2574 error_setg(errp
, "hotplug of virtio based memory devices not supported"
2579 * First, see if we can plug this memory device at all. If that
2580 * succeeds, branch of to the actual hotplug handler.
2582 memory_device_pre_plug(MEMORY_DEVICE(dev
), MACHINE(hotplug_dev
), NULL
,
2584 if (!local_err
&& hotplug_dev2
) {
2585 hotplug_handler_pre_plug(hotplug_dev2
, dev
, &local_err
);
2587 error_propagate(errp
, local_err
);
2590 static void virt_virtio_md_pci_plug(HotplugHandler
*hotplug_dev
,
2591 DeviceState
*dev
, Error
**errp
)
2593 HotplugHandler
*hotplug_dev2
= qdev_get_bus_hotplug_handler(dev
);
2594 Error
*local_err
= NULL
;
2597 * Plug the memory device first and then branch off to the actual
2598 * hotplug handler. If that one fails, we can easily undo the memory
2601 memory_device_plug(MEMORY_DEVICE(dev
), MACHINE(hotplug_dev
));
2603 hotplug_handler_plug(hotplug_dev2
, dev
, &local_err
);
2605 memory_device_unplug(MEMORY_DEVICE(dev
), MACHINE(hotplug_dev
));
2608 error_propagate(errp
, local_err
);
2611 static void virt_virtio_md_pci_unplug_request(HotplugHandler
*hotplug_dev
,
2612 DeviceState
*dev
, Error
**errp
)
2614 /* We don't support hot unplug of virtio based memory devices */
2615 error_setg(errp
, "virtio based memory devices cannot be unplugged.");
2619 static void virt_machine_device_pre_plug_cb(HotplugHandler
*hotplug_dev
,
2620 DeviceState
*dev
, Error
**errp
)
2622 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2624 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2625 virt_memory_pre_plug(hotplug_dev
, dev
, errp
);
2626 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MEM_PCI
)) {
2627 virt_virtio_md_pci_pre_plug(hotplug_dev
, dev
, errp
);
2628 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_IOMMU_PCI
)) {
2629 hwaddr db_start
= 0, db_end
= 0;
2630 char *resv_prop_str
;
2632 if (vms
->iommu
!= VIRT_IOMMU_NONE
) {
2633 error_setg(errp
, "virt machine does not support multiple IOMMUs");
2637 switch (vms
->msi_controller
) {
2638 case VIRT_MSI_CTRL_NONE
:
2640 case VIRT_MSI_CTRL_ITS
:
2641 /* GITS_TRANSLATER page */
2642 db_start
= base_memmap
[VIRT_GIC_ITS
].base
+ 0x10000;
2643 db_end
= base_memmap
[VIRT_GIC_ITS
].base
+
2644 base_memmap
[VIRT_GIC_ITS
].size
- 1;
2646 case VIRT_MSI_CTRL_GICV2M
:
2647 /* MSI_SETSPI_NS page */
2648 db_start
= base_memmap
[VIRT_GIC_V2M
].base
;
2649 db_end
= db_start
+ base_memmap
[VIRT_GIC_V2M
].size
- 1;
2652 resv_prop_str
= g_strdup_printf("0x%"PRIx64
":0x%"PRIx64
":%u",
2654 VIRTIO_IOMMU_RESV_MEM_T_MSI
);
2656 object_property_set_uint(OBJECT(dev
), "len-reserved-regions", 1, errp
);
2657 object_property_set_str(OBJECT(dev
), "reserved-regions[0]",
2658 resv_prop_str
, errp
);
2659 g_free(resv_prop_str
);
2663 static void virt_machine_device_plug_cb(HotplugHandler
*hotplug_dev
,
2664 DeviceState
*dev
, Error
**errp
)
2666 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2668 if (vms
->platform_bus_dev
) {
2669 MachineClass
*mc
= MACHINE_GET_CLASS(vms
);
2671 if (device_is_dynamic_sysbus(mc
, dev
)) {
2672 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms
->platform_bus_dev
),
2673 SYS_BUS_DEVICE(dev
));
2676 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2677 virt_memory_plug(hotplug_dev
, dev
, errp
);
2680 if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MEM_PCI
)) {
2681 virt_virtio_md_pci_plug(hotplug_dev
, dev
, errp
);
2684 if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_IOMMU_PCI
)) {
2685 PCIDevice
*pdev
= PCI_DEVICE(dev
);
2687 vms
->iommu
= VIRT_IOMMU_VIRTIO
;
2688 vms
->virtio_iommu_bdf
= pci_get_bdf(pdev
);
2689 create_virtio_iommu_dt_bindings(vms
);
2693 static void virt_dimm_unplug_request(HotplugHandler
*hotplug_dev
,
2694 DeviceState
*dev
, Error
**errp
)
2696 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2697 Error
*local_err
= NULL
;
2699 if (!vms
->acpi_dev
) {
2700 error_setg(&local_err
,
2701 "memory hotplug is not enabled: missing acpi-ged device");
2705 if (object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
)) {
2706 error_setg(&local_err
,
2707 "nvdimm device hot unplug is not supported yet.");
2711 hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms
->acpi_dev
), dev
,
2714 error_propagate(errp
, local_err
);
2717 static void virt_dimm_unplug(HotplugHandler
*hotplug_dev
,
2718 DeviceState
*dev
, Error
**errp
)
2720 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2721 Error
*local_err
= NULL
;
2723 hotplug_handler_unplug(HOTPLUG_HANDLER(vms
->acpi_dev
), dev
, &local_err
);
2728 pc_dimm_unplug(PC_DIMM(dev
), MACHINE(vms
));
2729 qdev_unrealize(dev
);
2732 error_propagate(errp
, local_err
);
2735 static void virt_machine_device_unplug_request_cb(HotplugHandler
*hotplug_dev
,
2736 DeviceState
*dev
, Error
**errp
)
2738 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2739 virt_dimm_unplug_request(hotplug_dev
, dev
, errp
);
2740 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MEM_PCI
)) {
2741 virt_virtio_md_pci_unplug_request(hotplug_dev
, dev
, errp
);
2743 error_setg(errp
, "device unplug request for unsupported device"
2744 " type: %s", object_get_typename(OBJECT(dev
)));
2748 static void virt_machine_device_unplug_cb(HotplugHandler
*hotplug_dev
,
2749 DeviceState
*dev
, Error
**errp
)
2751 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2752 virt_dimm_unplug(hotplug_dev
, dev
, errp
);
2754 error_setg(errp
, "virt: device unplug for unsupported device"
2755 " type: %s", object_get_typename(OBJECT(dev
)));
2759 static HotplugHandler
*virt_machine_get_hotplug_handler(MachineState
*machine
,
2762 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2764 if (device_is_dynamic_sysbus(mc
, dev
) ||
2765 object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
) ||
2766 object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MEM_PCI
) ||
2767 object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_IOMMU_PCI
)) {
2768 return HOTPLUG_HANDLER(machine
);
2774 * for arm64 kvm_type [7-0] encodes the requested number of bits
2775 * in the IPA address space
2777 static int virt_kvm_type(MachineState
*ms
, const char *type_str
)
2779 VirtMachineState
*vms
= VIRT_MACHINE(ms
);
2780 int max_vm_pa_size
, requested_pa_size
;
2783 max_vm_pa_size
= kvm_arm_get_max_vm_ipa_size(ms
, &fixed_ipa
);
2785 /* we freeze the memory map to compute the highest gpa */
2786 virt_set_memmap(vms
, max_vm_pa_size
);
2788 requested_pa_size
= 64 - clz64(vms
->highest_gpa
);
2791 * KVM requires the IPA size to be at least 32 bits.
2793 if (requested_pa_size
< 32) {
2794 requested_pa_size
= 32;
2797 if (requested_pa_size
> max_vm_pa_size
) {
2798 error_report("-m and ,maxmem option values "
2799 "require an IPA range (%d bits) larger than "
2800 "the one supported by the host (%d bits)",
2801 requested_pa_size
, max_vm_pa_size
);
2805 * We return the requested PA log size, unless KVM only supports
2806 * the implicit legacy 40b IPA setting, in which case the kvm_type
2809 return fixed_ipa
? 0 : requested_pa_size
;
2812 static void virt_machine_class_init(ObjectClass
*oc
, void *data
)
2814 MachineClass
*mc
= MACHINE_CLASS(oc
);
2815 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(oc
);
2817 mc
->init
= machvirt_init
;
2818 /* Start with max_cpus set to 512, which is the maximum supported by KVM.
2819 * The value may be reduced later when we have more information about the
2820 * configuration of the particular instance.
2823 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_CALXEDA_XGMAC
);
2824 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_AMD_XGBE
);
2825 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_RAMFB_DEVICE
);
2826 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_PLATFORM
);
2828 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_TPM_TIS_SYSBUS
);
2830 mc
->block_default_type
= IF_VIRTIO
;
2832 mc
->pci_allow_0_address
= true;
2833 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */
2834 mc
->minimum_page_bits
= 12;
2835 mc
->possible_cpu_arch_ids
= virt_possible_cpu_arch_ids
;
2836 mc
->cpu_index_to_instance_props
= virt_cpu_index_to_props
;
2837 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-a15");
2838 mc
->get_default_cpu_node_id
= virt_get_default_cpu_node_id
;
2839 mc
->kvm_type
= virt_kvm_type
;
2840 assert(!mc
->get_hotplug_handler
);
2841 mc
->get_hotplug_handler
= virt_machine_get_hotplug_handler
;
2842 hc
->pre_plug
= virt_machine_device_pre_plug_cb
;
2843 hc
->plug
= virt_machine_device_plug_cb
;
2844 hc
->unplug_request
= virt_machine_device_unplug_request_cb
;
2845 hc
->unplug
= virt_machine_device_unplug_cb
;
2846 mc
->nvdimm_supported
= true;
2847 mc
->smp_props
.clusters_supported
= true;
2848 mc
->auto_enable_numa_with_memhp
= true;
2849 mc
->auto_enable_numa_with_memdev
= true;
2850 mc
->default_ram_id
= "mach-virt.ram";
2852 object_class_property_add(oc
, "acpi", "OnOffAuto",
2853 virt_get_acpi
, virt_set_acpi
,
2855 object_class_property_set_description(oc
, "acpi",
2857 object_class_property_add_bool(oc
, "secure", virt_get_secure
,
2859 object_class_property_set_description(oc
, "secure",
2860 "Set on/off to enable/disable the ARM "
2861 "Security Extensions (TrustZone)");
2863 object_class_property_add_bool(oc
, "virtualization", virt_get_virt
,
2865 object_class_property_set_description(oc
, "virtualization",
2866 "Set on/off to enable/disable emulating a "
2867 "guest CPU which implements the ARM "
2868 "Virtualization Extensions");
2870 object_class_property_add_bool(oc
, "highmem", virt_get_highmem
,
2872 object_class_property_set_description(oc
, "highmem",
2873 "Set on/off to enable/disable using "
2874 "physical address space above 32 bits");
2876 object_class_property_add_str(oc
, "gic-version", virt_get_gic_version
,
2877 virt_set_gic_version
);
2878 object_class_property_set_description(oc
, "gic-version",
2880 "Valid values are 2, 3, host and max");
2882 object_class_property_add_str(oc
, "iommu", virt_get_iommu
, virt_set_iommu
);
2883 object_class_property_set_description(oc
, "iommu",
2884 "Set the IOMMU type. "
2885 "Valid values are none and smmuv3");
2887 object_class_property_add_bool(oc
, "default-bus-bypass-iommu",
2888 virt_get_default_bus_bypass_iommu
,
2889 virt_set_default_bus_bypass_iommu
);
2890 object_class_property_set_description(oc
, "default-bus-bypass-iommu",
2891 "Set on/off to enable/disable "
2892 "bypass_iommu for default root bus");
2894 object_class_property_add_bool(oc
, "ras", virt_get_ras
,
2896 object_class_property_set_description(oc
, "ras",
2897 "Set on/off to enable/disable reporting host memory errors "
2898 "to a KVM guest using ACPI and guest external abort exceptions");
2900 object_class_property_add_bool(oc
, "mte", virt_get_mte
, virt_set_mte
);
2901 object_class_property_set_description(oc
, "mte",
2902 "Set on/off to enable/disable emulating a "
2903 "guest CPU which implements the ARM "
2904 "Memory Tagging Extension");
2906 object_class_property_add_bool(oc
, "its", virt_get_its
,
2908 object_class_property_set_description(oc
, "its",
2909 "Set on/off to enable/disable "
2910 "ITS instantiation");
2912 object_class_property_add_bool(oc
, "dtb-kaslr-seed",
2913 virt_get_dtb_kaslr_seed
,
2914 virt_set_dtb_kaslr_seed
);
2915 object_class_property_set_description(oc
, "dtb-kaslr-seed",
2916 "Set off to disable passing of kaslr-seed "
2917 "dtb node to guest");
2919 object_class_property_add_str(oc
, "x-oem-id",
2922 object_class_property_set_description(oc
, "x-oem-id",
2923 "Override the default value of field OEMID "
2924 "in ACPI table header."
2925 "The string may be up to 6 bytes in size");
2928 object_class_property_add_str(oc
, "x-oem-table-id",
2929 virt_get_oem_table_id
,
2930 virt_set_oem_table_id
);
2931 object_class_property_set_description(oc
, "x-oem-table-id",
2932 "Override the default value of field OEM Table ID "
2933 "in ACPI table header."
2934 "The string may be up to 8 bytes in size");
2938 static void virt_instance_init(Object
*obj
)
2940 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2941 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
2943 /* EL3 is disabled by default on virt: this makes us consistent
2944 * between KVM and TCG for this board, and it also allows us to
2945 * boot UEFI blobs which assume no TrustZone support.
2947 vms
->secure
= false;
2949 /* EL2 is also disabled by default, for similar reasons */
2952 /* High memory is enabled by default */
2953 vms
->highmem
= true;
2954 vms
->gic_version
= VIRT_GIC_VERSION_NOSEL
;
2956 vms
->highmem_ecam
= !vmc
->no_highmem_ecam
;
2957 vms
->highmem_mmio
= true;
2958 vms
->highmem_redists
= true;
2963 /* Default allows ITS instantiation */
2966 if (vmc
->no_tcg_its
) {
2967 vms
->tcg_its
= false;
2969 vms
->tcg_its
= true;
2973 /* Default disallows iommu instantiation */
2974 vms
->iommu
= VIRT_IOMMU_NONE
;
2976 /* The default root bus is attached to iommu by default */
2977 vms
->default_bus_bypass_iommu
= false;
2979 /* Default disallows RAS instantiation */
2982 /* MTE is disabled by default. */
2985 /* Supply a kaslr-seed by default */
2986 vms
->dtb_kaslr_seed
= true;
2988 vms
->irqmap
= a15irqmap
;
2990 virt_flash_create(vms
);
2992 vms
->oem_id
= g_strndup(ACPI_BUILD_APPNAME6
, 6);
2993 vms
->oem_table_id
= g_strndup(ACPI_BUILD_APPNAME8
, 8);
2996 static const TypeInfo virt_machine_info
= {
2997 .name
= TYPE_VIRT_MACHINE
,
2998 .parent
= TYPE_MACHINE
,
3000 .instance_size
= sizeof(VirtMachineState
),
3001 .class_size
= sizeof(VirtMachineClass
),
3002 .class_init
= virt_machine_class_init
,
3003 .instance_init
= virt_instance_init
,
3004 .interfaces
= (InterfaceInfo
[]) {
3005 { TYPE_HOTPLUG_HANDLER
},
3010 static void machvirt_machine_init(void)
3012 type_register_static(&virt_machine_info
);
3014 type_init(machvirt_machine_init
);
3016 static void virt_machine_7_0_options(MachineClass
*mc
)
3019 DEFINE_VIRT_MACHINE_AS_LATEST(7, 0)
3021 static void virt_machine_6_2_options(MachineClass
*mc
)
3023 virt_machine_7_0_options(mc
);
3024 compat_props_add(mc
->compat_props
, hw_compat_6_2
, hw_compat_6_2_len
);
3026 DEFINE_VIRT_MACHINE(6, 2)
3028 static void virt_machine_6_1_options(MachineClass
*mc
)
3030 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3032 virt_machine_6_2_options(mc
);
3033 compat_props_add(mc
->compat_props
, hw_compat_6_1
, hw_compat_6_1_len
);
3034 mc
->smp_props
.prefer_sockets
= true;
3035 vmc
->no_cpu_topology
= true;
3037 /* qemu ITS was introduced with 6.2 */
3038 vmc
->no_tcg_its
= true;
3040 DEFINE_VIRT_MACHINE(6, 1)
3042 static void virt_machine_6_0_options(MachineClass
*mc
)
3044 virt_machine_6_1_options(mc
);
3045 compat_props_add(mc
->compat_props
, hw_compat_6_0
, hw_compat_6_0_len
);
3047 DEFINE_VIRT_MACHINE(6, 0)
3049 static void virt_machine_5_2_options(MachineClass
*mc
)
3051 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3053 virt_machine_6_0_options(mc
);
3054 compat_props_add(mc
->compat_props
, hw_compat_5_2
, hw_compat_5_2_len
);
3055 vmc
->no_secure_gpio
= true;
3057 DEFINE_VIRT_MACHINE(5, 2)
3059 static void virt_machine_5_1_options(MachineClass
*mc
)
3061 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3063 virt_machine_5_2_options(mc
);
3064 compat_props_add(mc
->compat_props
, hw_compat_5_1
, hw_compat_5_1_len
);
3065 vmc
->no_kvm_steal_time
= true;
3067 DEFINE_VIRT_MACHINE(5, 1)
3069 static void virt_machine_5_0_options(MachineClass
*mc
)
3071 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3073 virt_machine_5_1_options(mc
);
3074 compat_props_add(mc
->compat_props
, hw_compat_5_0
, hw_compat_5_0_len
);
3075 mc
->numa_mem_supported
= true;
3076 vmc
->acpi_expose_flash
= true;
3077 mc
->auto_enable_numa_with_memdev
= false;
3079 DEFINE_VIRT_MACHINE(5, 0)
3081 static void virt_machine_4_2_options(MachineClass
*mc
)
3083 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3085 virt_machine_5_0_options(mc
);
3086 compat_props_add(mc
->compat_props
, hw_compat_4_2
, hw_compat_4_2_len
);
3087 vmc
->kvm_no_adjvtime
= true;
3089 DEFINE_VIRT_MACHINE(4, 2)
3091 static void virt_machine_4_1_options(MachineClass
*mc
)
3093 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3095 virt_machine_4_2_options(mc
);
3096 compat_props_add(mc
->compat_props
, hw_compat_4_1
, hw_compat_4_1_len
);
3098 mc
->auto_enable_numa_with_memhp
= false;
3100 DEFINE_VIRT_MACHINE(4, 1)
3102 static void virt_machine_4_0_options(MachineClass
*mc
)
3104 virt_machine_4_1_options(mc
);
3105 compat_props_add(mc
->compat_props
, hw_compat_4_0
, hw_compat_4_0_len
);
3107 DEFINE_VIRT_MACHINE(4, 0)
3109 static void virt_machine_3_1_options(MachineClass
*mc
)
3111 virt_machine_4_0_options(mc
);
3112 compat_props_add(mc
->compat_props
, hw_compat_3_1
, hw_compat_3_1_len
);
3114 DEFINE_VIRT_MACHINE(3, 1)
3116 static void virt_machine_3_0_options(MachineClass
*mc
)
3118 virt_machine_3_1_options(mc
);
3119 compat_props_add(mc
->compat_props
, hw_compat_3_0
, hw_compat_3_0_len
);
3121 DEFINE_VIRT_MACHINE(3, 0)
3123 static void virt_machine_2_12_options(MachineClass
*mc
)
3125 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3127 virt_machine_3_0_options(mc
);
3128 compat_props_add(mc
->compat_props
, hw_compat_2_12
, hw_compat_2_12_len
);
3129 vmc
->no_highmem_ecam
= true;
3132 DEFINE_VIRT_MACHINE(2, 12)
3134 static void virt_machine_2_11_options(MachineClass
*mc
)
3136 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3138 virt_machine_2_12_options(mc
);
3139 compat_props_add(mc
->compat_props
, hw_compat_2_11
, hw_compat_2_11_len
);
3140 vmc
->smbios_old_sys_ver
= true;
3142 DEFINE_VIRT_MACHINE(2, 11)
3144 static void virt_machine_2_10_options(MachineClass
*mc
)
3146 virt_machine_2_11_options(mc
);
3147 compat_props_add(mc
->compat_props
, hw_compat_2_10
, hw_compat_2_10_len
);
3148 /* before 2.11 we never faulted accesses to bad addresses */
3149 mc
->ignore_memory_transaction_failures
= true;
3151 DEFINE_VIRT_MACHINE(2, 10)
3153 static void virt_machine_2_9_options(MachineClass
*mc
)
3155 virt_machine_2_10_options(mc
);
3156 compat_props_add(mc
->compat_props
, hw_compat_2_9
, hw_compat_2_9_len
);
3158 DEFINE_VIRT_MACHINE(2, 9)
3160 static void virt_machine_2_8_options(MachineClass
*mc
)
3162 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3164 virt_machine_2_9_options(mc
);
3165 compat_props_add(mc
->compat_props
, hw_compat_2_8
, hw_compat_2_8_len
);
3166 /* For 2.8 and earlier we falsely claimed in the DT that
3167 * our timers were edge-triggered, not level-triggered.
3169 vmc
->claim_edge_triggered_timers
= true;
3171 DEFINE_VIRT_MACHINE(2, 8)
3173 static void virt_machine_2_7_options(MachineClass
*mc
)
3175 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3177 virt_machine_2_8_options(mc
);
3178 compat_props_add(mc
->compat_props
, hw_compat_2_7
, hw_compat_2_7_len
);
3179 /* ITS was introduced with 2.8 */
3181 /* Stick with 1K pages for migration compatibility */
3182 mc
->minimum_page_bits
= 0;
3184 DEFINE_VIRT_MACHINE(2, 7)
3186 static void virt_machine_2_6_options(MachineClass
*mc
)
3188 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3190 virt_machine_2_7_options(mc
);
3191 compat_props_add(mc
->compat_props
, hw_compat_2_6
, hw_compat_2_6_len
);
3192 vmc
->disallow_affinity_adjustment
= true;
3193 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */
3196 DEFINE_VIRT_MACHINE(2, 6)