2 * ARM mach-virt emulation
4 * Copyright (c) 2013 Linaro Limited
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
18 * Emulate a virtual board which works by passing Linux all the information
19 * it needs about what devices are present via the device tree.
20 * There are some restrictions about what we can do here:
21 * + we can only present devices whose Linux drivers will work based
22 * purely on the device tree with no platform data at all
23 * + we want to present a very stripped-down minimalist platform,
24 * both because this reduces the security attack surface from the guest
25 * and also because it reduces our exposure to being broken when
26 * the kernel updates its device tree bindings and requires further
27 * information in a device binding that we aren't providing.
28 * This is essentially the same approach kvmtool uses.
31 #include "qemu/osdep.h"
32 #include "qemu/datadir.h"
33 #include "qemu/units.h"
34 #include "qemu/option.h"
35 #include "monitor/qdev.h"
36 #include "hw/sysbus.h"
37 #include "hw/arm/boot.h"
38 #include "hw/arm/primecell.h"
39 #include "hw/arm/virt.h"
40 #include "hw/block/flash.h"
41 #include "hw/vfio/vfio-calxeda-xgmac.h"
42 #include "hw/vfio/vfio-amd-xgbe.h"
43 #include "hw/display/ramfb.h"
45 #include "sysemu/device_tree.h"
46 #include "sysemu/numa.h"
47 #include "sysemu/runstate.h"
48 #include "sysemu/tpm.h"
49 #include "sysemu/tcg.h"
50 #include "sysemu/kvm.h"
51 #include "sysemu/hvf.h"
52 #include "sysemu/qtest.h"
53 #include "hw/loader.h"
54 #include "qapi/error.h"
55 #include "qemu/bitops.h"
56 #include "qemu/error-report.h"
57 #include "qemu/module.h"
58 #include "hw/pci-host/gpex.h"
59 #include "hw/virtio/virtio-pci.h"
60 #include "hw/core/sysbus-fdt.h"
61 #include "hw/platform-bus.h"
62 #include "hw/qdev-properties.h"
63 #include "hw/arm/fdt.h"
64 #include "hw/intc/arm_gic.h"
65 #include "hw/intc/arm_gicv3_common.h"
66 #include "hw/intc/arm_gicv3_its_common.h"
69 #include "hw/firmware/smbios.h"
70 #include "qapi/visitor.h"
71 #include "qapi/qapi-visit-common.h"
72 #include "qapi/qmp/qlist.h"
73 #include "standard-headers/linux/input.h"
74 #include "hw/arm/smmuv3.h"
75 #include "hw/acpi/acpi.h"
76 #include "target/arm/cpu-qom.h"
77 #include "target/arm/internals.h"
78 #include "target/arm/multiprocessing.h"
79 #include "target/arm/gtimer.h"
80 #include "hw/mem/pc-dimm.h"
81 #include "hw/mem/nvdimm.h"
82 #include "hw/acpi/generic_event_device.h"
83 #include "hw/virtio/virtio-md-pci.h"
84 #include "hw/virtio/virtio-iommu.h"
85 #include "hw/char/pl011.h"
86 #include "qemu/guest-random.h"
88 static GlobalProperty arm_virt_compat
[] = {
89 { TYPE_VIRTIO_IOMMU_PCI
, "aw-bits", "48" },
91 static const size_t arm_virt_compat_len
= G_N_ELEMENTS(arm_virt_compat
);
94 * This cannot be called from the virt_machine_class_init() because
95 * TYPE_VIRT_MACHINE is abstract and mc->compat_props g_ptr_array_new()
96 * only is called on virt non abstract class init.
98 static void arm_virt_compat_set(MachineClass
*mc
)
100 compat_props_add(mc
->compat_props
, arm_virt_compat
,
101 arm_virt_compat_len
);
104 #define DEFINE_VIRT_MACHINE_IMPL(latest, ...) \
105 static void MACHINE_VER_SYM(class_init, virt, __VA_ARGS__)( \
109 MachineClass *mc = MACHINE_CLASS(oc); \
110 arm_virt_compat_set(mc); \
111 MACHINE_VER_SYM(options, virt, __VA_ARGS__)(mc); \
112 mc->desc = "QEMU " MACHINE_VER_STR(__VA_ARGS__) " ARM Virtual Machine"; \
113 MACHINE_VER_DEPRECATION(__VA_ARGS__); \
115 mc->alias = "virt"; \
118 static const TypeInfo MACHINE_VER_SYM(info, virt, __VA_ARGS__) = \
120 .name = MACHINE_VER_TYPE_NAME("virt", __VA_ARGS__), \
121 .parent = TYPE_VIRT_MACHINE, \
122 .class_init = MACHINE_VER_SYM(class_init, virt, __VA_ARGS__), \
124 static void MACHINE_VER_SYM(register, virt, __VA_ARGS__)(void) \
126 MACHINE_VER_DELETION(__VA_ARGS__); \
127 type_register_static(&MACHINE_VER_SYM(info, virt, __VA_ARGS__)); \
129 type_init(MACHINE_VER_SYM(register, virt, __VA_ARGS__));
131 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
132 DEFINE_VIRT_MACHINE_IMPL(true, major, minor)
133 #define DEFINE_VIRT_MACHINE(major, minor) \
134 DEFINE_VIRT_MACHINE_IMPL(false, major, minor)
137 /* Number of external interrupt lines to configure the GIC with */
140 #define PLATFORM_BUS_NUM_IRQS 64
142 /* Legacy RAM limit in GB (< version 4.0) */
143 #define LEGACY_RAMLIMIT_GB 255
144 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB)
146 /* Addresses and sizes of our components.
147 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
148 * 128MB..256MB is used for miscellaneous device I/O.
149 * 256MB..1GB is reserved for possible future PCI support (ie where the
150 * PCI memory window will go if we add a PCI host controller).
151 * 1GB and up is RAM (which may happily spill over into the
152 * high memory region beyond 4GB).
153 * This represents a compromise between how much RAM can be given to
154 * a 32 bit VM and leaving space for expansion and in particular for PCI.
155 * Note that devices should generally be placed at multiples of 0x10000,
156 * to accommodate guests using 64K pages.
158 static const MemMapEntry base_memmap
[] = {
159 /* Space up to 0x8000000 is reserved for a boot ROM */
160 [VIRT_FLASH
] = { 0, 0x08000000 },
161 [VIRT_CPUPERIPHS
] = { 0x08000000, 0x00020000 },
162 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
163 [VIRT_GIC_DIST
] = { 0x08000000, 0x00010000 },
164 [VIRT_GIC_CPU
] = { 0x08010000, 0x00010000 },
165 [VIRT_GIC_V2M
] = { 0x08020000, 0x00001000 },
166 [VIRT_GIC_HYP
] = { 0x08030000, 0x00010000 },
167 [VIRT_GIC_VCPU
] = { 0x08040000, 0x00010000 },
168 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */
169 [VIRT_GIC_ITS
] = { 0x08080000, 0x00020000 },
170 /* This redistributor space allows up to 2*64kB*123 CPUs */
171 [VIRT_GIC_REDIST
] = { 0x080A0000, 0x00F60000 },
172 [VIRT_UART0
] = { 0x09000000, 0x00001000 },
173 [VIRT_RTC
] = { 0x09010000, 0x00001000 },
174 [VIRT_FW_CFG
] = { 0x09020000, 0x00000018 },
175 [VIRT_GPIO
] = { 0x09030000, 0x00001000 },
176 [VIRT_UART1
] = { 0x09040000, 0x00001000 },
177 [VIRT_SMMU
] = { 0x09050000, 0x00020000 },
178 [VIRT_PCDIMM_ACPI
] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN
},
179 [VIRT_ACPI_GED
] = { 0x09080000, ACPI_GED_EVT_SEL_LEN
},
180 [VIRT_NVDIMM_ACPI
] = { 0x09090000, NVDIMM_ACPI_IO_LEN
},
181 [VIRT_PVTIME
] = { 0x090a0000, 0x00010000 },
182 [VIRT_SECURE_GPIO
] = { 0x090b0000, 0x00001000 },
183 [VIRT_MMIO
] = { 0x0a000000, 0x00000200 },
184 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
185 [VIRT_PLATFORM_BUS
] = { 0x0c000000, 0x02000000 },
186 [VIRT_SECURE_MEM
] = { 0x0e000000, 0x01000000 },
187 [VIRT_PCIE_MMIO
] = { 0x10000000, 0x2eff0000 },
188 [VIRT_PCIE_PIO
] = { 0x3eff0000, 0x00010000 },
189 [VIRT_PCIE_ECAM
] = { 0x3f000000, 0x01000000 },
190 /* Actual RAM size depends on initial RAM and device memory settings */
191 [VIRT_MEM
] = { GiB
, LEGACY_RAMLIMIT_BYTES
},
195 * Highmem IO Regions: This memory map is floating, located after the RAM.
196 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the
197 * top of the RAM, so that its base get the same alignment as the size,
198 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is
199 * less than 256GiB of RAM, the floating area starts at the 256GiB mark.
200 * Note the extended_memmap is sized so that it eventually also includes the
201 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last
202 * index of base_memmap).
204 * The memory map for these Highmem IO Regions can be in legacy or compact
205 * layout, depending on 'compact-highmem' property. With legacy layout, the
206 * PA space for one specific region is always reserved, even if the region
207 * has been disabled or doesn't fit into the PA space. However, the PA space
208 * for the region won't be reserved in these circumstances with compact layout.
210 static MemMapEntry extended_memmap
[] = {
211 /* Additional 64 MB redist region (can contain up to 512 redistributors) */
212 [VIRT_HIGH_GIC_REDIST2
] = { 0x0, 64 * MiB
},
213 [VIRT_HIGH_PCIE_ECAM
] = { 0x0, 256 * MiB
},
214 /* Second PCIe window */
215 [VIRT_HIGH_PCIE_MMIO
] = { 0x0, 512 * GiB
},
218 static const int a15irqmap
[] = {
221 [VIRT_PCIE
] = 3, /* ... to 6 */
225 [VIRT_MMIO
] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
226 [VIRT_GIC_V2M
] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
227 [VIRT_SMMU
] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */
228 [VIRT_PLATFORM_BUS
] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
231 static void create_randomness(MachineState
*ms
, const char *node
)
238 if (qemu_guest_getrandom(&seed
, sizeof(seed
), NULL
)) {
241 qemu_fdt_setprop_u64(ms
->fdt
, node
, "kaslr-seed", seed
.kaslr
);
242 qemu_fdt_setprop(ms
->fdt
, node
, "rng-seed", seed
.rng
, sizeof(seed
.rng
));
246 * The CPU object always exposes the NS EL2 virt timer IRQ line,
247 * but we don't want to advertise it to the guest in the dtb or ACPI
248 * table unless it's really going to do something.
250 static bool ns_el2_virt_timer_present(void)
252 ARMCPU
*cpu
= ARM_CPU(qemu_get_cpu(0));
253 CPUARMState
*env
= &cpu
->env
;
255 return arm_feature(env
, ARM_FEATURE_AARCH64
) &&
256 arm_feature(env
, ARM_FEATURE_EL2
) && cpu_isar_feature(aa64_vh
, cpu
);
259 static void create_fdt(VirtMachineState
*vms
)
261 MachineState
*ms
= MACHINE(vms
);
262 int nb_numa_nodes
= ms
->numa_state
->num_nodes
;
263 void *fdt
= create_device_tree(&vms
->fdt_size
);
266 error_report("create_device_tree() failed");
273 qemu_fdt_setprop_string(fdt
, "/", "compatible", "linux,dummy-virt");
274 qemu_fdt_setprop_cell(fdt
, "/", "#address-cells", 0x2);
275 qemu_fdt_setprop_cell(fdt
, "/", "#size-cells", 0x2);
276 qemu_fdt_setprop_string(fdt
, "/", "model", "linux,dummy-virt");
279 * For QEMU, all DMA is coherent. Advertising this in the root node
282 * - It avoids potential bugs where we forget to mark a DMA
283 * capable device as being dma-coherent
284 * - It avoids spurious warnings from the Linux kernel about
285 * devices which can't do DMA at all
287 qemu_fdt_setprop(fdt
, "/", "dma-coherent", NULL
, 0);
289 /* /chosen must exist for load_dtb to fill in necessary properties later */
290 qemu_fdt_add_subnode(fdt
, "/chosen");
291 if (vms
->dtb_randomness
) {
292 create_randomness(ms
, "/chosen");
296 qemu_fdt_add_subnode(fdt
, "/secure-chosen");
297 if (vms
->dtb_randomness
) {
298 create_randomness(ms
, "/secure-chosen");
302 qemu_fdt_add_subnode(fdt
, "/aliases");
304 /* Clock node, for the benefit of the UART. The kernel device tree
305 * binding documentation claims the PL011 node clock properties are
306 * optional but in practice if you omit them the kernel refuses to
307 * probe for the device.
309 vms
->clock_phandle
= qemu_fdt_alloc_phandle(fdt
);
310 qemu_fdt_add_subnode(fdt
, "/apb-pclk");
311 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "compatible", "fixed-clock");
312 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "#clock-cells", 0x0);
313 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "clock-frequency", 24000000);
314 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "clock-output-names",
316 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "phandle", vms
->clock_phandle
);
318 if (nb_numa_nodes
> 0 && ms
->numa_state
->have_numa_distance
) {
319 int size
= nb_numa_nodes
* nb_numa_nodes
* 3 * sizeof(uint32_t);
320 uint32_t *matrix
= g_malloc0(size
);
323 for (i
= 0; i
< nb_numa_nodes
; i
++) {
324 for (j
= 0; j
< nb_numa_nodes
; j
++) {
325 idx
= (i
* nb_numa_nodes
+ j
) * 3;
326 matrix
[idx
+ 0] = cpu_to_be32(i
);
327 matrix
[idx
+ 1] = cpu_to_be32(j
);
329 cpu_to_be32(ms
->numa_state
->nodes
[i
].distance
[j
]);
333 qemu_fdt_add_subnode(fdt
, "/distance-map");
334 qemu_fdt_setprop_string(fdt
, "/distance-map", "compatible",
335 "numa-distance-map-v1");
336 qemu_fdt_setprop(fdt
, "/distance-map", "distance-matrix",
342 static void fdt_add_timer_nodes(const VirtMachineState
*vms
)
344 /* On real hardware these interrupts are level-triggered.
345 * On KVM they were edge-triggered before host kernel version 4.4,
346 * and level-triggered afterwards.
347 * On emulated QEMU they are level-triggered.
349 * Getting the DTB info about them wrong is awkward for some
351 * pre-4.8 ignore the DT and leave the interrupt configured
352 * with whatever the GIC reset value (or the bootloader) left it at
353 * 4.8 before rc6 honour the incorrect data by programming it back
354 * into the GIC, causing problems
355 * 4.8rc6 and later ignore the DT and always write "level triggered"
358 * For backwards-compatibility, virt-2.8 and earlier will continue
359 * to say these are edge-triggered, but later machines will report
360 * the correct information.
363 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
364 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
365 MachineState
*ms
= MACHINE(vms
);
367 if (vmc
->claim_edge_triggered_timers
) {
368 irqflags
= GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
;
371 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
372 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
373 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
374 (1 << MACHINE(vms
)->smp
.cpus
) - 1);
377 qemu_fdt_add_subnode(ms
->fdt
, "/timer");
379 armcpu
= ARM_CPU(qemu_get_cpu(0));
380 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
381 const char compat
[] = "arm,armv8-timer\0arm,armv7-timer";
382 qemu_fdt_setprop(ms
->fdt
, "/timer", "compatible",
383 compat
, sizeof(compat
));
385 qemu_fdt_setprop_string(ms
->fdt
, "/timer", "compatible",
388 qemu_fdt_setprop(ms
->fdt
, "/timer", "always-on", NULL
, 0);
389 if (vms
->ns_el2_virt_timer_irq
) {
390 qemu_fdt_setprop_cells(ms
->fdt
, "/timer", "interrupts",
391 GIC_FDT_IRQ_TYPE_PPI
,
392 INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ
), irqflags
,
393 GIC_FDT_IRQ_TYPE_PPI
,
394 INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ
), irqflags
,
395 GIC_FDT_IRQ_TYPE_PPI
,
396 INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ
), irqflags
,
397 GIC_FDT_IRQ_TYPE_PPI
,
398 INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ
), irqflags
,
399 GIC_FDT_IRQ_TYPE_PPI
,
400 INTID_TO_PPI(ARCH_TIMER_NS_EL2_VIRT_IRQ
), irqflags
);
402 qemu_fdt_setprop_cells(ms
->fdt
, "/timer", "interrupts",
403 GIC_FDT_IRQ_TYPE_PPI
,
404 INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ
), irqflags
,
405 GIC_FDT_IRQ_TYPE_PPI
,
406 INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ
), irqflags
,
407 GIC_FDT_IRQ_TYPE_PPI
,
408 INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ
), irqflags
,
409 GIC_FDT_IRQ_TYPE_PPI
,
410 INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ
), irqflags
);
414 static void fdt_add_cpu_nodes(const VirtMachineState
*vms
)
418 const MachineState
*ms
= MACHINE(vms
);
419 const VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
420 int smp_cpus
= ms
->smp
.cpus
;
423 * See Linux Documentation/devicetree/bindings/arm/cpus.yaml
424 * On ARM v8 64-bit systems value should be set to 2,
425 * that corresponds to the MPIDR_EL1 register size.
426 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
427 * in the system, #address-cells can be set to 1, since
428 * MPIDR_EL1[63:32] bits are not used for CPUs
431 * Here we actually don't know whether our system is 32- or 64-bit one.
432 * The simplest way to go is to examine affinity IDs of all our CPUs. If
433 * at least one of them has Aff3 populated, we set #address-cells to 2.
435 for (cpu
= 0; cpu
< smp_cpus
; cpu
++) {
436 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
438 if (arm_cpu_mp_affinity(armcpu
) & ARM_AFF3_MASK
) {
444 qemu_fdt_add_subnode(ms
->fdt
, "/cpus");
445 qemu_fdt_setprop_cell(ms
->fdt
, "/cpus", "#address-cells", addr_cells
);
446 qemu_fdt_setprop_cell(ms
->fdt
, "/cpus", "#size-cells", 0x0);
448 for (cpu
= smp_cpus
- 1; cpu
>= 0; cpu
--) {
449 char *nodename
= g_strdup_printf("/cpus/cpu@%d", cpu
);
450 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
451 CPUState
*cs
= CPU(armcpu
);
453 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
454 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "device_type", "cpu");
455 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
456 armcpu
->dtb_compatible
);
458 if (vms
->psci_conduit
!= QEMU_PSCI_CONDUIT_DISABLED
&& smp_cpus
> 1) {
459 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
460 "enable-method", "psci");
463 if (addr_cells
== 2) {
464 qemu_fdt_setprop_u64(ms
->fdt
, nodename
, "reg",
465 arm_cpu_mp_affinity(armcpu
));
467 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "reg",
468 arm_cpu_mp_affinity(armcpu
));
471 if (ms
->possible_cpus
->cpus
[cs
->cpu_index
].props
.has_node_id
) {
472 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "numa-node-id",
473 ms
->possible_cpus
->cpus
[cs
->cpu_index
].props
.node_id
);
476 if (!vmc
->no_cpu_topology
) {
477 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle",
478 qemu_fdt_alloc_phandle(ms
->fdt
));
484 if (!vmc
->no_cpu_topology
) {
486 * Add vCPU topology description through fdt node cpu-map.
488 * See Linux Documentation/devicetree/bindings/cpu/cpu-topology.txt
489 * In a SMP system, the hierarchy of CPUs can be defined through
490 * four entities that are used to describe the layout of CPUs in
491 * the system: socket/cluster/core/thread.
493 * A socket node represents the boundary of system physical package
494 * and its child nodes must be one or more cluster nodes. A system
495 * can contain several layers of clustering within a single physical
496 * package and cluster nodes can be contained in parent cluster nodes.
498 * Note: currently we only support one layer of clustering within
499 * each physical package.
501 qemu_fdt_add_subnode(ms
->fdt
, "/cpus/cpu-map");
503 for (cpu
= smp_cpus
- 1; cpu
>= 0; cpu
--) {
504 char *cpu_path
= g_strdup_printf("/cpus/cpu@%d", cpu
);
507 if (ms
->smp
.threads
> 1) {
508 map_path
= g_strdup_printf(
509 "/cpus/cpu-map/socket%d/cluster%d/core%d/thread%d",
510 cpu
/ (ms
->smp
.clusters
* ms
->smp
.cores
* ms
->smp
.threads
),
511 (cpu
/ (ms
->smp
.cores
* ms
->smp
.threads
)) % ms
->smp
.clusters
,
512 (cpu
/ ms
->smp
.threads
) % ms
->smp
.cores
,
513 cpu
% ms
->smp
.threads
);
515 map_path
= g_strdup_printf(
516 "/cpus/cpu-map/socket%d/cluster%d/core%d",
517 cpu
/ (ms
->smp
.clusters
* ms
->smp
.cores
),
518 (cpu
/ ms
->smp
.cores
) % ms
->smp
.clusters
,
519 cpu
% ms
->smp
.cores
);
521 qemu_fdt_add_path(ms
->fdt
, map_path
);
522 qemu_fdt_setprop_phandle(ms
->fdt
, map_path
, "cpu", cpu_path
);
530 static void fdt_add_its_gic_node(VirtMachineState
*vms
)
533 MachineState
*ms
= MACHINE(vms
);
535 vms
->msi_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
536 nodename
= g_strdup_printf("/intc/its@%" PRIx64
,
537 vms
->memmap
[VIRT_GIC_ITS
].base
);
538 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
539 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
541 qemu_fdt_setprop(ms
->fdt
, nodename
, "msi-controller", NULL
, 0);
542 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#msi-cells", 1);
543 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
544 2, vms
->memmap
[VIRT_GIC_ITS
].base
,
545 2, vms
->memmap
[VIRT_GIC_ITS
].size
);
546 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle", vms
->msi_phandle
);
550 static void fdt_add_v2m_gic_node(VirtMachineState
*vms
)
552 MachineState
*ms
= MACHINE(vms
);
555 nodename
= g_strdup_printf("/intc/v2m@%" PRIx64
,
556 vms
->memmap
[VIRT_GIC_V2M
].base
);
557 vms
->msi_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
558 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
559 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
560 "arm,gic-v2m-frame");
561 qemu_fdt_setprop(ms
->fdt
, nodename
, "msi-controller", NULL
, 0);
562 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
563 2, vms
->memmap
[VIRT_GIC_V2M
].base
,
564 2, vms
->memmap
[VIRT_GIC_V2M
].size
);
565 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle", vms
->msi_phandle
);
569 static void fdt_add_gic_node(VirtMachineState
*vms
)
571 MachineState
*ms
= MACHINE(vms
);
574 vms
->gic_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
575 qemu_fdt_setprop_cell(ms
->fdt
, "/", "interrupt-parent", vms
->gic_phandle
);
577 nodename
= g_strdup_printf("/intc@%" PRIx64
,
578 vms
->memmap
[VIRT_GIC_DIST
].base
);
579 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
580 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#interrupt-cells", 3);
581 qemu_fdt_setprop(ms
->fdt
, nodename
, "interrupt-controller", NULL
, 0);
582 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#address-cells", 0x2);
583 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#size-cells", 0x2);
584 qemu_fdt_setprop(ms
->fdt
, nodename
, "ranges", NULL
, 0);
585 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
) {
586 int nb_redist_regions
= virt_gicv3_redist_region_count(vms
);
588 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
591 qemu_fdt_setprop_cell(ms
->fdt
, nodename
,
592 "#redistributor-regions", nb_redist_regions
);
594 if (nb_redist_regions
== 1) {
595 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
596 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
597 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
598 2, vms
->memmap
[VIRT_GIC_REDIST
].base
,
599 2, vms
->memmap
[VIRT_GIC_REDIST
].size
);
601 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
602 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
603 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
604 2, vms
->memmap
[VIRT_GIC_REDIST
].base
,
605 2, vms
->memmap
[VIRT_GIC_REDIST
].size
,
606 2, vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].base
,
607 2, vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].size
);
611 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
612 GIC_FDT_IRQ_TYPE_PPI
,
613 INTID_TO_PPI(ARCH_GIC_MAINT_IRQ
),
614 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
617 /* 'cortex-a15-gic' means 'GIC v2' */
618 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
619 "arm,cortex-a15-gic");
621 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
622 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
623 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
624 2, vms
->memmap
[VIRT_GIC_CPU
].base
,
625 2, vms
->memmap
[VIRT_GIC_CPU
].size
);
627 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
628 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
629 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
630 2, vms
->memmap
[VIRT_GIC_CPU
].base
,
631 2, vms
->memmap
[VIRT_GIC_CPU
].size
,
632 2, vms
->memmap
[VIRT_GIC_HYP
].base
,
633 2, vms
->memmap
[VIRT_GIC_HYP
].size
,
634 2, vms
->memmap
[VIRT_GIC_VCPU
].base
,
635 2, vms
->memmap
[VIRT_GIC_VCPU
].size
);
636 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
637 GIC_FDT_IRQ_TYPE_PPI
,
638 INTID_TO_PPI(ARCH_GIC_MAINT_IRQ
),
639 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
643 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle", vms
->gic_phandle
);
647 static void fdt_add_pmu_nodes(const VirtMachineState
*vms
)
649 ARMCPU
*armcpu
= ARM_CPU(first_cpu
);
650 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
651 MachineState
*ms
= MACHINE(vms
);
653 if (!arm_feature(&armcpu
->env
, ARM_FEATURE_PMU
)) {
654 assert(!object_property_get_bool(OBJECT(armcpu
), "pmu", NULL
));
658 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
659 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
660 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
661 (1 << MACHINE(vms
)->smp
.cpus
) - 1);
664 qemu_fdt_add_subnode(ms
->fdt
, "/pmu");
665 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
666 const char compat
[] = "arm,armv8-pmuv3";
667 qemu_fdt_setprop(ms
->fdt
, "/pmu", "compatible",
668 compat
, sizeof(compat
));
669 qemu_fdt_setprop_cells(ms
->fdt
, "/pmu", "interrupts",
670 GIC_FDT_IRQ_TYPE_PPI
,
671 INTID_TO_PPI(VIRTUAL_PMU_IRQ
), irqflags
);
675 static inline DeviceState
*create_acpi_ged(VirtMachineState
*vms
)
678 MachineState
*ms
= MACHINE(vms
);
679 int irq
= vms
->irqmap
[VIRT_ACPI_GED
];
680 uint32_t event
= ACPI_GED_PWR_DOWN_EVT
;
683 event
|= ACPI_GED_MEM_HOTPLUG_EVT
;
686 if (ms
->nvdimms_state
->is_enabled
) {
687 event
|= ACPI_GED_NVDIMM_HOTPLUG_EVT
;
690 dev
= qdev_new(TYPE_ACPI_GED
);
691 qdev_prop_set_uint32(dev
, "ged-event", event
);
692 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
694 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_ACPI_GED
].base
);
695 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 1, vms
->memmap
[VIRT_PCDIMM_ACPI
].base
);
696 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0, qdev_get_gpio_in(vms
->gic
, irq
));
701 static void create_its(VirtMachineState
*vms
)
703 const char *itsclass
= its_class_name();
706 if (!strcmp(itsclass
, "arm-gicv3-its")) {
713 /* Do nothing if not supported */
717 dev
= qdev_new(itsclass
);
719 object_property_set_link(OBJECT(dev
), "parent-gicv3", OBJECT(vms
->gic
),
721 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
722 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_GIC_ITS
].base
);
724 fdt_add_its_gic_node(vms
);
725 vms
->msi_controller
= VIRT_MSI_CTRL_ITS
;
728 static void create_v2m(VirtMachineState
*vms
)
731 int irq
= vms
->irqmap
[VIRT_GIC_V2M
];
734 dev
= qdev_new("arm-gicv2m");
735 qdev_prop_set_uint32(dev
, "base-spi", irq
);
736 qdev_prop_set_uint32(dev
, "num-spi", NUM_GICV2M_SPIS
);
737 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
738 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_GIC_V2M
].base
);
740 for (i
= 0; i
< NUM_GICV2M_SPIS
; i
++) {
741 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
742 qdev_get_gpio_in(vms
->gic
, irq
+ i
));
745 fdt_add_v2m_gic_node(vms
);
746 vms
->msi_controller
= VIRT_MSI_CTRL_GICV2M
;
750 * If the CPU has FEAT_NMI, then turn on the NMI support in the GICv3 too.
751 * It's permitted to have a configuration with NMI in the CPU (and thus the
752 * GICv3 CPU interface) but not in the distributor/redistributors, but it's
755 static bool gicv3_nmi_present(VirtMachineState
*vms
)
757 ARMCPU
*cpu
= ARM_CPU(qemu_get_cpu(0));
759 return tcg_enabled() && cpu_isar_feature(aa64_nmi
, cpu
) &&
760 (vms
->gic_version
!= VIRT_GIC_VERSION_2
);
763 static void create_gic(VirtMachineState
*vms
, MemoryRegion
*mem
)
765 MachineState
*ms
= MACHINE(vms
);
766 /* We create a standalone GIC */
767 SysBusDevice
*gicbusdev
;
770 unsigned int smp_cpus
= ms
->smp
.cpus
;
771 uint32_t nb_redist_regions
= 0;
774 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
775 gictype
= gic_class_name();
777 gictype
= gicv3_class_name();
780 switch (vms
->gic_version
) {
781 case VIRT_GIC_VERSION_2
:
784 case VIRT_GIC_VERSION_3
:
787 case VIRT_GIC_VERSION_4
:
791 g_assert_not_reached();
793 vms
->gic
= qdev_new(gictype
);
794 qdev_prop_set_uint32(vms
->gic
, "revision", revision
);
795 qdev_prop_set_uint32(vms
->gic
, "num-cpu", smp_cpus
);
796 /* Note that the num-irq property counts both internal and external
797 * interrupts; there are always 32 of the former (mandated by GIC spec).
799 qdev_prop_set_uint32(vms
->gic
, "num-irq", NUM_IRQS
+ 32);
800 if (!kvm_irqchip_in_kernel()) {
801 qdev_prop_set_bit(vms
->gic
, "has-security-extensions", vms
->secure
);
804 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
) {
805 QList
*redist_region_count
;
806 uint32_t redist0_capacity
= virt_redist_capacity(vms
, VIRT_GIC_REDIST
);
807 uint32_t redist0_count
= MIN(smp_cpus
, redist0_capacity
);
809 nb_redist_regions
= virt_gicv3_redist_region_count(vms
);
811 redist_region_count
= qlist_new();
812 qlist_append_int(redist_region_count
, redist0_count
);
813 if (nb_redist_regions
== 2) {
814 uint32_t redist1_capacity
=
815 virt_redist_capacity(vms
, VIRT_HIGH_GIC_REDIST2
);
817 qlist_append_int(redist_region_count
,
818 MIN(smp_cpus
- redist0_count
, redist1_capacity
));
820 qdev_prop_set_array(vms
->gic
, "redist-region-count",
821 redist_region_count
);
823 if (!kvm_irqchip_in_kernel()) {
825 object_property_set_link(OBJECT(vms
->gic
), "sysmem",
826 OBJECT(mem
), &error_fatal
);
827 qdev_prop_set_bit(vms
->gic
, "has-lpi", true);
831 if (!kvm_irqchip_in_kernel()) {
832 qdev_prop_set_bit(vms
->gic
, "has-virtualization-extensions",
837 if (gicv3_nmi_present(vms
)) {
838 qdev_prop_set_bit(vms
->gic
, "has-nmi", true);
841 gicbusdev
= SYS_BUS_DEVICE(vms
->gic
);
842 sysbus_realize_and_unref(gicbusdev
, &error_fatal
);
843 sysbus_mmio_map(gicbusdev
, 0, vms
->memmap
[VIRT_GIC_DIST
].base
);
844 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
) {
845 sysbus_mmio_map(gicbusdev
, 1, vms
->memmap
[VIRT_GIC_REDIST
].base
);
846 if (nb_redist_regions
== 2) {
847 sysbus_mmio_map(gicbusdev
, 2,
848 vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].base
);
851 sysbus_mmio_map(gicbusdev
, 1, vms
->memmap
[VIRT_GIC_CPU
].base
);
853 sysbus_mmio_map(gicbusdev
, 2, vms
->memmap
[VIRT_GIC_HYP
].base
);
854 sysbus_mmio_map(gicbusdev
, 3, vms
->memmap
[VIRT_GIC_VCPU
].base
);
858 /* Wire the outputs from each CPU's generic timer and the GICv3
859 * maintenance interrupt signal to the appropriate GIC PPI inputs,
860 * and the GIC's IRQ/FIQ/VIRQ/VFIQ/NMI/VINMI interrupt outputs to the
863 for (i
= 0; i
< smp_cpus
; i
++) {
864 DeviceState
*cpudev
= DEVICE(qemu_get_cpu(i
));
865 int intidbase
= NUM_IRQS
+ i
* GIC_INTERNAL
;
866 /* Mapping from the output timer irq lines from the CPU to the
867 * GIC PPI inputs we use for the virt board.
869 const int timer_irq
[] = {
870 [GTIMER_PHYS
] = ARCH_TIMER_NS_EL1_IRQ
,
871 [GTIMER_VIRT
] = ARCH_TIMER_VIRT_IRQ
,
872 [GTIMER_HYP
] = ARCH_TIMER_NS_EL2_IRQ
,
873 [GTIMER_SEC
] = ARCH_TIMER_S_EL1_IRQ
,
874 [GTIMER_HYPVIRT
] = ARCH_TIMER_NS_EL2_VIRT_IRQ
,
877 for (unsigned irq
= 0; irq
< ARRAY_SIZE(timer_irq
); irq
++) {
878 qdev_connect_gpio_out(cpudev
, irq
,
879 qdev_get_gpio_in(vms
->gic
,
880 intidbase
+ timer_irq
[irq
]));
883 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
) {
884 qemu_irq irq
= qdev_get_gpio_in(vms
->gic
,
885 intidbase
+ ARCH_GIC_MAINT_IRQ
);
886 qdev_connect_gpio_out_named(cpudev
, "gicv3-maintenance-interrupt",
888 } else if (vms
->virt
) {
889 qemu_irq irq
= qdev_get_gpio_in(vms
->gic
,
890 intidbase
+ ARCH_GIC_MAINT_IRQ
);
891 sysbus_connect_irq(gicbusdev
, i
+ 4 * smp_cpus
, irq
);
894 qdev_connect_gpio_out_named(cpudev
, "pmu-interrupt", 0,
895 qdev_get_gpio_in(vms
->gic
, intidbase
898 sysbus_connect_irq(gicbusdev
, i
, qdev_get_gpio_in(cpudev
, ARM_CPU_IRQ
));
899 sysbus_connect_irq(gicbusdev
, i
+ smp_cpus
,
900 qdev_get_gpio_in(cpudev
, ARM_CPU_FIQ
));
901 sysbus_connect_irq(gicbusdev
, i
+ 2 * smp_cpus
,
902 qdev_get_gpio_in(cpudev
, ARM_CPU_VIRQ
));
903 sysbus_connect_irq(gicbusdev
, i
+ 3 * smp_cpus
,
904 qdev_get_gpio_in(cpudev
, ARM_CPU_VFIQ
));
906 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
) {
907 sysbus_connect_irq(gicbusdev
, i
+ 4 * smp_cpus
,
908 qdev_get_gpio_in(cpudev
, ARM_CPU_NMI
));
909 sysbus_connect_irq(gicbusdev
, i
+ 5 * smp_cpus
,
910 qdev_get_gpio_in(cpudev
, ARM_CPU_VINMI
));
914 fdt_add_gic_node(vms
);
916 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
&& vms
->its
) {
918 } else if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
923 static void create_uart(const VirtMachineState
*vms
, int uart
,
924 MemoryRegion
*mem
, Chardev
*chr
, bool secure
)
927 hwaddr base
= vms
->memmap
[uart
].base
;
928 hwaddr size
= vms
->memmap
[uart
].size
;
929 int irq
= vms
->irqmap
[uart
];
930 const char compat
[] = "arm,pl011\0arm,primecell";
931 const char clocknames
[] = "uartclk\0apb_pclk";
932 DeviceState
*dev
= qdev_new(TYPE_PL011
);
933 SysBusDevice
*s
= SYS_BUS_DEVICE(dev
);
934 MachineState
*ms
= MACHINE(vms
);
936 qdev_prop_set_chr(dev
, "chardev", chr
);
937 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
938 memory_region_add_subregion(mem
, base
,
939 sysbus_mmio_get_region(s
, 0));
940 sysbus_connect_irq(s
, 0, qdev_get_gpio_in(vms
->gic
, irq
));
942 nodename
= g_strdup_printf("/pl011@%" PRIx64
, base
);
943 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
944 /* Note that we can't use setprop_string because of the embedded NUL */
945 qemu_fdt_setprop(ms
->fdt
, nodename
, "compatible",
946 compat
, sizeof(compat
));
947 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
949 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
950 GIC_FDT_IRQ_TYPE_SPI
, irq
,
951 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
952 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "clocks",
953 vms
->clock_phandle
, vms
->clock_phandle
);
954 qemu_fdt_setprop(ms
->fdt
, nodename
, "clock-names",
955 clocknames
, sizeof(clocknames
));
957 if (uart
== VIRT_UART0
) {
958 qemu_fdt_setprop_string(ms
->fdt
, "/chosen", "stdout-path", nodename
);
959 qemu_fdt_setprop_string(ms
->fdt
, "/aliases", "serial0", nodename
);
961 qemu_fdt_setprop_string(ms
->fdt
, "/aliases", "serial1", nodename
);
964 /* Mark as not usable by the normal world */
965 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "status", "disabled");
966 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "secure-status", "okay");
968 qemu_fdt_setprop_string(ms
->fdt
, "/secure-chosen", "stdout-path",
975 static void create_rtc(const VirtMachineState
*vms
)
978 hwaddr base
= vms
->memmap
[VIRT_RTC
].base
;
979 hwaddr size
= vms
->memmap
[VIRT_RTC
].size
;
980 int irq
= vms
->irqmap
[VIRT_RTC
];
981 const char compat
[] = "arm,pl031\0arm,primecell";
982 MachineState
*ms
= MACHINE(vms
);
984 sysbus_create_simple("pl031", base
, qdev_get_gpio_in(vms
->gic
, irq
));
986 nodename
= g_strdup_printf("/pl031@%" PRIx64
, base
);
987 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
988 qemu_fdt_setprop(ms
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
989 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
991 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
992 GIC_FDT_IRQ_TYPE_SPI
, irq
,
993 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
994 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "clocks", vms
->clock_phandle
);
995 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "clock-names", "apb_pclk");
999 static DeviceState
*gpio_key_dev
;
1000 static void virt_powerdown_req(Notifier
*n
, void *opaque
)
1002 VirtMachineState
*s
= container_of(n
, VirtMachineState
, powerdown_notifier
);
1005 acpi_send_event(s
->acpi_dev
, ACPI_POWER_DOWN_STATUS
);
1007 /* use gpio Pin for power button event */
1008 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev
, 0), 1);
1012 static void create_gpio_keys(char *fdt
, DeviceState
*pl061_dev
,
1015 gpio_key_dev
= sysbus_create_simple("gpio-key", -1,
1016 qdev_get_gpio_in(pl061_dev
,
1017 GPIO_PIN_POWER_BUTTON
));
1019 qemu_fdt_add_subnode(fdt
, "/gpio-keys");
1020 qemu_fdt_setprop_string(fdt
, "/gpio-keys", "compatible", "gpio-keys");
1022 qemu_fdt_add_subnode(fdt
, "/gpio-keys/poweroff");
1023 qemu_fdt_setprop_string(fdt
, "/gpio-keys/poweroff",
1024 "label", "GPIO Key Poweroff");
1025 qemu_fdt_setprop_cell(fdt
, "/gpio-keys/poweroff", "linux,code",
1027 qemu_fdt_setprop_cells(fdt
, "/gpio-keys/poweroff",
1028 "gpios", phandle
, GPIO_PIN_POWER_BUTTON
, 0);
1031 #define SECURE_GPIO_POWEROFF 0
1032 #define SECURE_GPIO_RESET 1
1034 static void create_secure_gpio_pwr(char *fdt
, DeviceState
*pl061_dev
,
1037 DeviceState
*gpio_pwr_dev
;
1040 gpio_pwr_dev
= sysbus_create_simple("gpio-pwr", -1, NULL
);
1042 /* connect secure pl061 to gpio-pwr */
1043 qdev_connect_gpio_out(pl061_dev
, SECURE_GPIO_RESET
,
1044 qdev_get_gpio_in_named(gpio_pwr_dev
, "reset", 0));
1045 qdev_connect_gpio_out(pl061_dev
, SECURE_GPIO_POWEROFF
,
1046 qdev_get_gpio_in_named(gpio_pwr_dev
, "shutdown", 0));
1048 qemu_fdt_add_subnode(fdt
, "/gpio-poweroff");
1049 qemu_fdt_setprop_string(fdt
, "/gpio-poweroff", "compatible",
1051 qemu_fdt_setprop_cells(fdt
, "/gpio-poweroff",
1052 "gpios", phandle
, SECURE_GPIO_POWEROFF
, 0);
1053 qemu_fdt_setprop_string(fdt
, "/gpio-poweroff", "status", "disabled");
1054 qemu_fdt_setprop_string(fdt
, "/gpio-poweroff", "secure-status",
1057 qemu_fdt_add_subnode(fdt
, "/gpio-restart");
1058 qemu_fdt_setprop_string(fdt
, "/gpio-restart", "compatible",
1060 qemu_fdt_setprop_cells(fdt
, "/gpio-restart",
1061 "gpios", phandle
, SECURE_GPIO_RESET
, 0);
1062 qemu_fdt_setprop_string(fdt
, "/gpio-restart", "status", "disabled");
1063 qemu_fdt_setprop_string(fdt
, "/gpio-restart", "secure-status",
1067 static void create_gpio_devices(const VirtMachineState
*vms
, int gpio
,
1071 DeviceState
*pl061_dev
;
1072 hwaddr base
= vms
->memmap
[gpio
].base
;
1073 hwaddr size
= vms
->memmap
[gpio
].size
;
1074 int irq
= vms
->irqmap
[gpio
];
1075 const char compat
[] = "arm,pl061\0arm,primecell";
1077 MachineState
*ms
= MACHINE(vms
);
1079 pl061_dev
= qdev_new("pl061");
1080 /* Pull lines down to 0 if not driven by the PL061 */
1081 qdev_prop_set_uint32(pl061_dev
, "pullups", 0);
1082 qdev_prop_set_uint32(pl061_dev
, "pulldowns", 0xff);
1083 s
= SYS_BUS_DEVICE(pl061_dev
);
1084 sysbus_realize_and_unref(s
, &error_fatal
);
1085 memory_region_add_subregion(mem
, base
, sysbus_mmio_get_region(s
, 0));
1086 sysbus_connect_irq(s
, 0, qdev_get_gpio_in(vms
->gic
, irq
));
1088 uint32_t phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
1089 nodename
= g_strdup_printf("/pl061@%" PRIx64
, base
);
1090 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1091 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1093 qemu_fdt_setprop(ms
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
1094 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#gpio-cells", 2);
1095 qemu_fdt_setprop(ms
->fdt
, nodename
, "gpio-controller", NULL
, 0);
1096 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
1097 GIC_FDT_IRQ_TYPE_SPI
, irq
,
1098 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
1099 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "clocks", vms
->clock_phandle
);
1100 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "clock-names", "apb_pclk");
1101 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle", phandle
);
1103 if (gpio
!= VIRT_GPIO
) {
1104 /* Mark as not usable by the normal world */
1105 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "status", "disabled");
1106 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "secure-status", "okay");
1110 /* Child gpio devices */
1111 if (gpio
== VIRT_GPIO
) {
1112 create_gpio_keys(ms
->fdt
, pl061_dev
, phandle
);
1114 create_secure_gpio_pwr(ms
->fdt
, pl061_dev
, phandle
);
1118 static void create_virtio_devices(const VirtMachineState
*vms
)
1121 hwaddr size
= vms
->memmap
[VIRT_MMIO
].size
;
1122 MachineState
*ms
= MACHINE(vms
);
1124 /* We create the transports in forwards order. Since qbus_realize()
1125 * prepends (not appends) new child buses, the incrementing loop below will
1126 * create a list of virtio-mmio buses with decreasing base addresses.
1128 * When a -device option is processed from the command line,
1129 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards
1130 * order. The upshot is that -device options in increasing command line
1131 * order are mapped to virtio-mmio buses with decreasing base addresses.
1133 * When this code was originally written, that arrangement ensured that the
1134 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to
1135 * the first -device on the command line. (The end-to-end order is a
1136 * function of this loop, qbus_realize(), qbus_find_recursive(), and the
1137 * guest kernel's name-to-address assignment strategy.)
1139 * Meanwhile, the kernel's traversal seems to have been reversed; see eg.
1140 * the message, if not necessarily the code, of commit 70161ff336.
1141 * Therefore the loop now establishes the inverse of the original intent.
1143 * Unfortunately, we can't counteract the kernel change by reversing the
1144 * loop; it would break existing command lines.
1146 * In any case, the kernel makes no guarantee about the stability of
1147 * enumeration order of virtio devices (as demonstrated by it changing
1148 * between kernel versions). For reliable and stable identification
1149 * of disks users must use UUIDs or similar mechanisms.
1151 for (i
= 0; i
< NUM_VIRTIO_TRANSPORTS
; i
++) {
1152 int irq
= vms
->irqmap
[VIRT_MMIO
] + i
;
1153 hwaddr base
= vms
->memmap
[VIRT_MMIO
].base
+ i
* size
;
1155 sysbus_create_simple("virtio-mmio", base
,
1156 qdev_get_gpio_in(vms
->gic
, irq
));
1159 /* We add dtb nodes in reverse order so that they appear in the finished
1160 * device tree lowest address first.
1162 * Note that this mapping is independent of the loop above. The previous
1163 * loop influences virtio device to virtio transport assignment, whereas
1164 * this loop controls how virtio transports are laid out in the dtb.
1166 for (i
= NUM_VIRTIO_TRANSPORTS
- 1; i
>= 0; i
--) {
1168 int irq
= vms
->irqmap
[VIRT_MMIO
] + i
;
1169 hwaddr base
= vms
->memmap
[VIRT_MMIO
].base
+ i
* size
;
1171 nodename
= g_strdup_printf("/virtio_mmio@%" PRIx64
, base
);
1172 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1173 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
1174 "compatible", "virtio,mmio");
1175 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1177 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
1178 GIC_FDT_IRQ_TYPE_SPI
, irq
,
1179 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
);
1180 qemu_fdt_setprop(ms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1185 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
1187 static PFlashCFI01
*virt_flash_create1(VirtMachineState
*vms
,
1189 const char *alias_prop_name
)
1192 * Create a single flash device. We use the same parameters as
1193 * the flash devices on the Versatile Express board.
1195 DeviceState
*dev
= qdev_new(TYPE_PFLASH_CFI01
);
1197 qdev_prop_set_uint64(dev
, "sector-length", VIRT_FLASH_SECTOR_SIZE
);
1198 qdev_prop_set_uint8(dev
, "width", 4);
1199 qdev_prop_set_uint8(dev
, "device-width", 2);
1200 qdev_prop_set_bit(dev
, "big-endian", false);
1201 qdev_prop_set_uint16(dev
, "id0", 0x89);
1202 qdev_prop_set_uint16(dev
, "id1", 0x18);
1203 qdev_prop_set_uint16(dev
, "id2", 0x00);
1204 qdev_prop_set_uint16(dev
, "id3", 0x00);
1205 qdev_prop_set_string(dev
, "name", name
);
1206 object_property_add_child(OBJECT(vms
), name
, OBJECT(dev
));
1207 object_property_add_alias(OBJECT(vms
), alias_prop_name
,
1208 OBJECT(dev
), "drive");
1209 return PFLASH_CFI01(dev
);
1212 static void virt_flash_create(VirtMachineState
*vms
)
1214 vms
->flash
[0] = virt_flash_create1(vms
, "virt.flash0", "pflash0");
1215 vms
->flash
[1] = virt_flash_create1(vms
, "virt.flash1", "pflash1");
1218 static void virt_flash_map1(PFlashCFI01
*flash
,
1219 hwaddr base
, hwaddr size
,
1220 MemoryRegion
*sysmem
)
1222 DeviceState
*dev
= DEVICE(flash
);
1224 assert(QEMU_IS_ALIGNED(size
, VIRT_FLASH_SECTOR_SIZE
));
1225 assert(size
/ VIRT_FLASH_SECTOR_SIZE
<= UINT32_MAX
);
1226 qdev_prop_set_uint32(dev
, "num-blocks", size
/ VIRT_FLASH_SECTOR_SIZE
);
1227 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1229 memory_region_add_subregion(sysmem
, base
,
1230 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
),
1234 static void virt_flash_map(VirtMachineState
*vms
,
1235 MemoryRegion
*sysmem
,
1236 MemoryRegion
*secure_sysmem
)
1239 * Map two flash devices to fill the VIRT_FLASH space in the memmap.
1240 * sysmem is the system memory space. secure_sysmem is the secure view
1241 * of the system, and the first flash device should be made visible only
1242 * there. The second flash device is visible to both secure and nonsecure.
1243 * If sysmem == secure_sysmem this means there is no separate Secure
1244 * address space and both flash devices are generally visible.
1246 hwaddr flashsize
= vms
->memmap
[VIRT_FLASH
].size
/ 2;
1247 hwaddr flashbase
= vms
->memmap
[VIRT_FLASH
].base
;
1249 virt_flash_map1(vms
->flash
[0], flashbase
, flashsize
,
1251 virt_flash_map1(vms
->flash
[1], flashbase
+ flashsize
, flashsize
,
1255 static void virt_flash_fdt(VirtMachineState
*vms
,
1256 MemoryRegion
*sysmem
,
1257 MemoryRegion
*secure_sysmem
)
1259 hwaddr flashsize
= vms
->memmap
[VIRT_FLASH
].size
/ 2;
1260 hwaddr flashbase
= vms
->memmap
[VIRT_FLASH
].base
;
1261 MachineState
*ms
= MACHINE(vms
);
1264 if (sysmem
== secure_sysmem
) {
1265 /* Report both flash devices as a single node in the DT */
1266 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
1267 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1268 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible", "cfi-flash");
1269 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1270 2, flashbase
, 2, flashsize
,
1271 2, flashbase
+ flashsize
, 2, flashsize
);
1272 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "bank-width", 4);
1276 * Report the devices as separate nodes so we can mark one as
1277 * only visible to the secure world.
1279 nodename
= g_strdup_printf("/secflash@%" PRIx64
, flashbase
);
1280 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1281 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible", "cfi-flash");
1282 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1283 2, flashbase
, 2, flashsize
);
1284 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "bank-width", 4);
1285 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "status", "disabled");
1286 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "secure-status", "okay");
1289 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
+ flashsize
);
1290 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1291 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible", "cfi-flash");
1292 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1293 2, flashbase
+ flashsize
, 2, flashsize
);
1294 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "bank-width", 4);
1299 static bool virt_firmware_init(VirtMachineState
*vms
,
1300 MemoryRegion
*sysmem
,
1301 MemoryRegion
*secure_sysmem
)
1304 const char *bios_name
;
1305 BlockBackend
*pflash_blk0
;
1307 /* Map legacy -drive if=pflash to machine properties */
1308 for (i
= 0; i
< ARRAY_SIZE(vms
->flash
); i
++) {
1309 pflash_cfi01_legacy_drive(vms
->flash
[i
],
1310 drive_get(IF_PFLASH
, 0, i
));
1313 virt_flash_map(vms
, sysmem
, secure_sysmem
);
1315 pflash_blk0
= pflash_cfi01_get_blk(vms
->flash
[0]);
1317 bios_name
= MACHINE(vms
)->firmware
;
1324 error_report("The contents of the first flash device may be "
1325 "specified with -bios or with -drive if=pflash... "
1326 "but you cannot use both options at once");
1330 /* Fall back to -bios */
1332 fname
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
1334 error_report("Could not find ROM image '%s'", bios_name
);
1337 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(vms
->flash
[0]), 0);
1338 image_size
= load_image_mr(fname
, mr
);
1340 if (image_size
< 0) {
1341 error_report("Could not load ROM image '%s'", bios_name
);
1346 return pflash_blk0
|| bios_name
;
1349 static FWCfgState
*create_fw_cfg(const VirtMachineState
*vms
, AddressSpace
*as
)
1351 MachineState
*ms
= MACHINE(vms
);
1352 hwaddr base
= vms
->memmap
[VIRT_FW_CFG
].base
;
1353 hwaddr size
= vms
->memmap
[VIRT_FW_CFG
].size
;
1357 fw_cfg
= fw_cfg_init_mem_wide(base
+ 8, base
, 8, base
+ 16, as
);
1358 fw_cfg_add_i16(fw_cfg
, FW_CFG_NB_CPUS
, (uint16_t)ms
->smp
.cpus
);
1360 nodename
= g_strdup_printf("/fw-cfg@%" PRIx64
, base
);
1361 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1362 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
1363 "compatible", "qemu,fw-cfg-mmio");
1364 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1366 qemu_fdt_setprop(ms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1371 static void create_pcie_irq_map(const MachineState
*ms
,
1372 uint32_t gic_phandle
,
1373 int first_irq
, const char *nodename
)
1376 uint32_t full_irq_map
[4 * 4 * 10] = { 0 };
1377 uint32_t *irq_map
= full_irq_map
;
1379 for (devfn
= 0; devfn
<= 0x18; devfn
+= 0x8) {
1380 for (pin
= 0; pin
< 4; pin
++) {
1381 int irq_type
= GIC_FDT_IRQ_TYPE_SPI
;
1382 int irq_nr
= first_irq
+ ((pin
+ PCI_SLOT(devfn
)) % PCI_NUM_PINS
);
1383 int irq_level
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
1387 devfn
<< 8, 0, 0, /* devfn */
1388 pin
+ 1, /* PCI pin */
1389 gic_phandle
, 0, 0, irq_type
, irq_nr
, irq_level
}; /* GIC irq */
1391 /* Convert map to big endian */
1392 for (i
= 0; i
< 10; i
++) {
1393 irq_map
[i
] = cpu_to_be32(map
[i
]);
1399 qemu_fdt_setprop(ms
->fdt
, nodename
, "interrupt-map",
1400 full_irq_map
, sizeof(full_irq_map
));
1402 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupt-map-mask",
1403 cpu_to_be16(PCI_DEVFN(3, 0)), /* Slot 3 */
1408 static void create_smmu(const VirtMachineState
*vms
,
1412 const char compat
[] = "arm,smmu-v3";
1413 int irq
= vms
->irqmap
[VIRT_SMMU
];
1415 hwaddr base
= vms
->memmap
[VIRT_SMMU
].base
;
1416 hwaddr size
= vms
->memmap
[VIRT_SMMU
].size
;
1417 const char irq_names
[] = "eventq\0priq\0cmdq-sync\0gerror";
1419 MachineState
*ms
= MACHINE(vms
);
1421 if (vms
->iommu
!= VIRT_IOMMU_SMMUV3
|| !vms
->iommu_phandle
) {
1425 dev
= qdev_new(TYPE_ARM_SMMUV3
);
1427 object_property_set_link(OBJECT(dev
), "primary-bus", OBJECT(bus
),
1429 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1430 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, base
);
1431 for (i
= 0; i
< NUM_SMMU_IRQS
; i
++) {
1432 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
1433 qdev_get_gpio_in(vms
->gic
, irq
+ i
));
1436 node
= g_strdup_printf("/smmuv3@%" PRIx64
, base
);
1437 qemu_fdt_add_subnode(ms
->fdt
, node
);
1438 qemu_fdt_setprop(ms
->fdt
, node
, "compatible", compat
, sizeof(compat
));
1439 qemu_fdt_setprop_sized_cells(ms
->fdt
, node
, "reg", 2, base
, 2, size
);
1441 qemu_fdt_setprop_cells(ms
->fdt
, node
, "interrupts",
1442 GIC_FDT_IRQ_TYPE_SPI
, irq
, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1443 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1444 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1445 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
);
1447 qemu_fdt_setprop(ms
->fdt
, node
, "interrupt-names", irq_names
,
1450 qemu_fdt_setprop(ms
->fdt
, node
, "dma-coherent", NULL
, 0);
1452 qemu_fdt_setprop_cell(ms
->fdt
, node
, "#iommu-cells", 1);
1454 qemu_fdt_setprop_cell(ms
->fdt
, node
, "phandle", vms
->iommu_phandle
);
1458 static void create_virtio_iommu_dt_bindings(VirtMachineState
*vms
)
1460 const char compat
[] = "virtio,pci-iommu\0pci1af4,1057";
1461 uint16_t bdf
= vms
->virtio_iommu_bdf
;
1462 MachineState
*ms
= MACHINE(vms
);
1465 vms
->iommu_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
1467 node
= g_strdup_printf("%s/virtio_iommu@%x,%x", vms
->pciehb_nodename
,
1468 PCI_SLOT(bdf
), PCI_FUNC(bdf
));
1469 qemu_fdt_add_subnode(ms
->fdt
, node
);
1470 qemu_fdt_setprop(ms
->fdt
, node
, "compatible", compat
, sizeof(compat
));
1471 qemu_fdt_setprop_sized_cells(ms
->fdt
, node
, "reg",
1472 1, bdf
<< 8, 1, 0, 1, 0,
1475 qemu_fdt_setprop_cell(ms
->fdt
, node
, "#iommu-cells", 1);
1476 qemu_fdt_setprop_cell(ms
->fdt
, node
, "phandle", vms
->iommu_phandle
);
1479 qemu_fdt_setprop_cells(ms
->fdt
, vms
->pciehb_nodename
, "iommu-map",
1480 0x0, vms
->iommu_phandle
, 0x0, bdf
,
1481 bdf
+ 1, vms
->iommu_phandle
, bdf
+ 1, 0xffff - bdf
);
1484 static void create_pcie(VirtMachineState
*vms
)
1486 hwaddr base_mmio
= vms
->memmap
[VIRT_PCIE_MMIO
].base
;
1487 hwaddr size_mmio
= vms
->memmap
[VIRT_PCIE_MMIO
].size
;
1488 hwaddr base_mmio_high
= vms
->memmap
[VIRT_HIGH_PCIE_MMIO
].base
;
1489 hwaddr size_mmio_high
= vms
->memmap
[VIRT_HIGH_PCIE_MMIO
].size
;
1490 hwaddr base_pio
= vms
->memmap
[VIRT_PCIE_PIO
].base
;
1491 hwaddr size_pio
= vms
->memmap
[VIRT_PCIE_PIO
].size
;
1492 hwaddr base_ecam
, size_ecam
;
1493 hwaddr base
= base_mmio
;
1495 int irq
= vms
->irqmap
[VIRT_PCIE
];
1496 MemoryRegion
*mmio_alias
;
1497 MemoryRegion
*mmio_reg
;
1498 MemoryRegion
*ecam_alias
;
1499 MemoryRegion
*ecam_reg
;
1504 MachineState
*ms
= MACHINE(vms
);
1505 MachineClass
*mc
= MACHINE_GET_CLASS(ms
);
1507 dev
= qdev_new(TYPE_GPEX_HOST
);
1508 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1510 ecam_id
= VIRT_ECAM_ID(vms
->highmem_ecam
);
1511 base_ecam
= vms
->memmap
[ecam_id
].base
;
1512 size_ecam
= vms
->memmap
[ecam_id
].size
;
1513 nr_pcie_buses
= size_ecam
/ PCIE_MMCFG_SIZE_MIN
;
1514 /* Map only the first size_ecam bytes of ECAM space */
1515 ecam_alias
= g_new0(MemoryRegion
, 1);
1516 ecam_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0);
1517 memory_region_init_alias(ecam_alias
, OBJECT(dev
), "pcie-ecam",
1518 ecam_reg
, 0, size_ecam
);
1519 memory_region_add_subregion(get_system_memory(), base_ecam
, ecam_alias
);
1521 /* Map the MMIO window into system address space so as to expose
1522 * the section of PCI MMIO space which starts at the same base address
1523 * (ie 1:1 mapping for that part of PCI MMIO space visible through
1526 mmio_alias
= g_new0(MemoryRegion
, 1);
1527 mmio_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 1);
1528 memory_region_init_alias(mmio_alias
, OBJECT(dev
), "pcie-mmio",
1529 mmio_reg
, base_mmio
, size_mmio
);
1530 memory_region_add_subregion(get_system_memory(), base_mmio
, mmio_alias
);
1532 if (vms
->highmem_mmio
) {
1533 /* Map high MMIO space */
1534 MemoryRegion
*high_mmio_alias
= g_new0(MemoryRegion
, 1);
1536 memory_region_init_alias(high_mmio_alias
, OBJECT(dev
), "pcie-mmio-high",
1537 mmio_reg
, base_mmio_high
, size_mmio_high
);
1538 memory_region_add_subregion(get_system_memory(), base_mmio_high
,
1542 /* Map IO port space */
1543 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 2, base_pio
);
1545 for (i
= 0; i
< GPEX_NUM_IRQS
; i
++) {
1546 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
1547 qdev_get_gpio_in(vms
->gic
, irq
+ i
));
1548 gpex_set_irq_num(GPEX_HOST(dev
), i
, irq
+ i
);
1551 pci
= PCI_HOST_BRIDGE(dev
);
1552 pci
->bypass_iommu
= vms
->default_bus_bypass_iommu
;
1553 vms
->bus
= pci
->bus
;
1555 pci_init_nic_devices(pci
->bus
, mc
->default_nic
);
1558 nodename
= vms
->pciehb_nodename
= g_strdup_printf("/pcie@%" PRIx64
, base
);
1559 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1560 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
1561 "compatible", "pci-host-ecam-generic");
1562 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "device_type", "pci");
1563 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#address-cells", 3);
1564 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#size-cells", 2);
1565 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "linux,pci-domain", 0);
1566 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "bus-range", 0,
1568 qemu_fdt_setprop(ms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1570 if (vms
->msi_phandle
) {
1571 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "msi-map",
1572 0, vms
->msi_phandle
, 0, 0x10000);
1575 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1576 2, base_ecam
, 2, size_ecam
);
1578 if (vms
->highmem_mmio
) {
1579 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "ranges",
1580 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
1581 2, base_pio
, 2, size_pio
,
1582 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
1583 2, base_mmio
, 2, size_mmio
,
1584 1, FDT_PCI_RANGE_MMIO_64BIT
,
1586 2, base_mmio_high
, 2, size_mmio_high
);
1588 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "ranges",
1589 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
1590 2, base_pio
, 2, size_pio
,
1591 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
1592 2, base_mmio
, 2, size_mmio
);
1595 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#interrupt-cells", 1);
1596 create_pcie_irq_map(ms
, vms
->gic_phandle
, irq
, nodename
);
1599 vms
->iommu_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
1601 switch (vms
->iommu
) {
1602 case VIRT_IOMMU_SMMUV3
:
1603 create_smmu(vms
, vms
->bus
);
1604 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "iommu-map",
1605 0x0, vms
->iommu_phandle
, 0x0, 0x10000);
1608 g_assert_not_reached();
1613 static void create_platform_bus(VirtMachineState
*vms
)
1618 MemoryRegion
*sysmem
= get_system_memory();
1620 dev
= qdev_new(TYPE_PLATFORM_BUS_DEVICE
);
1621 dev
->id
= g_strdup(TYPE_PLATFORM_BUS_DEVICE
);
1622 qdev_prop_set_uint32(dev
, "num_irqs", PLATFORM_BUS_NUM_IRQS
);
1623 qdev_prop_set_uint32(dev
, "mmio_size", vms
->memmap
[VIRT_PLATFORM_BUS
].size
);
1624 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1625 vms
->platform_bus_dev
= dev
;
1627 s
= SYS_BUS_DEVICE(dev
);
1628 for (i
= 0; i
< PLATFORM_BUS_NUM_IRQS
; i
++) {
1629 int irq
= vms
->irqmap
[VIRT_PLATFORM_BUS
] + i
;
1630 sysbus_connect_irq(s
, i
, qdev_get_gpio_in(vms
->gic
, irq
));
1633 memory_region_add_subregion(sysmem
,
1634 vms
->memmap
[VIRT_PLATFORM_BUS
].base
,
1635 sysbus_mmio_get_region(s
, 0));
1638 static void create_tag_ram(MemoryRegion
*tag_sysmem
,
1639 hwaddr base
, hwaddr size
,
1642 MemoryRegion
*tagram
= g_new(MemoryRegion
, 1);
1644 memory_region_init_ram(tagram
, NULL
, name
, size
/ 32, &error_fatal
);
1645 memory_region_add_subregion(tag_sysmem
, base
/ 32, tagram
);
1648 static void create_secure_ram(VirtMachineState
*vms
,
1649 MemoryRegion
*secure_sysmem
,
1650 MemoryRegion
*secure_tag_sysmem
)
1652 MemoryRegion
*secram
= g_new(MemoryRegion
, 1);
1654 hwaddr base
= vms
->memmap
[VIRT_SECURE_MEM
].base
;
1655 hwaddr size
= vms
->memmap
[VIRT_SECURE_MEM
].size
;
1656 MachineState
*ms
= MACHINE(vms
);
1658 memory_region_init_ram(secram
, NULL
, "virt.secure-ram", size
,
1660 memory_region_add_subregion(secure_sysmem
, base
, secram
);
1662 nodename
= g_strdup_printf("/secram@%" PRIx64
, base
);
1663 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1664 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "device_type", "memory");
1665 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg", 2, base
, 2, size
);
1666 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "status", "disabled");
1667 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "secure-status", "okay");
1669 if (secure_tag_sysmem
) {
1670 create_tag_ram(secure_tag_sysmem
, base
, size
, "mach-virt.secure-tag");
1676 static void *machvirt_dtb(const struct arm_boot_info
*binfo
, int *fdt_size
)
1678 const VirtMachineState
*board
= container_of(binfo
, VirtMachineState
,
1680 MachineState
*ms
= MACHINE(board
);
1683 *fdt_size
= board
->fdt_size
;
1687 static void virt_build_smbios(VirtMachineState
*vms
)
1689 MachineClass
*mc
= MACHINE_GET_CLASS(vms
);
1690 MachineState
*ms
= MACHINE(vms
);
1691 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
1692 uint8_t *smbios_tables
, *smbios_anchor
;
1693 size_t smbios_tables_len
, smbios_anchor_len
;
1694 struct smbios_phys_mem_area mem_array
;
1695 const char *product
= "QEMU Virtual Machine";
1697 if (kvm_enabled()) {
1698 product
= "KVM Virtual Machine";
1701 smbios_set_defaults("QEMU", product
,
1702 vmc
->smbios_old_sys_ver
? "1.0" : mc
->name
);
1704 /* build the array of physical mem area from base_memmap */
1705 mem_array
.address
= vms
->memmap
[VIRT_MEM
].base
;
1706 mem_array
.length
= ms
->ram_size
;
1708 smbios_get_tables(ms
, SMBIOS_ENTRY_POINT_TYPE_64
, &mem_array
, 1,
1709 &smbios_tables
, &smbios_tables_len
,
1710 &smbios_anchor
, &smbios_anchor_len
,
1713 if (smbios_anchor
) {
1714 fw_cfg_add_file(vms
->fw_cfg
, "etc/smbios/smbios-tables",
1715 smbios_tables
, smbios_tables_len
);
1716 fw_cfg_add_file(vms
->fw_cfg
, "etc/smbios/smbios-anchor",
1717 smbios_anchor
, smbios_anchor_len
);
1722 void virt_machine_done(Notifier
*notifier
, void *data
)
1724 VirtMachineState
*vms
= container_of(notifier
, VirtMachineState
,
1726 MachineState
*ms
= MACHINE(vms
);
1727 ARMCPU
*cpu
= ARM_CPU(first_cpu
);
1728 struct arm_boot_info
*info
= &vms
->bootinfo
;
1729 AddressSpace
*as
= arm_boot_address_space(cpu
, info
);
1732 * If the user provided a dtb, we assume the dynamic sysbus nodes
1733 * already are integrated there. This corresponds to a use case where
1734 * the dynamic sysbus nodes are complex and their generation is not yet
1735 * supported. In that case the user can take charge of the guest dt
1736 * while qemu takes charge of the qom stuff.
1738 if (info
->dtb_filename
== NULL
) {
1739 platform_bus_add_all_fdt_nodes(ms
->fdt
, "/intc",
1740 vms
->memmap
[VIRT_PLATFORM_BUS
].base
,
1741 vms
->memmap
[VIRT_PLATFORM_BUS
].size
,
1742 vms
->irqmap
[VIRT_PLATFORM_BUS
]);
1744 if (arm_load_dtb(info
->dtb_start
, info
, info
->dtb_limit
, as
, ms
) < 0) {
1748 fw_cfg_add_extra_pci_roots(vms
->bus
, vms
->fw_cfg
);
1750 virt_acpi_setup(vms
);
1751 virt_build_smbios(vms
);
1754 static uint64_t virt_cpu_mp_affinity(VirtMachineState
*vms
, int idx
)
1756 uint8_t clustersz
= ARM_DEFAULT_CPUS_PER_CLUSTER
;
1757 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
1759 if (!vmc
->disallow_affinity_adjustment
) {
1760 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the
1761 * GIC's target-list limitations. 32-bit KVM hosts currently
1762 * always create clusters of 4 CPUs, but that is expected to
1763 * change when they gain support for gicv3. When KVM is enabled
1764 * it will override the changes we make here, therefore our
1765 * purposes are to make TCG consistent (with 64-bit KVM hosts)
1766 * and to improve SGI efficiency.
1768 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
1769 clustersz
= GIC_TARGETLIST_BITS
;
1771 clustersz
= GICV3_TARGETLIST_BITS
;
1774 return arm_build_mp_affinity(idx
, clustersz
);
1777 static inline bool *virt_get_high_memmap_enabled(VirtMachineState
*vms
,
1780 bool *enabled_array
[] = {
1781 &vms
->highmem_redists
,
1786 assert(ARRAY_SIZE(extended_memmap
) - VIRT_LOWMEMMAP_LAST
==
1787 ARRAY_SIZE(enabled_array
));
1788 assert(index
- VIRT_LOWMEMMAP_LAST
< ARRAY_SIZE(enabled_array
));
1790 return enabled_array
[index
- VIRT_LOWMEMMAP_LAST
];
1793 static void virt_set_high_memmap(VirtMachineState
*vms
,
1794 hwaddr base
, int pa_bits
)
1796 hwaddr region_base
, region_size
;
1797 bool *region_enabled
, fits
;
1800 for (i
= VIRT_LOWMEMMAP_LAST
; i
< ARRAY_SIZE(extended_memmap
); i
++) {
1801 region_enabled
= virt_get_high_memmap_enabled(vms
, i
);
1802 region_base
= ROUND_UP(base
, extended_memmap
[i
].size
);
1803 region_size
= extended_memmap
[i
].size
;
1805 vms
->memmap
[i
].base
= region_base
;
1806 vms
->memmap
[i
].size
= region_size
;
1809 * Check each device to see if it fits in the PA space,
1810 * moving highest_gpa as we go. For compatibility, move
1811 * highest_gpa for disabled fitting devices as well, if
1812 * the compact layout has been disabled.
1814 * For each device that doesn't fit, disable it.
1816 fits
= (region_base
+ region_size
) <= BIT_ULL(pa_bits
);
1817 *region_enabled
&= fits
;
1818 if (vms
->highmem_compact
&& !*region_enabled
) {
1822 base
= region_base
+ region_size
;
1824 vms
->highest_gpa
= base
- 1;
1829 static void virt_set_memmap(VirtMachineState
*vms
, int pa_bits
)
1831 MachineState
*ms
= MACHINE(vms
);
1832 hwaddr base
, device_memory_base
, device_memory_size
, memtop
;
1835 vms
->memmap
= extended_memmap
;
1837 for (i
= 0; i
< ARRAY_SIZE(base_memmap
); i
++) {
1838 vms
->memmap
[i
] = base_memmap
[i
];
1841 if (ms
->ram_slots
> ACPI_MAX_RAM_SLOTS
) {
1842 error_report("unsupported number of memory slots: %"PRIu64
,
1848 * !highmem is exactly the same as limiting the PA space to 32bit,
1849 * irrespective of the underlying capabilities of the HW.
1851 if (!vms
->highmem
) {
1856 * We compute the base of the high IO region depending on the
1857 * amount of initial and device memory. The device memory start/size
1858 * is aligned on 1GiB. We never put the high IO region below 256GiB
1859 * so that if maxram_size is < 255GiB we keep the legacy memory map.
1860 * The device region size assumes 1GiB page max alignment per slot.
1862 device_memory_base
=
1863 ROUND_UP(vms
->memmap
[VIRT_MEM
].base
+ ms
->ram_size
, GiB
);
1864 device_memory_size
= ms
->maxram_size
- ms
->ram_size
+ ms
->ram_slots
* GiB
;
1866 /* Base address of the high IO region */
1867 memtop
= base
= device_memory_base
+ ROUND_UP(device_memory_size
, GiB
);
1868 if (memtop
> BIT_ULL(pa_bits
)) {
1869 error_report("Addressing limited to %d bits, but memory exceeds it by %llu bytes",
1870 pa_bits
, memtop
- BIT_ULL(pa_bits
));
1873 if (base
< device_memory_base
) {
1874 error_report("maxmem/slots too huge");
1877 if (base
< vms
->memmap
[VIRT_MEM
].base
+ LEGACY_RAMLIMIT_BYTES
) {
1878 base
= vms
->memmap
[VIRT_MEM
].base
+ LEGACY_RAMLIMIT_BYTES
;
1881 /* We know for sure that at least the memory fits in the PA space */
1882 vms
->highest_gpa
= memtop
- 1;
1884 virt_set_high_memmap(vms
, base
, pa_bits
);
1886 if (device_memory_size
> 0) {
1887 machine_memory_devices_init(ms
, device_memory_base
, device_memory_size
);
1891 static VirtGICType
finalize_gic_version_do(const char *accel_name
,
1892 VirtGICType gic_version
,
1894 unsigned int max_cpus
)
1896 /* Convert host/max/nosel to GIC version number */
1897 switch (gic_version
) {
1898 case VIRT_GIC_VERSION_HOST
:
1899 if (!kvm_enabled()) {
1900 error_report("gic-version=host requires KVM");
1904 /* For KVM, gic-version=host means gic-version=max */
1905 return finalize_gic_version_do(accel_name
, VIRT_GIC_VERSION_MAX
,
1906 gics_supported
, max_cpus
);
1907 case VIRT_GIC_VERSION_MAX
:
1908 if (gics_supported
& VIRT_GIC_VERSION_4_MASK
) {
1909 gic_version
= VIRT_GIC_VERSION_4
;
1910 } else if (gics_supported
& VIRT_GIC_VERSION_3_MASK
) {
1911 gic_version
= VIRT_GIC_VERSION_3
;
1913 gic_version
= VIRT_GIC_VERSION_2
;
1916 case VIRT_GIC_VERSION_NOSEL
:
1917 if ((gics_supported
& VIRT_GIC_VERSION_2_MASK
) &&
1918 max_cpus
<= GIC_NCPU
) {
1919 gic_version
= VIRT_GIC_VERSION_2
;
1920 } else if (gics_supported
& VIRT_GIC_VERSION_3_MASK
) {
1922 * in case the host does not support v2 emulation or
1923 * the end-user requested more than 8 VCPUs we now default
1924 * to v3. In any case defaulting to v2 would be broken.
1926 gic_version
= VIRT_GIC_VERSION_3
;
1927 } else if (max_cpus
> GIC_NCPU
) {
1928 error_report("%s only supports GICv2 emulation but more than 8 "
1929 "vcpus are requested", accel_name
);
1933 case VIRT_GIC_VERSION_2
:
1934 case VIRT_GIC_VERSION_3
:
1935 case VIRT_GIC_VERSION_4
:
1939 /* Check chosen version is effectively supported */
1940 switch (gic_version
) {
1941 case VIRT_GIC_VERSION_2
:
1942 if (!(gics_supported
& VIRT_GIC_VERSION_2_MASK
)) {
1943 error_report("%s does not support GICv2 emulation", accel_name
);
1947 case VIRT_GIC_VERSION_3
:
1948 if (!(gics_supported
& VIRT_GIC_VERSION_3_MASK
)) {
1949 error_report("%s does not support GICv3 emulation", accel_name
);
1953 case VIRT_GIC_VERSION_4
:
1954 if (!(gics_supported
& VIRT_GIC_VERSION_4_MASK
)) {
1955 error_report("%s does not support GICv4 emulation, is virtualization=on?",
1961 error_report("logic error in finalize_gic_version");
1970 * finalize_gic_version - Determines the final gic_version
1971 * according to the gic-version property
1973 * Default GIC type is v2
1975 static void finalize_gic_version(VirtMachineState
*vms
)
1977 const char *accel_name
= current_accel_name();
1978 unsigned int max_cpus
= MACHINE(vms
)->smp
.max_cpus
;
1979 int gics_supported
= 0;
1981 /* Determine which GIC versions the current environment supports */
1982 if (kvm_enabled() && kvm_irqchip_in_kernel()) {
1983 int probe_bitmap
= kvm_arm_vgic_probe();
1985 if (!probe_bitmap
) {
1986 error_report("Unable to determine GIC version supported by host");
1990 if (probe_bitmap
& KVM_ARM_VGIC_V2
) {
1991 gics_supported
|= VIRT_GIC_VERSION_2_MASK
;
1993 if (probe_bitmap
& KVM_ARM_VGIC_V3
) {
1994 gics_supported
|= VIRT_GIC_VERSION_3_MASK
;
1996 } else if (kvm_enabled() && !kvm_irqchip_in_kernel()) {
1997 /* KVM w/o kernel irqchip can only deal with GICv2 */
1998 gics_supported
|= VIRT_GIC_VERSION_2_MASK
;
1999 accel_name
= "KVM with kernel-irqchip=off";
2000 } else if (tcg_enabled() || hvf_enabled() || qtest_enabled()) {
2001 gics_supported
|= VIRT_GIC_VERSION_2_MASK
;
2002 if (module_object_class_by_name("arm-gicv3")) {
2003 gics_supported
|= VIRT_GIC_VERSION_3_MASK
;
2005 /* GICv4 only makes sense if CPU has EL2 */
2006 gics_supported
|= VIRT_GIC_VERSION_4_MASK
;
2010 error_report("Unsupported accelerator, can not determine GIC support");
2015 * Then convert helpers like host/max to concrete GIC versions and ensure
2016 * the desired version is supported
2018 vms
->gic_version
= finalize_gic_version_do(accel_name
, vms
->gic_version
,
2019 gics_supported
, max_cpus
);
2023 * virt_cpu_post_init() must be called after the CPUs have
2024 * been realized and the GIC has been created.
2026 static void virt_cpu_post_init(VirtMachineState
*vms
, MemoryRegion
*sysmem
)
2028 int max_cpus
= MACHINE(vms
)->smp
.max_cpus
;
2029 bool aarch64
, pmu
, steal_time
;
2032 aarch64
= object_property_get_bool(OBJECT(first_cpu
), "aarch64", NULL
);
2033 pmu
= object_property_get_bool(OBJECT(first_cpu
), "pmu", NULL
);
2034 steal_time
= object_property_get_bool(OBJECT(first_cpu
),
2035 "kvm-steal-time", NULL
);
2037 if (kvm_enabled()) {
2038 hwaddr pvtime_reg_base
= vms
->memmap
[VIRT_PVTIME
].base
;
2039 hwaddr pvtime_reg_size
= vms
->memmap
[VIRT_PVTIME
].size
;
2042 MemoryRegion
*pvtime
= g_new(MemoryRegion
, 1);
2043 hwaddr pvtime_size
= max_cpus
* PVTIME_SIZE_PER_CPU
;
2045 /* The memory region size must be a multiple of host page size. */
2046 pvtime_size
= REAL_HOST_PAGE_ALIGN(pvtime_size
);
2048 if (pvtime_size
> pvtime_reg_size
) {
2049 error_report("pvtime requires a %" HWADDR_PRId
2050 " byte memory region for %d CPUs,"
2051 " but only %" HWADDR_PRId
" has been reserved",
2052 pvtime_size
, max_cpus
, pvtime_reg_size
);
2056 memory_region_init_ram(pvtime
, NULL
, "pvtime", pvtime_size
, NULL
);
2057 memory_region_add_subregion(sysmem
, pvtime_reg_base
, pvtime
);
2062 assert(arm_feature(&ARM_CPU(cpu
)->env
, ARM_FEATURE_PMU
));
2063 if (kvm_irqchip_in_kernel()) {
2064 kvm_arm_pmu_set_irq(ARM_CPU(cpu
), VIRTUAL_PMU_IRQ
);
2066 kvm_arm_pmu_init(ARM_CPU(cpu
));
2069 kvm_arm_pvtime_init(ARM_CPU(cpu
), pvtime_reg_base
2071 * PVTIME_SIZE_PER_CPU
);
2075 if (aarch64
&& vms
->highmem
) {
2076 int requested_pa_size
= 64 - clz64(vms
->highest_gpa
);
2077 int pamax
= arm_pamax(ARM_CPU(first_cpu
));
2079 if (pamax
< requested_pa_size
) {
2080 error_report("VCPU supports less PA bits (%d) than "
2081 "requested by the memory map (%d)",
2082 pamax
, requested_pa_size
);
2089 static void machvirt_init(MachineState
*machine
)
2091 VirtMachineState
*vms
= VIRT_MACHINE(machine
);
2092 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(machine
);
2093 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2094 const CPUArchIdList
*possible_cpus
;
2095 MemoryRegion
*sysmem
= get_system_memory();
2096 MemoryRegion
*secure_sysmem
= NULL
;
2097 MemoryRegion
*tag_sysmem
= NULL
;
2098 MemoryRegion
*secure_tag_sysmem
= NULL
;
2099 int n
, virt_max_cpus
;
2100 bool firmware_loaded
;
2101 bool aarch64
= true;
2102 bool has_ged
= !vmc
->no_ged
;
2103 unsigned int smp_cpus
= machine
->smp
.cpus
;
2104 unsigned int max_cpus
= machine
->smp
.max_cpus
;
2106 possible_cpus
= mc
->possible_cpu_arch_ids(machine
);
2109 * In accelerated mode, the memory map is computed earlier in kvm_type()
2110 * to create a VM with the right number of IPA bits.
2118 * Instantiate a temporary CPU object to find out about what
2119 * we are about to deal with. Once this is done, get rid of
2122 cpuobj
= object_new(possible_cpus
->cpus
[0].type
);
2123 armcpu
= ARM_CPU(cpuobj
);
2125 pa_bits
= arm_pamax(armcpu
);
2127 object_unref(cpuobj
);
2129 virt_set_memmap(vms
, pa_bits
);
2132 /* We can probe only here because during property set
2133 * KVM is not available yet
2135 finalize_gic_version(vms
);
2139 * The Secure view of the world is the same as the NonSecure,
2140 * but with a few extra devices. Create it as a container region
2141 * containing the system memory at low priority; any secure-only
2142 * devices go in at higher priority and take precedence.
2144 secure_sysmem
= g_new(MemoryRegion
, 1);
2145 memory_region_init(secure_sysmem
, OBJECT(machine
), "secure-memory",
2147 memory_region_add_subregion_overlap(secure_sysmem
, 0, sysmem
, -1);
2150 firmware_loaded
= virt_firmware_init(vms
, sysmem
,
2151 secure_sysmem
?: sysmem
);
2153 /* If we have an EL3 boot ROM then the assumption is that it will
2154 * implement PSCI itself, so disable QEMU's internal implementation
2155 * so it doesn't get in the way. Instead of starting secondary
2156 * CPUs in PSCI powerdown state we will start them all running and
2157 * let the boot ROM sort them out.
2158 * The usual case is that we do use QEMU's PSCI implementation;
2159 * if the guest has EL2 then we will use SMC as the conduit,
2160 * and otherwise we will use HVC (for backwards compatibility and
2161 * because if we're using KVM then we must use HVC).
2163 if (vms
->secure
&& firmware_loaded
) {
2164 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_DISABLED
;
2165 } else if (vms
->virt
) {
2166 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_SMC
;
2168 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_HVC
;
2172 * The maximum number of CPUs depends on the GIC version, or on how
2173 * many redistributors we can fit into the memory map (which in turn
2174 * depends on whether this is a GICv3 or v4).
2176 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
2177 virt_max_cpus
= GIC_NCPU
;
2179 virt_max_cpus
= virt_redist_capacity(vms
, VIRT_GIC_REDIST
);
2180 if (vms
->highmem_redists
) {
2181 virt_max_cpus
+= virt_redist_capacity(vms
, VIRT_HIGH_GIC_REDIST2
);
2185 if (max_cpus
> virt_max_cpus
) {
2186 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
2187 "supported by machine 'mach-virt' (%d)",
2188 max_cpus
, virt_max_cpus
);
2189 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
&& !vms
->highmem_redists
) {
2190 error_printf("Try 'highmem-redists=on' for more CPUs\n");
2196 if (vms
->secure
&& (kvm_enabled() || hvf_enabled())) {
2197 error_report("mach-virt: %s does not support providing "
2198 "Security extensions (TrustZone) to the guest CPU",
2199 current_accel_name());
2203 if (vms
->virt
&& (kvm_enabled() || hvf_enabled())) {
2204 error_report("mach-virt: %s does not support providing "
2205 "Virtualization extensions to the guest CPU",
2206 current_accel_name());
2210 if (vms
->mte
&& (kvm_enabled() || hvf_enabled())) {
2211 error_report("mach-virt: %s does not support providing "
2212 "MTE to the guest CPU",
2213 current_accel_name());
2219 assert(possible_cpus
->len
== max_cpus
);
2220 for (n
= 0; n
< possible_cpus
->len
; n
++) {
2224 if (n
>= smp_cpus
) {
2228 cpuobj
= object_new(possible_cpus
->cpus
[n
].type
);
2229 object_property_set_int(cpuobj
, "mp-affinity",
2230 possible_cpus
->cpus
[n
].arch_id
, NULL
);
2235 numa_cpu_pre_plug(&possible_cpus
->cpus
[cs
->cpu_index
], DEVICE(cpuobj
),
2238 aarch64
&= object_property_get_bool(cpuobj
, "aarch64", NULL
);
2241 object_property_set_bool(cpuobj
, "has_el3", false, NULL
);
2244 if (!vms
->virt
&& object_property_find(cpuobj
, "has_el2")) {
2245 object_property_set_bool(cpuobj
, "has_el2", false, NULL
);
2248 if (vmc
->kvm_no_adjvtime
&&
2249 object_property_find(cpuobj
, "kvm-no-adjvtime")) {
2250 object_property_set_bool(cpuobj
, "kvm-no-adjvtime", true, NULL
);
2253 if (vmc
->no_kvm_steal_time
&&
2254 object_property_find(cpuobj
, "kvm-steal-time")) {
2255 object_property_set_bool(cpuobj
, "kvm-steal-time", false, NULL
);
2258 if (vmc
->no_pmu
&& object_property_find(cpuobj
, "pmu")) {
2259 object_property_set_bool(cpuobj
, "pmu", false, NULL
);
2262 if (vmc
->no_tcg_lpa2
&& object_property_find(cpuobj
, "lpa2")) {
2263 object_property_set_bool(cpuobj
, "lpa2", false, NULL
);
2266 if (object_property_find(cpuobj
, "reset-cbar")) {
2267 object_property_set_int(cpuobj
, "reset-cbar",
2268 vms
->memmap
[VIRT_CPUPERIPHS
].base
,
2272 object_property_set_link(cpuobj
, "memory", OBJECT(sysmem
),
2275 object_property_set_link(cpuobj
, "secure-memory",
2276 OBJECT(secure_sysmem
), &error_abort
);
2280 /* Create the memory region only once, but link to all cpus. */
2283 * The property exists only if MemTag is supported.
2284 * If it is, we must allocate the ram to back that up.
2286 if (!object_property_find(cpuobj
, "tag-memory")) {
2287 error_report("MTE requested, but not supported "
2288 "by the guest CPU");
2292 tag_sysmem
= g_new(MemoryRegion
, 1);
2293 memory_region_init(tag_sysmem
, OBJECT(machine
),
2294 "tag-memory", UINT64_MAX
/ 32);
2297 secure_tag_sysmem
= g_new(MemoryRegion
, 1);
2298 memory_region_init(secure_tag_sysmem
, OBJECT(machine
),
2299 "secure-tag-memory", UINT64_MAX
/ 32);
2301 /* As with ram, secure-tag takes precedence over tag. */
2302 memory_region_add_subregion_overlap(secure_tag_sysmem
, 0,
2307 object_property_set_link(cpuobj
, "tag-memory", OBJECT(tag_sysmem
),
2310 object_property_set_link(cpuobj
, "secure-tag-memory",
2311 OBJECT(secure_tag_sysmem
),
2316 qdev_realize(DEVICE(cpuobj
), NULL
, &error_fatal
);
2317 object_unref(cpuobj
);
2320 /* Now we've created the CPUs we can see if they have the hypvirt timer */
2321 vms
->ns_el2_virt_timer_irq
= ns_el2_virt_timer_present() &&
2322 !vmc
->no_ns_el2_virt_timer_irq
;
2324 fdt_add_timer_nodes(vms
);
2325 fdt_add_cpu_nodes(vms
);
2327 memory_region_add_subregion(sysmem
, vms
->memmap
[VIRT_MEM
].base
,
2330 virt_flash_fdt(vms
, sysmem
, secure_sysmem
?: sysmem
);
2332 create_gic(vms
, sysmem
);
2334 virt_cpu_post_init(vms
, sysmem
);
2336 fdt_add_pmu_nodes(vms
);
2339 * The first UART always exists. If the security extensions are
2340 * enabled, the second UART also always exists. Otherwise, it only exists
2341 * if a backend is configured explicitly via '-serial <backend>'.
2342 * This avoids potentially breaking existing user setups that expect
2343 * only one NonSecure UART to be present (for instance, older EDK2
2346 * The nodes end up in the DTB in reverse order of creation, so we must
2347 * create UART0 last to ensure it appears as the first node in the DTB,
2348 * for compatibility with guest software that just iterates through the
2349 * DTB to find the first UART, as older versions of EDK2 do.
2350 * DTB readers that follow the spec, as Linux does, should honour the
2351 * aliases node information and /chosen/stdout-path regardless of
2352 * the order that nodes appear in the DTB.
2354 * For similar back-compatibility reasons, if UART1 is the secure UART
2355 * we create it second (and so it appears first in the DTB), because
2356 * that's what QEMU has always done.
2359 Chardev
*serial1
= serial_hd(1);
2362 vms
->second_ns_uart_present
= true;
2363 create_uart(vms
, VIRT_UART1
, sysmem
, serial1
, false);
2366 create_uart(vms
, VIRT_UART0
, sysmem
, serial_hd(0), false);
2368 create_uart(vms
, VIRT_UART1
, secure_sysmem
, serial_hd(1), true);
2372 create_secure_ram(vms
, secure_sysmem
, secure_tag_sysmem
);
2376 create_tag_ram(tag_sysmem
, vms
->memmap
[VIRT_MEM
].base
,
2377 machine
->ram_size
, "mach-virt.tag");
2380 vms
->highmem_ecam
&= (!firmware_loaded
|| aarch64
);
2386 if (has_ged
&& aarch64
&& firmware_loaded
&& virt_is_acpi_enabled(vms
)) {
2387 vms
->acpi_dev
= create_acpi_ged(vms
);
2389 create_gpio_devices(vms
, VIRT_GPIO
, sysmem
);
2392 if (vms
->secure
&& !vmc
->no_secure_gpio
) {
2393 create_gpio_devices(vms
, VIRT_SECURE_GPIO
, secure_sysmem
);
2396 /* connect powerdown request */
2397 vms
->powerdown_notifier
.notify
= virt_powerdown_req
;
2398 qemu_register_powerdown_notifier(&vms
->powerdown_notifier
);
2400 /* Create mmio transports, so the user can create virtio backends
2401 * (which will be automatically plugged in to the transports). If
2402 * no backend is created the transport will just sit harmlessly idle.
2404 create_virtio_devices(vms
);
2406 vms
->fw_cfg
= create_fw_cfg(vms
, &address_space_memory
);
2407 rom_set_fw(vms
->fw_cfg
);
2409 create_platform_bus(vms
);
2411 if (machine
->nvdimms_state
->is_enabled
) {
2412 const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio
= {
2413 .space_id
= AML_AS_SYSTEM_MEMORY
,
2414 .address
= vms
->memmap
[VIRT_NVDIMM_ACPI
].base
,
2415 .bit_width
= NVDIMM_ACPI_IO_LEN
<< 3
2418 nvdimm_init_acpi_state(machine
->nvdimms_state
, sysmem
,
2419 arm_virt_nvdimm_acpi_dsmio
,
2420 vms
->fw_cfg
, OBJECT(vms
));
2423 vms
->bootinfo
.ram_size
= machine
->ram_size
;
2424 vms
->bootinfo
.board_id
= -1;
2425 vms
->bootinfo
.loader_start
= vms
->memmap
[VIRT_MEM
].base
;
2426 vms
->bootinfo
.get_dtb
= machvirt_dtb
;
2427 vms
->bootinfo
.skip_dtb_autoload
= true;
2428 vms
->bootinfo
.firmware_loaded
= firmware_loaded
;
2429 vms
->bootinfo
.psci_conduit
= vms
->psci_conduit
;
2430 arm_load_kernel(ARM_CPU(first_cpu
), machine
, &vms
->bootinfo
);
2432 vms
->machine_done
.notify
= virt_machine_done
;
2433 qemu_add_machine_init_done_notifier(&vms
->machine_done
);
2436 static bool virt_get_secure(Object
*obj
, Error
**errp
)
2438 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2443 static void virt_set_secure(Object
*obj
, bool value
, Error
**errp
)
2445 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2447 vms
->secure
= value
;
2450 static bool virt_get_virt(Object
*obj
, Error
**errp
)
2452 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2457 static void virt_set_virt(Object
*obj
, bool value
, Error
**errp
)
2459 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2464 static bool virt_get_highmem(Object
*obj
, Error
**errp
)
2466 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2468 return vms
->highmem
;
2471 static void virt_set_highmem(Object
*obj
, bool value
, Error
**errp
)
2473 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2475 vms
->highmem
= value
;
2478 static bool virt_get_compact_highmem(Object
*obj
, Error
**errp
)
2480 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2482 return vms
->highmem_compact
;
2485 static void virt_set_compact_highmem(Object
*obj
, bool value
, Error
**errp
)
2487 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2489 vms
->highmem_compact
= value
;
2492 static bool virt_get_highmem_redists(Object
*obj
, Error
**errp
)
2494 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2496 return vms
->highmem_redists
;
2499 static void virt_set_highmem_redists(Object
*obj
, bool value
, Error
**errp
)
2501 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2503 vms
->highmem_redists
= value
;
2506 static bool virt_get_highmem_ecam(Object
*obj
, Error
**errp
)
2508 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2510 return vms
->highmem_ecam
;
2513 static void virt_set_highmem_ecam(Object
*obj
, bool value
, Error
**errp
)
2515 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2517 vms
->highmem_ecam
= value
;
2520 static bool virt_get_highmem_mmio(Object
*obj
, Error
**errp
)
2522 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2524 return vms
->highmem_mmio
;
2527 static void virt_set_highmem_mmio(Object
*obj
, bool value
, Error
**errp
)
2529 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2531 vms
->highmem_mmio
= value
;
2535 static bool virt_get_its(Object
*obj
, Error
**errp
)
2537 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2542 static void virt_set_its(Object
*obj
, bool value
, Error
**errp
)
2544 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2549 static bool virt_get_dtb_randomness(Object
*obj
, Error
**errp
)
2551 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2553 return vms
->dtb_randomness
;
2556 static void virt_set_dtb_randomness(Object
*obj
, bool value
, Error
**errp
)
2558 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2560 vms
->dtb_randomness
= value
;
2563 static char *virt_get_oem_id(Object
*obj
, Error
**errp
)
2565 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2567 return g_strdup(vms
->oem_id
);
2570 static void virt_set_oem_id(Object
*obj
, const char *value
, Error
**errp
)
2572 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2573 size_t len
= strlen(value
);
2577 "User specified oem-id value is bigger than 6 bytes in size");
2581 strncpy(vms
->oem_id
, value
, 6);
2584 static char *virt_get_oem_table_id(Object
*obj
, Error
**errp
)
2586 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2588 return g_strdup(vms
->oem_table_id
);
2591 static void virt_set_oem_table_id(Object
*obj
, const char *value
,
2594 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2595 size_t len
= strlen(value
);
2599 "User specified oem-table-id value is bigger than 8 bytes in size");
2602 strncpy(vms
->oem_table_id
, value
, 8);
2606 bool virt_is_acpi_enabled(VirtMachineState
*vms
)
2608 if (vms
->acpi
== ON_OFF_AUTO_OFF
) {
2614 static void virt_get_acpi(Object
*obj
, Visitor
*v
, const char *name
,
2615 void *opaque
, Error
**errp
)
2617 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2618 OnOffAuto acpi
= vms
->acpi
;
2620 visit_type_OnOffAuto(v
, name
, &acpi
, errp
);
2623 static void virt_set_acpi(Object
*obj
, Visitor
*v
, const char *name
,
2624 void *opaque
, Error
**errp
)
2626 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2628 visit_type_OnOffAuto(v
, name
, &vms
->acpi
, errp
);
2631 static bool virt_get_ras(Object
*obj
, Error
**errp
)
2633 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2638 static void virt_set_ras(Object
*obj
, bool value
, Error
**errp
)
2640 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2645 static bool virt_get_mte(Object
*obj
, Error
**errp
)
2647 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2652 static void virt_set_mte(Object
*obj
, bool value
, Error
**errp
)
2654 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2659 static char *virt_get_gic_version(Object
*obj
, Error
**errp
)
2661 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2664 switch (vms
->gic_version
) {
2665 case VIRT_GIC_VERSION_4
:
2668 case VIRT_GIC_VERSION_3
:
2675 return g_strdup(val
);
2678 static void virt_set_gic_version(Object
*obj
, const char *value
, Error
**errp
)
2680 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2682 if (!strcmp(value
, "4")) {
2683 vms
->gic_version
= VIRT_GIC_VERSION_4
;
2684 } else if (!strcmp(value
, "3")) {
2685 vms
->gic_version
= VIRT_GIC_VERSION_3
;
2686 } else if (!strcmp(value
, "2")) {
2687 vms
->gic_version
= VIRT_GIC_VERSION_2
;
2688 } else if (!strcmp(value
, "host")) {
2689 vms
->gic_version
= VIRT_GIC_VERSION_HOST
; /* Will probe later */
2690 } else if (!strcmp(value
, "max")) {
2691 vms
->gic_version
= VIRT_GIC_VERSION_MAX
; /* Will probe later */
2693 error_setg(errp
, "Invalid gic-version value");
2694 error_append_hint(errp
, "Valid values are 3, 2, host, max.\n");
2698 static char *virt_get_iommu(Object
*obj
, Error
**errp
)
2700 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2702 switch (vms
->iommu
) {
2703 case VIRT_IOMMU_NONE
:
2704 return g_strdup("none");
2705 case VIRT_IOMMU_SMMUV3
:
2706 return g_strdup("smmuv3");
2708 g_assert_not_reached();
2712 static void virt_set_iommu(Object
*obj
, const char *value
, Error
**errp
)
2714 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2716 if (!strcmp(value
, "smmuv3")) {
2717 vms
->iommu
= VIRT_IOMMU_SMMUV3
;
2718 } else if (!strcmp(value
, "none")) {
2719 vms
->iommu
= VIRT_IOMMU_NONE
;
2721 error_setg(errp
, "Invalid iommu value");
2722 error_append_hint(errp
, "Valid values are none, smmuv3.\n");
2726 static bool virt_get_default_bus_bypass_iommu(Object
*obj
, Error
**errp
)
2728 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2730 return vms
->default_bus_bypass_iommu
;
2733 static void virt_set_default_bus_bypass_iommu(Object
*obj
, bool value
,
2736 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2738 vms
->default_bus_bypass_iommu
= value
;
2741 static CpuInstanceProperties
2742 virt_cpu_index_to_props(MachineState
*ms
, unsigned cpu_index
)
2744 MachineClass
*mc
= MACHINE_GET_CLASS(ms
);
2745 const CPUArchIdList
*possible_cpus
= mc
->possible_cpu_arch_ids(ms
);
2747 assert(cpu_index
< possible_cpus
->len
);
2748 return possible_cpus
->cpus
[cpu_index
].props
;
2751 static int64_t virt_get_default_cpu_node_id(const MachineState
*ms
, int idx
)
2753 int64_t socket_id
= ms
->possible_cpus
->cpus
[idx
].props
.socket_id
;
2755 return socket_id
% ms
->numa_state
->num_nodes
;
2758 static const CPUArchIdList
*virt_possible_cpu_arch_ids(MachineState
*ms
)
2761 unsigned int max_cpus
= ms
->smp
.max_cpus
;
2762 VirtMachineState
*vms
= VIRT_MACHINE(ms
);
2763 MachineClass
*mc
= MACHINE_GET_CLASS(vms
);
2765 if (ms
->possible_cpus
) {
2766 assert(ms
->possible_cpus
->len
== max_cpus
);
2767 return ms
->possible_cpus
;
2770 ms
->possible_cpus
= g_malloc0(sizeof(CPUArchIdList
) +
2771 sizeof(CPUArchId
) * max_cpus
);
2772 ms
->possible_cpus
->len
= max_cpus
;
2773 for (n
= 0; n
< ms
->possible_cpus
->len
; n
++) {
2774 ms
->possible_cpus
->cpus
[n
].type
= ms
->cpu_type
;
2775 ms
->possible_cpus
->cpus
[n
].arch_id
=
2776 virt_cpu_mp_affinity(vms
, n
);
2778 assert(!mc
->smp_props
.dies_supported
);
2779 ms
->possible_cpus
->cpus
[n
].props
.has_socket_id
= true;
2780 ms
->possible_cpus
->cpus
[n
].props
.socket_id
=
2781 n
/ (ms
->smp
.clusters
* ms
->smp
.cores
* ms
->smp
.threads
);
2782 ms
->possible_cpus
->cpus
[n
].props
.has_cluster_id
= true;
2783 ms
->possible_cpus
->cpus
[n
].props
.cluster_id
=
2784 (n
/ (ms
->smp
.cores
* ms
->smp
.threads
)) % ms
->smp
.clusters
;
2785 ms
->possible_cpus
->cpus
[n
].props
.has_core_id
= true;
2786 ms
->possible_cpus
->cpus
[n
].props
.core_id
=
2787 (n
/ ms
->smp
.threads
) % ms
->smp
.cores
;
2788 ms
->possible_cpus
->cpus
[n
].props
.has_thread_id
= true;
2789 ms
->possible_cpus
->cpus
[n
].props
.thread_id
=
2790 n
% ms
->smp
.threads
;
2792 return ms
->possible_cpus
;
2795 static void virt_memory_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
2798 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2799 const MachineState
*ms
= MACHINE(hotplug_dev
);
2800 const bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
2802 if (!vms
->acpi_dev
) {
2804 "memory hotplug is not enabled: missing acpi-ged device");
2809 error_setg(errp
, "memory hotplug is not enabled: MTE is enabled");
2813 if (is_nvdimm
&& !ms
->nvdimms_state
->is_enabled
) {
2814 error_setg(errp
, "nvdimm is not enabled: add 'nvdimm=on' to '-M'");
2818 pc_dimm_pre_plug(PC_DIMM(dev
), MACHINE(hotplug_dev
), errp
);
2821 static void virt_memory_plug(HotplugHandler
*hotplug_dev
,
2822 DeviceState
*dev
, Error
**errp
)
2824 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2825 MachineState
*ms
= MACHINE(hotplug_dev
);
2826 bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
2828 pc_dimm_plug(PC_DIMM(dev
), MACHINE(vms
));
2831 nvdimm_plug(ms
->nvdimms_state
);
2834 hotplug_handler_plug(HOTPLUG_HANDLER(vms
->acpi_dev
),
2838 static void virt_machine_device_pre_plug_cb(HotplugHandler
*hotplug_dev
,
2839 DeviceState
*dev
, Error
**errp
)
2841 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2843 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2844 virt_memory_pre_plug(hotplug_dev
, dev
, errp
);
2845 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MD_PCI
)) {
2846 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev
), MACHINE(hotplug_dev
), errp
);
2847 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_IOMMU_PCI
)) {
2848 hwaddr db_start
= 0, db_end
= 0;
2849 QList
*reserved_regions
;
2850 char *resv_prop_str
;
2852 if (vms
->iommu
!= VIRT_IOMMU_NONE
) {
2853 error_setg(errp
, "virt machine does not support multiple IOMMUs");
2857 switch (vms
->msi_controller
) {
2858 case VIRT_MSI_CTRL_NONE
:
2860 case VIRT_MSI_CTRL_ITS
:
2861 /* GITS_TRANSLATER page */
2862 db_start
= base_memmap
[VIRT_GIC_ITS
].base
+ 0x10000;
2863 db_end
= base_memmap
[VIRT_GIC_ITS
].base
+
2864 base_memmap
[VIRT_GIC_ITS
].size
- 1;
2866 case VIRT_MSI_CTRL_GICV2M
:
2867 /* MSI_SETSPI_NS page */
2868 db_start
= base_memmap
[VIRT_GIC_V2M
].base
;
2869 db_end
= db_start
+ base_memmap
[VIRT_GIC_V2M
].size
- 1;
2872 resv_prop_str
= g_strdup_printf("0x%"PRIx64
":0x%"PRIx64
":%u",
2874 VIRTIO_IOMMU_RESV_MEM_T_MSI
);
2876 reserved_regions
= qlist_new();
2877 qlist_append_str(reserved_regions
, resv_prop_str
);
2878 qdev_prop_set_array(dev
, "reserved-regions", reserved_regions
);
2879 g_free(resv_prop_str
);
2883 static void virt_machine_device_plug_cb(HotplugHandler
*hotplug_dev
,
2884 DeviceState
*dev
, Error
**errp
)
2886 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2888 if (vms
->platform_bus_dev
) {
2889 MachineClass
*mc
= MACHINE_GET_CLASS(vms
);
2891 if (device_is_dynamic_sysbus(mc
, dev
)) {
2892 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms
->platform_bus_dev
),
2893 SYS_BUS_DEVICE(dev
));
2897 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2898 virt_memory_plug(hotplug_dev
, dev
, errp
);
2899 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MD_PCI
)) {
2900 virtio_md_pci_plug(VIRTIO_MD_PCI(dev
), MACHINE(hotplug_dev
), errp
);
2903 if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_IOMMU_PCI
)) {
2904 PCIDevice
*pdev
= PCI_DEVICE(dev
);
2906 vms
->iommu
= VIRT_IOMMU_VIRTIO
;
2907 vms
->virtio_iommu_bdf
= pci_get_bdf(pdev
);
2908 create_virtio_iommu_dt_bindings(vms
);
2912 static void virt_dimm_unplug_request(HotplugHandler
*hotplug_dev
,
2913 DeviceState
*dev
, Error
**errp
)
2915 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2917 if (!vms
->acpi_dev
) {
2919 "memory hotplug is not enabled: missing acpi-ged device");
2923 if (object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
)) {
2924 error_setg(errp
, "nvdimm device hot unplug is not supported yet.");
2928 hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms
->acpi_dev
), dev
,
2932 static void virt_dimm_unplug(HotplugHandler
*hotplug_dev
,
2933 DeviceState
*dev
, Error
**errp
)
2935 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2936 Error
*local_err
= NULL
;
2938 hotplug_handler_unplug(HOTPLUG_HANDLER(vms
->acpi_dev
), dev
, &local_err
);
2943 pc_dimm_unplug(PC_DIMM(dev
), MACHINE(vms
));
2944 qdev_unrealize(dev
);
2947 error_propagate(errp
, local_err
);
2950 static void virt_machine_device_unplug_request_cb(HotplugHandler
*hotplug_dev
,
2951 DeviceState
*dev
, Error
**errp
)
2953 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2954 virt_dimm_unplug_request(hotplug_dev
, dev
, errp
);
2955 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MD_PCI
)) {
2956 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev
), MACHINE(hotplug_dev
),
2959 error_setg(errp
, "device unplug request for unsupported device"
2960 " type: %s", object_get_typename(OBJECT(dev
)));
2964 static void virt_machine_device_unplug_cb(HotplugHandler
*hotplug_dev
,
2965 DeviceState
*dev
, Error
**errp
)
2967 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2968 virt_dimm_unplug(hotplug_dev
, dev
, errp
);
2969 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MD_PCI
)) {
2970 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev
), MACHINE(hotplug_dev
), errp
);
2972 error_setg(errp
, "virt: device unplug for unsupported device"
2973 " type: %s", object_get_typename(OBJECT(dev
)));
2977 static HotplugHandler
*virt_machine_get_hotplug_handler(MachineState
*machine
,
2980 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2982 if (device_is_dynamic_sysbus(mc
, dev
) ||
2983 object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
) ||
2984 object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MD_PCI
) ||
2985 object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_IOMMU_PCI
)) {
2986 return HOTPLUG_HANDLER(machine
);
2992 * for arm64 kvm_type [7-0] encodes the requested number of bits
2993 * in the IPA address space
2995 static int virt_kvm_type(MachineState
*ms
, const char *type_str
)
2997 VirtMachineState
*vms
= VIRT_MACHINE(ms
);
2998 int max_vm_pa_size
, requested_pa_size
;
3001 max_vm_pa_size
= kvm_arm_get_max_vm_ipa_size(ms
, &fixed_ipa
);
3003 /* we freeze the memory map to compute the highest gpa */
3004 virt_set_memmap(vms
, max_vm_pa_size
);
3006 requested_pa_size
= 64 - clz64(vms
->highest_gpa
);
3009 * KVM requires the IPA size to be at least 32 bits.
3011 if (requested_pa_size
< 32) {
3012 requested_pa_size
= 32;
3015 if (requested_pa_size
> max_vm_pa_size
) {
3016 error_report("-m and ,maxmem option values "
3017 "require an IPA range (%d bits) larger than "
3018 "the one supported by the host (%d bits)",
3019 requested_pa_size
, max_vm_pa_size
);
3023 * We return the requested PA log size, unless KVM only supports
3024 * the implicit legacy 40b IPA setting, in which case the kvm_type
3027 return fixed_ipa
? 0 : requested_pa_size
;
3030 static void virt_machine_class_init(ObjectClass
*oc
, void *data
)
3032 MachineClass
*mc
= MACHINE_CLASS(oc
);
3033 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(oc
);
3034 static const char * const valid_cpu_types
[] = {
3036 ARM_CPU_TYPE_NAME("cortex-a7"),
3037 ARM_CPU_TYPE_NAME("cortex-a15"),
3038 #ifdef TARGET_AARCH64
3039 ARM_CPU_TYPE_NAME("cortex-a35"),
3040 ARM_CPU_TYPE_NAME("cortex-a55"),
3041 ARM_CPU_TYPE_NAME("cortex-a72"),
3042 ARM_CPU_TYPE_NAME("cortex-a76"),
3043 ARM_CPU_TYPE_NAME("cortex-a710"),
3044 ARM_CPU_TYPE_NAME("a64fx"),
3045 ARM_CPU_TYPE_NAME("neoverse-n1"),
3046 ARM_CPU_TYPE_NAME("neoverse-v1"),
3047 ARM_CPU_TYPE_NAME("neoverse-n2"),
3048 #endif /* TARGET_AARCH64 */
3049 #endif /* CONFIG_TCG */
3050 #ifdef TARGET_AARCH64
3051 ARM_CPU_TYPE_NAME("cortex-a53"),
3052 ARM_CPU_TYPE_NAME("cortex-a57"),
3053 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
3054 ARM_CPU_TYPE_NAME("host"),
3055 #endif /* CONFIG_KVM || CONFIG_HVF */
3056 #endif /* TARGET_AARCH64 */
3057 ARM_CPU_TYPE_NAME("max"),
3061 mc
->init
= machvirt_init
;
3062 /* Start with max_cpus set to 512, which is the maximum supported by KVM.
3063 * The value may be reduced later when we have more information about the
3064 * configuration of the particular instance.
3067 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_CALXEDA_XGMAC
);
3068 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_AMD_XGBE
);
3069 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_RAMFB_DEVICE
);
3070 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_PLATFORM
);
3072 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_TPM_TIS_SYSBUS
);
3074 mc
->block_default_type
= IF_VIRTIO
;
3076 mc
->pci_allow_0_address
= true;
3077 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */
3078 mc
->minimum_page_bits
= 12;
3079 mc
->possible_cpu_arch_ids
= virt_possible_cpu_arch_ids
;
3080 mc
->cpu_index_to_instance_props
= virt_cpu_index_to_props
;
3082 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-a15");
3084 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("max");
3086 mc
->valid_cpu_types
= valid_cpu_types
;
3087 mc
->get_default_cpu_node_id
= virt_get_default_cpu_node_id
;
3088 mc
->kvm_type
= virt_kvm_type
;
3089 assert(!mc
->get_hotplug_handler
);
3090 mc
->get_hotplug_handler
= virt_machine_get_hotplug_handler
;
3091 hc
->pre_plug
= virt_machine_device_pre_plug_cb
;
3092 hc
->plug
= virt_machine_device_plug_cb
;
3093 hc
->unplug_request
= virt_machine_device_unplug_request_cb
;
3094 hc
->unplug
= virt_machine_device_unplug_cb
;
3095 mc
->nvdimm_supported
= true;
3096 mc
->smp_props
.clusters_supported
= true;
3097 mc
->auto_enable_numa_with_memhp
= true;
3098 mc
->auto_enable_numa_with_memdev
= true;
3099 /* platform instead of architectural choice */
3100 mc
->cpu_cluster_has_numa_boundary
= true;
3101 mc
->default_ram_id
= "mach-virt.ram";
3102 mc
->default_nic
= "virtio-net-pci";
3104 object_class_property_add(oc
, "acpi", "OnOffAuto",
3105 virt_get_acpi
, virt_set_acpi
,
3107 object_class_property_set_description(oc
, "acpi",
3109 object_class_property_add_bool(oc
, "secure", virt_get_secure
,
3111 object_class_property_set_description(oc
, "secure",
3112 "Set on/off to enable/disable the ARM "
3113 "Security Extensions (TrustZone)");
3115 object_class_property_add_bool(oc
, "virtualization", virt_get_virt
,
3117 object_class_property_set_description(oc
, "virtualization",
3118 "Set on/off to enable/disable emulating a "
3119 "guest CPU which implements the ARM "
3120 "Virtualization Extensions");
3122 object_class_property_add_bool(oc
, "highmem", virt_get_highmem
,
3124 object_class_property_set_description(oc
, "highmem",
3125 "Set on/off to enable/disable using "
3126 "physical address space above 32 bits");
3128 object_class_property_add_bool(oc
, "compact-highmem",
3129 virt_get_compact_highmem
,
3130 virt_set_compact_highmem
);
3131 object_class_property_set_description(oc
, "compact-highmem",
3132 "Set on/off to enable/disable compact "
3133 "layout for high memory regions");
3135 object_class_property_add_bool(oc
, "highmem-redists",
3136 virt_get_highmem_redists
,
3137 virt_set_highmem_redists
);
3138 object_class_property_set_description(oc
, "highmem-redists",
3139 "Set on/off to enable/disable high "
3140 "memory region for GICv3 or GICv4 "
3143 object_class_property_add_bool(oc
, "highmem-ecam",
3144 virt_get_highmem_ecam
,
3145 virt_set_highmem_ecam
);
3146 object_class_property_set_description(oc
, "highmem-ecam",
3147 "Set on/off to enable/disable high "
3148 "memory region for PCI ECAM");
3150 object_class_property_add_bool(oc
, "highmem-mmio",
3151 virt_get_highmem_mmio
,
3152 virt_set_highmem_mmio
);
3153 object_class_property_set_description(oc
, "highmem-mmio",
3154 "Set on/off to enable/disable high "
3155 "memory region for PCI MMIO");
3157 object_class_property_add_str(oc
, "gic-version", virt_get_gic_version
,
3158 virt_set_gic_version
);
3159 object_class_property_set_description(oc
, "gic-version",
3161 "Valid values are 2, 3, 4, host and max");
3163 object_class_property_add_str(oc
, "iommu", virt_get_iommu
, virt_set_iommu
);
3164 object_class_property_set_description(oc
, "iommu",
3165 "Set the IOMMU type. "
3166 "Valid values are none and smmuv3");
3168 object_class_property_add_bool(oc
, "default-bus-bypass-iommu",
3169 virt_get_default_bus_bypass_iommu
,
3170 virt_set_default_bus_bypass_iommu
);
3171 object_class_property_set_description(oc
, "default-bus-bypass-iommu",
3172 "Set on/off to enable/disable "
3173 "bypass_iommu for default root bus");
3175 object_class_property_add_bool(oc
, "ras", virt_get_ras
,
3177 object_class_property_set_description(oc
, "ras",
3178 "Set on/off to enable/disable reporting host memory errors "
3179 "to a KVM guest using ACPI and guest external abort exceptions");
3181 object_class_property_add_bool(oc
, "mte", virt_get_mte
, virt_set_mte
);
3182 object_class_property_set_description(oc
, "mte",
3183 "Set on/off to enable/disable emulating a "
3184 "guest CPU which implements the ARM "
3185 "Memory Tagging Extension");
3187 object_class_property_add_bool(oc
, "its", virt_get_its
,
3189 object_class_property_set_description(oc
, "its",
3190 "Set on/off to enable/disable "
3191 "ITS instantiation");
3193 object_class_property_add_bool(oc
, "dtb-randomness",
3194 virt_get_dtb_randomness
,
3195 virt_set_dtb_randomness
);
3196 object_class_property_set_description(oc
, "dtb-randomness",
3197 "Set off to disable passing random or "
3198 "non-deterministic dtb nodes to guest");
3200 object_class_property_add_bool(oc
, "dtb-kaslr-seed",
3201 virt_get_dtb_randomness
,
3202 virt_set_dtb_randomness
);
3203 object_class_property_set_description(oc
, "dtb-kaslr-seed",
3204 "Deprecated synonym of dtb-randomness");
3206 object_class_property_add_str(oc
, "x-oem-id",
3209 object_class_property_set_description(oc
, "x-oem-id",
3210 "Override the default value of field OEMID "
3211 "in ACPI table header."
3212 "The string may be up to 6 bytes in size");
3215 object_class_property_add_str(oc
, "x-oem-table-id",
3216 virt_get_oem_table_id
,
3217 virt_set_oem_table_id
);
3218 object_class_property_set_description(oc
, "x-oem-table-id",
3219 "Override the default value of field OEM Table ID "
3220 "in ACPI table header."
3221 "The string may be up to 8 bytes in size");
3225 static void virt_instance_init(Object
*obj
)
3227 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
3228 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
3230 /* EL3 is disabled by default on virt: this makes us consistent
3231 * between KVM and TCG for this board, and it also allows us to
3232 * boot UEFI blobs which assume no TrustZone support.
3234 vms
->secure
= false;
3236 /* EL2 is also disabled by default, for similar reasons */
3239 /* High memory is enabled by default */
3240 vms
->highmem
= true;
3241 vms
->highmem_compact
= !vmc
->no_highmem_compact
;
3242 vms
->gic_version
= VIRT_GIC_VERSION_NOSEL
;
3244 vms
->highmem_ecam
= !vmc
->no_highmem_ecam
;
3245 vms
->highmem_mmio
= true;
3246 vms
->highmem_redists
= true;
3251 /* Default allows ITS instantiation */
3254 if (vmc
->no_tcg_its
) {
3255 vms
->tcg_its
= false;
3257 vms
->tcg_its
= true;
3261 /* Default disallows iommu instantiation */
3262 vms
->iommu
= VIRT_IOMMU_NONE
;
3264 /* The default root bus is attached to iommu by default */
3265 vms
->default_bus_bypass_iommu
= false;
3267 /* Default disallows RAS instantiation */
3270 /* MTE is disabled by default. */
3273 /* Supply kaslr-seed and rng-seed by default */
3274 vms
->dtb_randomness
= true;
3276 vms
->irqmap
= a15irqmap
;
3278 virt_flash_create(vms
);
3280 vms
->oem_id
= g_strndup(ACPI_BUILD_APPNAME6
, 6);
3281 vms
->oem_table_id
= g_strndup(ACPI_BUILD_APPNAME8
, 8);
3284 static const TypeInfo virt_machine_info
= {
3285 .name
= TYPE_VIRT_MACHINE
,
3286 .parent
= TYPE_MACHINE
,
3288 .instance_size
= sizeof(VirtMachineState
),
3289 .class_size
= sizeof(VirtMachineClass
),
3290 .class_init
= virt_machine_class_init
,
3291 .instance_init
= virt_instance_init
,
3292 .interfaces
= (InterfaceInfo
[]) {
3293 { TYPE_HOTPLUG_HANDLER
},
3298 static void machvirt_machine_init(void)
3300 type_register_static(&virt_machine_info
);
3302 type_init(machvirt_machine_init
);
3304 static void virt_machine_9_1_options(MachineClass
*mc
)
3307 DEFINE_VIRT_MACHINE_AS_LATEST(9, 1)
3309 static void virt_machine_9_0_options(MachineClass
*mc
)
3311 virt_machine_9_1_options(mc
);
3312 mc
->smbios_memory_device_size
= 16 * GiB
;
3313 compat_props_add(mc
->compat_props
, hw_compat_9_0
, hw_compat_9_0_len
);
3315 DEFINE_VIRT_MACHINE(9, 0)
3317 static void virt_machine_8_2_options(MachineClass
*mc
)
3319 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3321 virt_machine_9_0_options(mc
);
3322 compat_props_add(mc
->compat_props
, hw_compat_8_2
, hw_compat_8_2_len
);
3324 * Don't expose NS_EL2_VIRT timer IRQ in DTB on ACPI on 8.2 and
3325 * earlier machines. (Exposing it tickles a bug in older EDK2
3326 * guest BIOS binaries.)
3328 vmc
->no_ns_el2_virt_timer_irq
= true;
3330 DEFINE_VIRT_MACHINE(8, 2)
3332 static void virt_machine_8_1_options(MachineClass
*mc
)
3334 virt_machine_8_2_options(mc
);
3335 compat_props_add(mc
->compat_props
, hw_compat_8_1
, hw_compat_8_1_len
);
3337 DEFINE_VIRT_MACHINE(8, 1)
3339 static void virt_machine_8_0_options(MachineClass
*mc
)
3341 virt_machine_8_1_options(mc
);
3342 compat_props_add(mc
->compat_props
, hw_compat_8_0
, hw_compat_8_0_len
);
3344 DEFINE_VIRT_MACHINE(8, 0)
3346 static void virt_machine_7_2_options(MachineClass
*mc
)
3348 virt_machine_8_0_options(mc
);
3349 compat_props_add(mc
->compat_props
, hw_compat_7_2
, hw_compat_7_2_len
);
3351 DEFINE_VIRT_MACHINE(7, 2)
3353 static void virt_machine_7_1_options(MachineClass
*mc
)
3355 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3357 virt_machine_7_2_options(mc
);
3358 compat_props_add(mc
->compat_props
, hw_compat_7_1
, hw_compat_7_1_len
);
3359 /* Compact layout for high memory regions was introduced with 7.2 */
3360 vmc
->no_highmem_compact
= true;
3362 DEFINE_VIRT_MACHINE(7, 1)
3364 static void virt_machine_7_0_options(MachineClass
*mc
)
3366 virt_machine_7_1_options(mc
);
3367 compat_props_add(mc
->compat_props
, hw_compat_7_0
, hw_compat_7_0_len
);
3369 DEFINE_VIRT_MACHINE(7, 0)
3371 static void virt_machine_6_2_options(MachineClass
*mc
)
3373 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3375 virt_machine_7_0_options(mc
);
3376 compat_props_add(mc
->compat_props
, hw_compat_6_2
, hw_compat_6_2_len
);
3377 vmc
->no_tcg_lpa2
= true;
3379 DEFINE_VIRT_MACHINE(6, 2)
3381 static void virt_machine_6_1_options(MachineClass
*mc
)
3383 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3385 virt_machine_6_2_options(mc
);
3386 compat_props_add(mc
->compat_props
, hw_compat_6_1
, hw_compat_6_1_len
);
3387 mc
->smp_props
.prefer_sockets
= true;
3388 vmc
->no_cpu_topology
= true;
3390 /* qemu ITS was introduced with 6.2 */
3391 vmc
->no_tcg_its
= true;
3393 DEFINE_VIRT_MACHINE(6, 1)
3395 static void virt_machine_6_0_options(MachineClass
*mc
)
3397 virt_machine_6_1_options(mc
);
3398 compat_props_add(mc
->compat_props
, hw_compat_6_0
, hw_compat_6_0_len
);
3400 DEFINE_VIRT_MACHINE(6, 0)
3402 static void virt_machine_5_2_options(MachineClass
*mc
)
3404 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3406 virt_machine_6_0_options(mc
);
3407 compat_props_add(mc
->compat_props
, hw_compat_5_2
, hw_compat_5_2_len
);
3408 vmc
->no_secure_gpio
= true;
3410 DEFINE_VIRT_MACHINE(5, 2)
3412 static void virt_machine_5_1_options(MachineClass
*mc
)
3414 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3416 virt_machine_5_2_options(mc
);
3417 compat_props_add(mc
->compat_props
, hw_compat_5_1
, hw_compat_5_1_len
);
3418 vmc
->no_kvm_steal_time
= true;
3420 DEFINE_VIRT_MACHINE(5, 1)
3422 static void virt_machine_5_0_options(MachineClass
*mc
)
3424 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3426 virt_machine_5_1_options(mc
);
3427 compat_props_add(mc
->compat_props
, hw_compat_5_0
, hw_compat_5_0_len
);
3428 mc
->numa_mem_supported
= true;
3429 vmc
->acpi_expose_flash
= true;
3430 mc
->auto_enable_numa_with_memdev
= false;
3432 DEFINE_VIRT_MACHINE(5, 0)
3434 static void virt_machine_4_2_options(MachineClass
*mc
)
3436 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3438 virt_machine_5_0_options(mc
);
3439 compat_props_add(mc
->compat_props
, hw_compat_4_2
, hw_compat_4_2_len
);
3440 vmc
->kvm_no_adjvtime
= true;
3442 DEFINE_VIRT_MACHINE(4, 2)
3444 static void virt_machine_4_1_options(MachineClass
*mc
)
3446 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3448 virt_machine_4_2_options(mc
);
3449 compat_props_add(mc
->compat_props
, hw_compat_4_1
, hw_compat_4_1_len
);
3451 mc
->auto_enable_numa_with_memhp
= false;
3453 DEFINE_VIRT_MACHINE(4, 1)
3455 static void virt_machine_4_0_options(MachineClass
*mc
)
3457 virt_machine_4_1_options(mc
);
3458 compat_props_add(mc
->compat_props
, hw_compat_4_0
, hw_compat_4_0_len
);
3460 DEFINE_VIRT_MACHINE(4, 0)
3462 static void virt_machine_3_1_options(MachineClass
*mc
)
3464 virt_machine_4_0_options(mc
);
3465 compat_props_add(mc
->compat_props
, hw_compat_3_1
, hw_compat_3_1_len
);
3467 DEFINE_VIRT_MACHINE(3, 1)
3469 static void virt_machine_3_0_options(MachineClass
*mc
)
3471 virt_machine_3_1_options(mc
);
3472 compat_props_add(mc
->compat_props
, hw_compat_3_0
, hw_compat_3_0_len
);
3474 DEFINE_VIRT_MACHINE(3, 0)
3476 static void virt_machine_2_12_options(MachineClass
*mc
)
3478 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3480 virt_machine_3_0_options(mc
);
3481 compat_props_add(mc
->compat_props
, hw_compat_2_12
, hw_compat_2_12_len
);
3482 vmc
->no_highmem_ecam
= true;
3485 DEFINE_VIRT_MACHINE(2, 12)
3487 static void virt_machine_2_11_options(MachineClass
*mc
)
3489 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3491 virt_machine_2_12_options(mc
);
3492 compat_props_add(mc
->compat_props
, hw_compat_2_11
, hw_compat_2_11_len
);
3493 vmc
->smbios_old_sys_ver
= true;
3495 DEFINE_VIRT_MACHINE(2, 11)
3497 static void virt_machine_2_10_options(MachineClass
*mc
)
3499 virt_machine_2_11_options(mc
);
3500 compat_props_add(mc
->compat_props
, hw_compat_2_10
, hw_compat_2_10_len
);
3501 /* before 2.11 we never faulted accesses to bad addresses */
3502 mc
->ignore_memory_transaction_failures
= true;
3504 DEFINE_VIRT_MACHINE(2, 10)
3506 static void virt_machine_2_9_options(MachineClass
*mc
)
3508 virt_machine_2_10_options(mc
);
3509 compat_props_add(mc
->compat_props
, hw_compat_2_9
, hw_compat_2_9_len
);
3511 DEFINE_VIRT_MACHINE(2, 9)
3513 static void virt_machine_2_8_options(MachineClass
*mc
)
3515 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3517 virt_machine_2_9_options(mc
);
3518 compat_props_add(mc
->compat_props
, hw_compat_2_8
, hw_compat_2_8_len
);
3519 /* For 2.8 and earlier we falsely claimed in the DT that
3520 * our timers were edge-triggered, not level-triggered.
3522 vmc
->claim_edge_triggered_timers
= true;
3524 DEFINE_VIRT_MACHINE(2, 8)
3526 static void virt_machine_2_7_options(MachineClass
*mc
)
3528 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3530 virt_machine_2_8_options(mc
);
3531 compat_props_add(mc
->compat_props
, hw_compat_2_7
, hw_compat_2_7_len
);
3532 /* ITS was introduced with 2.8 */
3534 /* Stick with 1K pages for migration compatibility */
3535 mc
->minimum_page_bits
= 0;
3537 DEFINE_VIRT_MACHINE(2, 7)
3539 static void virt_machine_2_6_options(MachineClass
*mc
)
3541 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3543 virt_machine_2_7_options(mc
);
3544 compat_props_add(mc
->compat_props
, hw_compat_2_6
, hw_compat_2_6_len
);
3545 vmc
->disallow_affinity_adjustment
= true;
3546 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */
3549 DEFINE_VIRT_MACHINE(2, 6)