hw/misc/aspeed_sdmc.c

   1 /*
   2  * ASPEED SDRAM Memory Controller
   3  *
   4  * Copyright (C) 2016 IBM Corp.
   5  *
   6  * This code is licensed under the GPL version 2 or later.  See
   7  * the COPYING file in the top-level directory.
   8  */
   9
  10 #include "qemu/osdep.h"
  11 #include "qemu/log.h"
  12 #include "qemu/error-report.h"
  13 #include "hw/misc/aspeed_sdmc.h"
  14 #include "hw/misc/aspeed_scu.h"
  15 #include "hw/qdev-properties.h"
  16 #include "qapi/error.h"
  17 #include "trace.h"
  18
  19 /* Protection Key Register */
  20 #define R_PROT            (0x00 / 4)
  21 #define   PROT_KEY_UNLOCK     0xFC600309
  22
  23 /* Configuration Register */
  24 #define R_CONF            (0x04 / 4)
  25
  26 /* Control/Status Register #1 (ast2500) */
  27 #define R_STATUS1         (0x60 / 4)
  28 #define   PHY_BUSY_STATE      BIT(0)
  29
  30 /*
  31  * Configuration register Ox4 (for Aspeed AST2400 SOC)
  32  *
  33  * These are for the record and future use. ASPEED_SDMC_DRAM_SIZE is
  34  * what we care about right now as it is checked by U-Boot to
  35  * determine the RAM size.
  36  */
  37
  38 #define ASPEED_SDMC_RESERVED            0xFFFFF800 /* 31:11 reserved */
  39 #define ASPEED_SDMC_AST2300_COMPAT      (1 << 10)
  40 #define ASPEED_SDMC_SCRAMBLE_PATTERN    (1 << 9)
  41 #define ASPEED_SDMC_DATA_SCRAMBLE       (1 << 8)
  42 #define ASPEED_SDMC_ECC_ENABLE          (1 << 7)
  43 #define ASPEED_SDMC_VGA_COMPAT          (1 << 6) /* readonly */
  44 #define ASPEED_SDMC_DRAM_BANK           (1 << 5)
  45 #define ASPEED_SDMC_DRAM_BURST          (1 << 4)
  46 #define ASPEED_SDMC_VGA_APERTURE(x)     ((x & 0x3) << 2) /* readonly */
  47 #define     ASPEED_SDMC_VGA_8MB             0x0
  48 #define     ASPEED_SDMC_VGA_16MB            0x1
  49 #define     ASPEED_SDMC_VGA_32MB            0x2
  50 #define     ASPEED_SDMC_VGA_64MB            0x3
  51 #define ASPEED_SDMC_DRAM_SIZE(x)        (x & 0x3)
  52 #define     ASPEED_SDMC_DRAM_64MB           0x0
  53 #define     ASPEED_SDMC_DRAM_128MB          0x1
  54 #define     ASPEED_SDMC_DRAM_256MB          0x2
  55 #define     ASPEED_SDMC_DRAM_512MB          0x3
  56
  57 #define ASPEED_SDMC_READONLY_MASK                       \
  58     (ASPEED_SDMC_RESERVED | ASPEED_SDMC_VGA_COMPAT |    \
  59      ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB))
  60 /*
  61  * Configuration register Ox4 (for Aspeed AST2500 SOC and higher)
  62  *
  63  * Incompatibilities are annotated in the list. ASPEED_SDMC_HW_VERSION
  64  * should be set to 1 for the AST2500 SOC.
  65  */
  66 #define ASPEED_SDMC_HW_VERSION(x)       ((x & 0xf) << 28) /* readonly */
  67 #define ASPEED_SDMC_SW_VERSION          ((x & 0xff) << 20)
  68 #define ASPEED_SDMC_CACHE_INITIAL_DONE  (1 << 19)  /* readonly */
  69 #define ASPEED_SDMC_AST2500_RESERVED    0x7C000 /* 18:14 reserved */
  70 #define ASPEED_SDMC_CACHE_DDR4_CONF     (1 << 13)
  71 #define ASPEED_SDMC_CACHE_INITIAL       (1 << 12)
  72 #define ASPEED_SDMC_CACHE_RANGE_CTRL    (1 << 11)
  73 #define ASPEED_SDMC_CACHE_ENABLE        (1 << 10) /* differs from AST2400 */
  74 #define ASPEED_SDMC_DRAM_TYPE           (1 << 4)  /* differs from AST2400 */
  75
  76 /* DRAM size definitions differs */
  77 #define     ASPEED_SDMC_AST2500_128MB       0x0
  78 #define     ASPEED_SDMC_AST2500_256MB       0x1
  79 #define     ASPEED_SDMC_AST2500_512MB       0x2
  80 #define     ASPEED_SDMC_AST2500_1024MB      0x3
  81
  82 #define ASPEED_SDMC_AST2500_READONLY_MASK                               \
  83     (ASPEED_SDMC_HW_VERSION(0xf) | ASPEED_SDMC_CACHE_INITIAL_DONE |     \
  84      ASPEED_SDMC_AST2500_RESERVED | ASPEED_SDMC_VGA_COMPAT |            \
  85      ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB))
  86
  87 static uint64_t aspeed_sdmc_read(void *opaque, hwaddr addr, unsigned size)
  88 {
  89     AspeedSDMCState *s = ASPEED_SDMC(opaque);
  90
  91     addr >>= 2;
  92
  93     if (addr >= ARRAY_SIZE(s->regs)) {
  94         qemu_log_mask(LOG_GUEST_ERROR,
  95                       "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
  96                       __func__, addr);
  97         return 0;
  98     }
  99
 100     return s->regs[addr];
 101 }
 102
 103 static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data,
 104                              unsigned int size)
 105 {
 106     AspeedSDMCState *s = ASPEED_SDMC(opaque);
 107
 108     addr >>= 2;
 109
 110     if (addr >= ARRAY_SIZE(s->regs)) {
 111         qemu_log_mask(LOG_GUEST_ERROR,
 112                       "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
 113                       __func__, addr);
 114         return;
 115     }
 116
 117     if (addr == R_PROT) {
 118         s->regs[addr] = (data == PROT_KEY_UNLOCK) ? 1 : 0;
 119         return;
 120     }
 121
 122     if (!s->regs[R_PROT]) {
 123         qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__);
 124         return;
 125     }
 126
 127     if (addr == R_CONF) {
 128         /* Make sure readonly bits are kept */
 129         switch (s->silicon_rev) {
 130         case AST2400_A0_SILICON_REV:
 131         case AST2400_A1_SILICON_REV:
 132             data &= ~ASPEED_SDMC_READONLY_MASK;
 133             data |= s->fixed_conf;
 134             break;
 135         case AST2500_A0_SILICON_REV:
 136         case AST2500_A1_SILICON_REV:
 137             data &= ~ASPEED_SDMC_AST2500_READONLY_MASK;
 138             data |= s->fixed_conf;
 139             break;
 140         default:
 141             g_assert_not_reached();
 142         }
 143     }
 144     if (s->silicon_rev == AST2500_A0_SILICON_REV ||
 145             s->silicon_rev == AST2500_A1_SILICON_REV) {
 146         switch (addr) {
 147         case R_STATUS1:
 148             /* Will never return 'busy' */
 149             data &= ~PHY_BUSY_STATE;
 150             break;
 151         default:
 152             break;
 153         }
 154     }
 155
 156     s->regs[addr] = data;
 157 }
 158
 159 static const MemoryRegionOps aspeed_sdmc_ops = {
 160     .read = aspeed_sdmc_read,
 161     .write = aspeed_sdmc_write,
 162     .endianness = DEVICE_LITTLE_ENDIAN,
 163     .valid.min_access_size = 4,
 164     .valid.max_access_size = 4,
 165 };
 166
 167 static int ast2400_rambits(AspeedSDMCState *s)
 168 {
 169     switch (s->ram_size >> 20) {
 170     case 64:
 171         return ASPEED_SDMC_DRAM_64MB;
 172     case 128:
 173         return ASPEED_SDMC_DRAM_128MB;
 174     case 256:
 175         return ASPEED_SDMC_DRAM_256MB;
 176     case 512:
 177         return ASPEED_SDMC_DRAM_512MB;
 178     default:
 179         break;
 180     }
 181
 182     /* use a common default */
 183     warn_report("Invalid RAM size 0x%" PRIx64 ". Using default 256M",
 184                 s->ram_size);
 185     s->ram_size = 256 << 20;
 186     return ASPEED_SDMC_DRAM_256MB;
 187 }
 188
 189 static int ast2500_rambits(AspeedSDMCState *s)
 190 {
 191     switch (s->ram_size >> 20) {
 192     case 128:
 193         return ASPEED_SDMC_AST2500_128MB;
 194     case 256:
 195         return ASPEED_SDMC_AST2500_256MB;
 196     case 512:
 197         return ASPEED_SDMC_AST2500_512MB;
 198     case 1024:
 199         return ASPEED_SDMC_AST2500_1024MB;
 200     default:
 201         break;
 202     }
 203
 204     /* use a common default */
 205     warn_report("Invalid RAM size 0x%" PRIx64 ". Using default 512M",
 206                 s->ram_size);
 207     s->ram_size = 512 << 20;
 208     return ASPEED_SDMC_AST2500_512MB;
 209 }
 210
 211 static void aspeed_sdmc_reset(DeviceState *dev)
 212 {
 213     AspeedSDMCState *s = ASPEED_SDMC(dev);
 214
 215     memset(s->regs, 0, sizeof(s->regs));
 216
 217     /* Set ram size bit and defaults values */
 218     s->regs[R_CONF] = s->fixed_conf;
 219 }
 220
 221 static void aspeed_sdmc_realize(DeviceState *dev, Error **errp)
 222 {
 223     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 224     AspeedSDMCState *s = ASPEED_SDMC(dev);
 225
 226     if (!is_supported_silicon_rev(s->silicon_rev)) {
 227         error_setg(errp, "Unknown silicon revision: 0x%" PRIx32,
 228                 s->silicon_rev);
 229         return;
 230     }
 231
 232     switch (s->silicon_rev) {
 233     case AST2400_A0_SILICON_REV:
 234     case AST2400_A1_SILICON_REV:
 235         s->ram_bits = ast2400_rambits(s);
 236         s->fixed_conf = ASPEED_SDMC_VGA_COMPAT |
 237             ASPEED_SDMC_DRAM_SIZE(s->ram_bits);
 238         break;
 239     case AST2500_A0_SILICON_REV:
 240     case AST2500_A1_SILICON_REV:
 241         s->ram_bits = ast2500_rambits(s);
 242         s->fixed_conf = ASPEED_SDMC_HW_VERSION(1) |
 243             ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) |
 244             ASPEED_SDMC_CACHE_INITIAL_DONE |
 245             ASPEED_SDMC_DRAM_SIZE(s->ram_bits);
 246         break;
 247     default:
 248         g_assert_not_reached();
 249     }
 250
 251     memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_sdmc_ops, s,
 252                           TYPE_ASPEED_SDMC, 0x1000);
 253     sysbus_init_mmio(sbd, &s->iomem);
 254 }
 255
 256 static const VMStateDescription vmstate_aspeed_sdmc = {
 257     .name = "aspeed.sdmc",
 258     .version_id = 1,
 259     .minimum_version_id = 1,
 260     .fields = (VMStateField[]) {
 261         VMSTATE_UINT32_ARRAY(regs, AspeedSDMCState, ASPEED_SDMC_NR_REGS),
 262         VMSTATE_END_OF_LIST()
 263     }
 264 };
 265
 266 static Property aspeed_sdmc_properties[] = {
 267     DEFINE_PROP_UINT32("silicon-rev", AspeedSDMCState, silicon_rev, 0),
 268     DEFINE_PROP_UINT64("ram-size", AspeedSDMCState, ram_size, 0),
 269     DEFINE_PROP_END_OF_LIST(),
 270 };
 271
 272 static void aspeed_sdmc_class_init(ObjectClass *klass, void *data)
 273 {
 274     DeviceClass *dc = DEVICE_CLASS(klass);
 275     dc->realize = aspeed_sdmc_realize;
 276     dc->reset = aspeed_sdmc_reset;
 277     dc->desc = "ASPEED SDRAM Memory Controller";
 278     dc->vmsd = &vmstate_aspeed_sdmc;
 279     dc->props = aspeed_sdmc_properties;
 280 }
 281
 282 static const TypeInfo aspeed_sdmc_info = {
 283     .name = TYPE_ASPEED_SDMC,
 284     .parent = TYPE_SYS_BUS_DEVICE,
 285     .instance_size = sizeof(AspeedSDMCState),
 286     .class_init = aspeed_sdmc_class_init,
 287 };
 288
 289 static void aspeed_sdmc_register_types(void)
 290 {
 291     type_register_static(&aspeed_sdmc_info);
 292 }
 293
 294 type_init(aspeed_sdmc_register_types);