| commit | 33883ce840b291f4f5767aea911b56acae8dfb66 | |
| author | Joel Stanley <joel@jms.id.au> | |
| Thu, 16 Aug 2018 13:05:29 +0000 (16 14:05 +0100) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Thu, 16 Aug 2018 13:29:58 +0000 (16 14:29 +0100) | ||
| tree | f025cdf610d095c2da4563ef86a510dd001d0dc9 | treesnapshot (tar.gz zip) |
| parent | b33f1e0b8921c95d744880e9f963b16a00653cad | commitdiff |
aspeed_sdmc: Init status always idle
The ast2500 SDRAM training routine busy waits on the 'init cycle busy
state' bit in DDR PHY Control/Status register #1 (MCR60).
This ensures the bit always reads zero, and allows training to
complete with upstream u-boot on the ast2500-evb.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20180807075757.7242-5-joel@jms.id.au
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
The ast2500 SDRAM training routine busy waits on the 'init cycle busy
state' bit in DDR PHY Control/Status register #1 (MCR60).
This ensures the bit always reads zero, and allows training to
complete with upstream u-boot on the ast2500-evb.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20180807075757.7242-5-joel@jms.id.au
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| hw/misc/aspeed_sdmc.c | diffblobblamehistory |