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vmxnet3: Reset packet state after emptying Tx queue
[qemu/armbru.git] / hw / net / e1000e_core.c
blob7dce44865781fac36bff7d7564d43d00981b240e
1 /*
2 * Core code for QEMU e1000e emulation
3 *
4 * Software developer's manuals:
5 * http://www.intel.com/content/dam/doc/datasheet/82574l-gbe-controller-datasheet.pdf
6 *
7 * Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com)
8 * Developed by Daynix Computing LTD (http://www.daynix.com)
9 *
10 * Authors:
11 * Dmitry Fleytman <dmitry@daynix.com>
12 * Leonid Bloch <leonid@daynix.com>
13 * Yan Vugenfirer <yan@daynix.com>
14 *
15 * Based on work done by:
16 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
17 * Copyright (c) 2008 Qumranet
18 * Based on work done by:
19 * Copyright (c) 2007 Dan Aloni
20 * Copyright (c) 2004 Antony T Curtis
21 *
22 * This library is free software; you can redistribute it and/or
23 * modify it under the terms of the GNU Lesser General Public
24 * License as published by the Free Software Foundation; either
25 * version 2.1 of the License, or (at your option) any later version.
26 *
27 * This library is distributed in the hope that it will be useful,
28 * but WITHOUT ANY WARRANTY; without even the implied warranty of
29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
30 * Lesser General Public License for more details.
31 *
32 * You should have received a copy of the GNU Lesser General Public
33 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
34 */
35
36 #include "qemu/osdep.h"
37 #include "qemu/log.h"
38 #include "net/net.h"
39 #include "net/tap.h"
40 #include "hw/net/mii.h"
41 #include "hw/pci/msi.h"
42 #include "hw/pci/msix.h"
43 #include "sysemu/runstate.h"
44
45 #include "net_tx_pkt.h"
46 #include "net_rx_pkt.h"
47
48 #include "e1000_common.h"
49 #include "e1000x_common.h"
50 #include "e1000e_core.h"
51
52 #include "trace.h"
53
54 /* No more then 7813 interrupts per second according to spec 10.2.4.2 */
55 #define E1000E_MIN_XITR (500)
56
57 #define E1000E_MAX_TX_FRAGS (64)
58
59 union e1000_rx_desc_union {
60 struct e1000_rx_desc legacy;
61 union e1000_rx_desc_extended extended;
62 union e1000_rx_desc_packet_split packet_split;
63 };
64
65 static ssize_t
66 e1000e_receive_internal(E1000ECore *core, const struct iovec *iov, int iovcnt,
67 bool has_vnet);
68
69 static inline void
70 e1000e_set_interrupt_cause(E1000ECore *core, uint32_t val);
71
72 static void e1000e_reset(E1000ECore *core, bool sw);
73
74 static inline void
75 e1000e_process_ts_option(E1000ECore *core, struct e1000_tx_desc *dp)
76 {
77 if (le32_to_cpu(dp->upper.data) & E1000_TXD_EXTCMD_TSTAMP) {
78 trace_e1000e_wrn_no_ts_support();
79 }
80 }
81
82 static inline void
83 e1000e_process_snap_option(E1000ECore *core, uint32_t cmd_and_length)
84 {
85 if (cmd_and_length & E1000_TXD_CMD_SNAP) {
86 trace_e1000e_wrn_no_snap_support();
87 }
88 }
89
90 static inline void
91 e1000e_raise_legacy_irq(E1000ECore *core)
92 {
93 trace_e1000e_irq_legacy_notify(true);
94 e1000x_inc_reg_if_not_full(core->mac, IAC);
95 pci_set_irq(core->owner, 1);
96 }
97
98 static inline void
99 e1000e_lower_legacy_irq(E1000ECore *core)
100 {
101 trace_e1000e_irq_legacy_notify(false);
102 pci_set_irq(core->owner, 0);
103 }
104
105 static inline void
106 e1000e_intrmgr_rearm_timer(E1000IntrDelayTimer *timer)
107 {
108 int64_t delay_ns = (int64_t) timer->core->mac[timer->delay_reg] *
109 timer->delay_resolution_ns;
110
111 trace_e1000e_irq_rearm_timer(timer->delay_reg << 2, delay_ns);
112
113 timer_mod(timer->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + delay_ns);
114
115 timer->running = true;
116 }
117
118 static void
119 e1000e_intmgr_timer_resume(E1000IntrDelayTimer *timer)
120 {
121 if (timer->running) {
122 e1000e_intrmgr_rearm_timer(timer);
123 }
124 }
125
126 static void
127 e1000e_intmgr_timer_pause(E1000IntrDelayTimer *timer)
128 {
129 if (timer->running) {
130 timer_del(timer->timer);
131 }
132 }
133
134 static inline void
135 e1000e_intrmgr_stop_timer(E1000IntrDelayTimer *timer)
136 {
137 if (timer->running) {
138 timer_del(timer->timer);
139 timer->running = false;
140 }
141 }
142
143 static inline void
144 e1000e_intrmgr_fire_delayed_interrupts(E1000ECore *core)
145 {
146 trace_e1000e_irq_fire_delayed_interrupts();
147 e1000e_set_interrupt_cause(core, 0);
148 }
149
150 static void
151 e1000e_intrmgr_on_timer(void *opaque)
152 {
153 E1000IntrDelayTimer *timer = opaque;
154
155 trace_e1000e_irq_throttling_timer(timer->delay_reg << 2);
156
157 timer->running = false;
158 e1000e_intrmgr_fire_delayed_interrupts(timer->core);
159 }
160
161 static void
162 e1000e_intrmgr_on_throttling_timer(void *opaque)
163 {
164 E1000IntrDelayTimer *timer = opaque;
165
166 timer->running = false;
167
168 if (msi_enabled(timer->core->owner)) {
169 trace_e1000e_irq_msi_notify_postponed();
170 /* Clear msi_causes_pending to fire MSI eventually */
171 timer->core->msi_causes_pending = 0;
172 e1000e_set_interrupt_cause(timer->core, 0);
173 } else {
174 trace_e1000e_irq_legacy_notify_postponed();
175 e1000e_set_interrupt_cause(timer->core, 0);
176 }
177 }
178
179 static void
180 e1000e_intrmgr_on_msix_throttling_timer(void *opaque)
181 {
182 E1000IntrDelayTimer *timer = opaque;
183 int idx = timer - &timer->core->eitr[0];
184
185 timer->running = false;
186
187 trace_e1000e_irq_msix_notify_postponed_vec(idx);
188 msix_notify(timer->core->owner, idx);
189 }
190
191 static void
192 e1000e_intrmgr_initialize_all_timers(E1000ECore *core, bool create)
193 {
194 int i;
195
196 core->radv.delay_reg = RADV;
197 core->rdtr.delay_reg = RDTR;
198 core->raid.delay_reg = RAID;
199 core->tadv.delay_reg = TADV;
200 core->tidv.delay_reg = TIDV;
201
202 core->radv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES;
203 core->rdtr.delay_resolution_ns = E1000_INTR_DELAY_NS_RES;
204 core->raid.delay_resolution_ns = E1000_INTR_DELAY_NS_RES;
205 core->tadv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES;
206 core->tidv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES;
207
208 core->radv.core = core;
209 core->rdtr.core = core;
210 core->raid.core = core;
211 core->tadv.core = core;
212 core->tidv.core = core;
213
214 core->itr.core = core;
215 core->itr.delay_reg = ITR;
216 core->itr.delay_resolution_ns = E1000_INTR_THROTTLING_NS_RES;
217
218 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
219 core->eitr[i].core = core;
220 core->eitr[i].delay_reg = EITR + i;
221 core->eitr[i].delay_resolution_ns = E1000_INTR_THROTTLING_NS_RES;
222 }
223
224 if (!create) {
225 return;
226 }
227
228 core->radv.timer =
229 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->radv);
230 core->rdtr.timer =
231 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->rdtr);
232 core->raid.timer =
233 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->raid);
234
235 core->tadv.timer =
236 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->tadv);
237 core->tidv.timer =
238 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->tidv);
239
240 core->itr.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
241 e1000e_intrmgr_on_throttling_timer,
242 &core->itr);
243
244 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
245 core->eitr[i].timer =
246 timer_new_ns(QEMU_CLOCK_VIRTUAL,
247 e1000e_intrmgr_on_msix_throttling_timer,
248 &core->eitr[i]);
249 }
250 }
251
252 static inline void
253 e1000e_intrmgr_stop_delay_timers(E1000ECore *core)
254 {
255 e1000e_intrmgr_stop_timer(&core->radv);
256 e1000e_intrmgr_stop_timer(&core->rdtr);
257 e1000e_intrmgr_stop_timer(&core->raid);
258 e1000e_intrmgr_stop_timer(&core->tidv);
259 e1000e_intrmgr_stop_timer(&core->tadv);
260 }
261
262 static bool
263 e1000e_intrmgr_delay_rx_causes(E1000ECore *core, uint32_t *causes)
264 {
265 uint32_t delayable_causes;
266 uint32_t rdtr = core->mac[RDTR];
267 uint32_t radv = core->mac[RADV];
268 uint32_t raid = core->mac[RAID];
269
270 if (msix_enabled(core->owner)) {
271 return false;
272 }
273
274 delayable_causes = E1000_ICR_RXQ0 |
275 E1000_ICR_RXQ1 |
276 E1000_ICR_RXT0;
277
278 if (!(core->mac[RFCTL] & E1000_RFCTL_ACK_DIS)) {
279 delayable_causes |= E1000_ICR_ACK;
280 }
281
282 /* Clean up all causes that may be delayed */
283 core->delayed_causes |= *causes & delayable_causes;
284 *causes &= ~delayable_causes;
285
286 /*
287 * Check if delayed RX interrupts disabled by client
288 * or if there are causes that cannot be delayed
289 */
290 if ((rdtr == 0) || (*causes != 0)) {
291 return false;
292 }
293
294 /*
295 * Check if delayed RX ACK interrupts disabled by client
296 * and there is an ACK packet received
297 */
298 if ((raid == 0) && (core->delayed_causes & E1000_ICR_ACK)) {
299 return false;
300 }
301
302 /* All causes delayed */
303 e1000e_intrmgr_rearm_timer(&core->rdtr);
304
305 if (!core->radv.running && (radv != 0)) {
306 e1000e_intrmgr_rearm_timer(&core->radv);
307 }
308
309 if (!core->raid.running && (core->delayed_causes & E1000_ICR_ACK)) {
310 e1000e_intrmgr_rearm_timer(&core->raid);
311 }
312
313 return true;
314 }
315
316 static bool
317 e1000e_intrmgr_delay_tx_causes(E1000ECore *core, uint32_t *causes)
318 {
319 static const uint32_t delayable_causes = E1000_ICR_TXQ0 |
320 E1000_ICR_TXQ1 |
321 E1000_ICR_TXQE |
322 E1000_ICR_TXDW;
323
324 if (msix_enabled(core->owner)) {
325 return false;
326 }
327
328 /* Clean up all causes that may be delayed */
329 core->delayed_causes |= *causes & delayable_causes;
330 *causes &= ~delayable_causes;
331
332 /* If there are causes that cannot be delayed */
333 if (*causes != 0) {
334 return false;
335 }
336
337 /* All causes delayed */
338 e1000e_intrmgr_rearm_timer(&core->tidv);
339
340 if (!core->tadv.running && (core->mac[TADV] != 0)) {
341 e1000e_intrmgr_rearm_timer(&core->tadv);
342 }
343
344 return true;
345 }
346
347 static uint32_t
348 e1000e_intmgr_collect_delayed_causes(E1000ECore *core)
349 {
350 uint32_t res;
351
352 if (msix_enabled(core->owner)) {
353 assert(core->delayed_causes == 0);
354 return 0;
355 }
356
357 res = core->delayed_causes;
358 core->delayed_causes = 0;
359
360 e1000e_intrmgr_stop_delay_timers(core);
361
362 return res;
363 }
364
365 static void
366 e1000e_intrmgr_fire_all_timers(E1000ECore *core)
367 {
368 int i;
369 uint32_t val = e1000e_intmgr_collect_delayed_causes(core);
370
371 trace_e1000e_irq_adding_delayed_causes(val, core->mac[ICR]);
372 core->mac[ICR] |= val;
373
374 if (core->itr.running) {
375 timer_del(core->itr.timer);
376 e1000e_intrmgr_on_throttling_timer(&core->itr);
377 }
378
379 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
380 if (core->eitr[i].running) {
381 timer_del(core->eitr[i].timer);
382 e1000e_intrmgr_on_msix_throttling_timer(&core->eitr[i]);
383 }
384 }
385 }
386
387 static void
388 e1000e_intrmgr_resume(E1000ECore *core)
389 {
390 int i;
391
392 e1000e_intmgr_timer_resume(&core->radv);
393 e1000e_intmgr_timer_resume(&core->rdtr);
394 e1000e_intmgr_timer_resume(&core->raid);
395 e1000e_intmgr_timer_resume(&core->tidv);
396 e1000e_intmgr_timer_resume(&core->tadv);
397
398 e1000e_intmgr_timer_resume(&core->itr);
399
400 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
401 e1000e_intmgr_timer_resume(&core->eitr[i]);
402 }
403 }
404
405 static void
406 e1000e_intrmgr_pause(E1000ECore *core)
407 {
408 int i;
409
410 e1000e_intmgr_timer_pause(&core->radv);
411 e1000e_intmgr_timer_pause(&core->rdtr);
412 e1000e_intmgr_timer_pause(&core->raid);
413 e1000e_intmgr_timer_pause(&core->tidv);
414 e1000e_intmgr_timer_pause(&core->tadv);
415
416 e1000e_intmgr_timer_pause(&core->itr);
417
418 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
419 e1000e_intmgr_timer_pause(&core->eitr[i]);
420 }
421 }
422
423 static void
424 e1000e_intrmgr_reset(E1000ECore *core)
425 {
426 int i;
427
428 core->delayed_causes = 0;
429
430 e1000e_intrmgr_stop_delay_timers(core);
431
432 e1000e_intrmgr_stop_timer(&core->itr);
433
434 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
435 e1000e_intrmgr_stop_timer(&core->eitr[i]);
436 }
437 }
438
439 static void
440 e1000e_intrmgr_pci_unint(E1000ECore *core)
441 {
442 int i;
443
444 timer_free(core->radv.timer);
445 timer_free(core->rdtr.timer);
446 timer_free(core->raid.timer);
447
448 timer_free(core->tadv.timer);
449 timer_free(core->tidv.timer);
450
451 timer_free(core->itr.timer);
452
453 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
454 timer_free(core->eitr[i].timer);
455 }
456 }
457
458 static void
459 e1000e_intrmgr_pci_realize(E1000ECore *core)
460 {
461 e1000e_intrmgr_initialize_all_timers(core, true);
462 }
463
464 static inline bool
465 e1000e_rx_csum_enabled(E1000ECore *core)
466 {
467 return (core->mac[RXCSUM] & E1000_RXCSUM_PCSD) ? false : true;
468 }
469
470 static inline bool
471 e1000e_rx_use_legacy_descriptor(E1000ECore *core)
472 {
473 return (core->mac[RFCTL] & E1000_RFCTL_EXTEN) ? false : true;
474 }
475
476 static inline bool
477 e1000e_rx_use_ps_descriptor(E1000ECore *core)
478 {
479 return !e1000e_rx_use_legacy_descriptor(core) &&
480 (core->mac[RCTL] & E1000_RCTL_DTYP_PS);
481 }
482
483 static inline bool
484 e1000e_rss_enabled(E1000ECore *core)
485 {
486 return E1000_MRQC_ENABLED(core->mac[MRQC]) &&
487 !e1000e_rx_csum_enabled(core) &&
488 !e1000e_rx_use_legacy_descriptor(core);
489 }
490
491 typedef struct E1000E_RSSInfo_st {
492 bool enabled;
493 uint32_t hash;
494 uint32_t queue;
495 uint32_t type;
496 } E1000E_RSSInfo;
497
498 static uint32_t
499 e1000e_rss_get_hash_type(E1000ECore *core, struct NetRxPkt *pkt)
500 {
501 bool hasip4, hasip6;
502 EthL4HdrProto l4hdr_proto;
503
504 assert(e1000e_rss_enabled(core));
505
506 net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto);
507
508 if (hasip4) {
509 trace_e1000e_rx_rss_ip4(l4hdr_proto, core->mac[MRQC],
510 E1000_MRQC_EN_TCPIPV4(core->mac[MRQC]),
511 E1000_MRQC_EN_IPV4(core->mac[MRQC]));
512
513 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP &&
514 E1000_MRQC_EN_TCPIPV4(core->mac[MRQC])) {
515 return E1000_MRQ_RSS_TYPE_IPV4TCP;
516 }
517
518 if (E1000_MRQC_EN_IPV4(core->mac[MRQC])) {
519 return E1000_MRQ_RSS_TYPE_IPV4;
520 }
521 } else if (hasip6) {
522 eth_ip6_hdr_info *ip6info = net_rx_pkt_get_ip6_info(pkt);
523
524 bool ex_dis = core->mac[RFCTL] & E1000_RFCTL_IPV6_EX_DIS;
525 bool new_ex_dis = core->mac[RFCTL] & E1000_RFCTL_NEW_IPV6_EXT_DIS;
526
527 /*
528 * Following two traces must not be combined because resulting
529 * event will have 11 arguments totally and some trace backends
530 * (at least "ust") have limitation of maximum 10 arguments per
531 * event. Events with more arguments fail to compile for
532 * backends like these.
533 */
534 trace_e1000e_rx_rss_ip6_rfctl(core->mac[RFCTL]);
535 trace_e1000e_rx_rss_ip6(ex_dis, new_ex_dis, l4hdr_proto,
536 ip6info->has_ext_hdrs,
537 ip6info->rss_ex_dst_valid,
538 ip6info->rss_ex_src_valid,
539 core->mac[MRQC],
540 E1000_MRQC_EN_TCPIPV6EX(core->mac[MRQC]),
541 E1000_MRQC_EN_IPV6EX(core->mac[MRQC]),
542 E1000_MRQC_EN_IPV6(core->mac[MRQC]));
543
544 if ((!ex_dis || !ip6info->has_ext_hdrs) &&
545 (!new_ex_dis || !(ip6info->rss_ex_dst_valid ||
546 ip6info->rss_ex_src_valid))) {
547
548 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP &&
549 E1000_MRQC_EN_TCPIPV6EX(core->mac[MRQC])) {
550 return E1000_MRQ_RSS_TYPE_IPV6TCPEX;
551 }
552
553 if (E1000_MRQC_EN_IPV6EX(core->mac[MRQC])) {
554 return E1000_MRQ_RSS_TYPE_IPV6EX;
555 }
556
557 }
558
559 if (E1000_MRQC_EN_IPV6(core->mac[MRQC])) {
560 return E1000_MRQ_RSS_TYPE_IPV6;
561 }
562
563 }
564
565 return E1000_MRQ_RSS_TYPE_NONE;
566 }
567
568 static uint32_t
569 e1000e_rss_calc_hash(E1000ECore *core,
570 struct NetRxPkt *pkt,
571 E1000E_RSSInfo *info)
572 {
573 NetRxPktRssType type;
574
575 assert(e1000e_rss_enabled(core));
576
577 switch (info->type) {
578 case E1000_MRQ_RSS_TYPE_IPV4:
579 type = NetPktRssIpV4;
580 break;
581 case E1000_MRQ_RSS_TYPE_IPV4TCP:
582 type = NetPktRssIpV4Tcp;
583 break;
584 case E1000_MRQ_RSS_TYPE_IPV6TCPEX:
585 type = NetPktRssIpV6TcpEx;
586 break;
587 case E1000_MRQ_RSS_TYPE_IPV6:
588 type = NetPktRssIpV6;
589 break;
590 case E1000_MRQ_RSS_TYPE_IPV6EX:
591 type = NetPktRssIpV6Ex;
592 break;
593 default:
594 assert(false);
595 return 0;
596 }
597
598 return net_rx_pkt_calc_rss_hash(pkt, type, (uint8_t *) &core->mac[RSSRK]);
599 }
600
601 static void
602 e1000e_rss_parse_packet(E1000ECore *core,
603 struct NetRxPkt *pkt,
604 E1000E_RSSInfo *info)
605 {
606 trace_e1000e_rx_rss_started();
607
608 if (!e1000e_rss_enabled(core)) {
609 info->enabled = false;
610 info->hash = 0;
611 info->queue = 0;
612 info->type = 0;
613 trace_e1000e_rx_rss_disabled();
614 return;
615 }
616
617 info->enabled = true;
618
619 info->type = e1000e_rss_get_hash_type(core, pkt);
620
621 trace_e1000e_rx_rss_type(info->type);
622
623 if (info->type == E1000_MRQ_RSS_TYPE_NONE) {
624 info->hash = 0;
625 info->queue = 0;
626 return;
627 }
628
629 info->hash = e1000e_rss_calc_hash(core, pkt, info);
630 info->queue = E1000_RSS_QUEUE(&core->mac[RETA], info->hash);
631 }
632
633 static bool
634 e1000e_setup_tx_offloads(E1000ECore *core, struct e1000e_tx *tx)
635 {
636 if (tx->props.tse && tx->cptse) {
637 if (!net_tx_pkt_build_vheader(tx->tx_pkt, true, true, tx->props.mss)) {
638 return false;
639 }
640
641 net_tx_pkt_update_ip_checksums(tx->tx_pkt);
642 e1000x_inc_reg_if_not_full(core->mac, TSCTC);
643 return true;
644 }
645
646 if (tx->sum_needed & E1000_TXD_POPTS_TXSM) {
647 if (!net_tx_pkt_build_vheader(tx->tx_pkt, false, true, 0)) {
648 return false;
649 }
650 }
651
652 if (tx->sum_needed & E1000_TXD_POPTS_IXSM) {
653 net_tx_pkt_update_ip_hdr_checksum(tx->tx_pkt);
654 }
655
656 return true;
657 }
658
659 static void e1000e_tx_pkt_callback(void *core,
660 const struct iovec *iov,
661 int iovcnt,
662 const struct iovec *virt_iov,
663 int virt_iovcnt)
664 {
665 e1000e_receive_internal(core, virt_iov, virt_iovcnt, true);
666 }
667
668 static bool
669 e1000e_tx_pkt_send(E1000ECore *core, struct e1000e_tx *tx, int queue_index)
670 {
671 int target_queue = MIN(core->max_queue_num, queue_index);
672 NetClientState *queue = qemu_get_subqueue(core->owner_nic, target_queue);
673
674 if (!e1000e_setup_tx_offloads(core, tx)) {
675 return false;
676 }
677
678 net_tx_pkt_dump(tx->tx_pkt);
679
680 if ((core->phy[0][MII_BMCR] & MII_BMCR_LOOPBACK) ||
681 ((core->mac[RCTL] & E1000_RCTL_LBM_MAC) == E1000_RCTL_LBM_MAC)) {
682 return net_tx_pkt_send_custom(tx->tx_pkt, false,
683 e1000e_tx_pkt_callback, core);
684 } else {
685 return net_tx_pkt_send(tx->tx_pkt, queue);
686 }
687 }
688
689 static void
690 e1000e_on_tx_done_update_stats(E1000ECore *core, struct NetTxPkt *tx_pkt)
691 {
692 static const int PTCregs[6] = { PTC64, PTC127, PTC255, PTC511,
693 PTC1023, PTC1522 };
694
695 size_t tot_len = net_tx_pkt_get_total_len(tx_pkt) + 4;
696
697 e1000x_increase_size_stats(core->mac, PTCregs, tot_len);
698 e1000x_inc_reg_if_not_full(core->mac, TPT);
699 e1000x_grow_8reg_if_not_full(core->mac, TOTL, tot_len);
700
701 switch (net_tx_pkt_get_packet_type(tx_pkt)) {
702 case ETH_PKT_BCAST:
703 e1000x_inc_reg_if_not_full(core->mac, BPTC);
704 break;
705 case ETH_PKT_MCAST:
706 e1000x_inc_reg_if_not_full(core->mac, MPTC);
707 break;
708 case ETH_PKT_UCAST:
709 break;
710 default:
711 g_assert_not_reached();
712 }
713
714 e1000x_inc_reg_if_not_full(core->mac, GPTC);
715 e1000x_grow_8reg_if_not_full(core->mac, GOTCL, tot_len);
716 }
717
718 static void
719 e1000e_process_tx_desc(E1000ECore *core,
720 struct e1000e_tx *tx,
721 struct e1000_tx_desc *dp,
722 int queue_index)
723 {
724 uint32_t txd_lower = le32_to_cpu(dp->lower.data);
725 uint32_t dtype = txd_lower & (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D);
726 unsigned int split_size = txd_lower & 0xffff;
727 uint64_t addr;
728 struct e1000_context_desc *xp = (struct e1000_context_desc *)dp;
729 bool eop = txd_lower & E1000_TXD_CMD_EOP;
730
731 if (dtype == E1000_TXD_CMD_DEXT) { /* context descriptor */
732 e1000x_read_tx_ctx_descr(xp, &tx->props);
733 e1000e_process_snap_option(core, le32_to_cpu(xp->cmd_and_length));
734 return;
735 } else if (dtype == (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)) {
736 /* data descriptor */
737 tx->sum_needed = le32_to_cpu(dp->upper.data) >> 8;
738 tx->cptse = (txd_lower & E1000_TXD_CMD_TSE) ? 1 : 0;
739 e1000e_process_ts_option(core, dp);
740 } else {
741 /* legacy descriptor */
742 e1000e_process_ts_option(core, dp);
743 tx->cptse = 0;
744 }
745
746 addr = le64_to_cpu(dp->buffer_addr);
747
748 if (!tx->skip_cp) {
749 if (!net_tx_pkt_add_raw_fragment_pci(tx->tx_pkt, core->owner,
750 addr, split_size)) {
751 tx->skip_cp = true;
752 }
753 }
754
755 if (eop) {
756 if (!tx->skip_cp && net_tx_pkt_parse(tx->tx_pkt)) {
757 if (e1000x_vlan_enabled(core->mac) &&
758 e1000x_is_vlan_txd(txd_lower)) {
759 net_tx_pkt_setup_vlan_header_ex(tx->tx_pkt,
760 le16_to_cpu(dp->upper.fields.special), core->mac[VET]);
761 }
762 if (e1000e_tx_pkt_send(core, tx, queue_index)) {
763 e1000e_on_tx_done_update_stats(core, tx->tx_pkt);
764 }
765 }
766
767 tx->skip_cp = false;
768 net_tx_pkt_reset(tx->tx_pkt, net_tx_pkt_unmap_frag_pci, core->owner);
769
770 tx->sum_needed = 0;
771 tx->cptse = 0;
772 }
773 }
774
775 static inline uint32_t
776 e1000e_tx_wb_interrupt_cause(E1000ECore *core, int queue_idx)
777 {
778 if (!msix_enabled(core->owner)) {
779 return E1000_ICR_TXDW;
780 }
781
782 return (queue_idx == 0) ? E1000_ICR_TXQ0 : E1000_ICR_TXQ1;
783 }
784
785 static inline uint32_t
786 e1000e_rx_wb_interrupt_cause(E1000ECore *core, int queue_idx,
787 bool min_threshold_hit)
788 {
789 if (!msix_enabled(core->owner)) {
790 return E1000_ICS_RXT0 | (min_threshold_hit ? E1000_ICS_RXDMT0 : 0);
791 }
792
793 return (queue_idx == 0) ? E1000_ICR_RXQ0 : E1000_ICR_RXQ1;
794 }
795
796 static uint32_t
797 e1000e_txdesc_writeback(E1000ECore *core, dma_addr_t base,
798 struct e1000_tx_desc *dp, bool *ide, int queue_idx)
799 {
800 uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data);
801
802 if (!(txd_lower & E1000_TXD_CMD_RS) &&
803 !(core->mac[IVAR] & E1000_IVAR_TX_INT_EVERY_WB)) {
804 return 0;
805 }
806
807 *ide = (txd_lower & E1000_TXD_CMD_IDE) ? true : false;
808
809 txd_upper = le32_to_cpu(dp->upper.data) | E1000_TXD_STAT_DD;
810
811 dp->upper.data = cpu_to_le32(txd_upper);
812 pci_dma_write(core->owner, base + ((char *)&dp->upper - (char *)dp),
813 &dp->upper, sizeof(dp->upper));
814 return e1000e_tx_wb_interrupt_cause(core, queue_idx);
815 }
816
817 typedef struct E1000E_RingInfo_st {
818 int dbah;
819 int dbal;
820 int dlen;
821 int dh;
822 int dt;
823 int idx;
824 } E1000E_RingInfo;
825
826 static inline bool
827 e1000e_ring_empty(E1000ECore *core, const E1000E_RingInfo *r)
828 {
829 return core->mac[r->dh] == core->mac[r->dt] ||
830 core->mac[r->dt] >= core->mac[r->dlen] / E1000_RING_DESC_LEN;
831 }
832
833 static inline uint64_t
834 e1000e_ring_base(E1000ECore *core, const E1000E_RingInfo *r)
835 {
836 uint64_t bah = core->mac[r->dbah];
837 uint64_t bal = core->mac[r->dbal];
838
839 return (bah << 32) + bal;
840 }
841
842 static inline uint64_t
843 e1000e_ring_head_descr(E1000ECore *core, const E1000E_RingInfo *r)
844 {
845 return e1000e_ring_base(core, r) + E1000_RING_DESC_LEN * core->mac[r->dh];
846 }
847
848 static inline void
849 e1000e_ring_advance(E1000ECore *core, const E1000E_RingInfo *r, uint32_t count)
850 {
851 core->mac[r->dh] += count;
852
853 if (core->mac[r->dh] * E1000_RING_DESC_LEN >= core->mac[r->dlen]) {
854 core->mac[r->dh] = 0;
855 }
856 }
857
858 static inline uint32_t
859 e1000e_ring_free_descr_num(E1000ECore *core, const E1000E_RingInfo *r)
860 {
861 trace_e1000e_ring_free_space(r->idx, core->mac[r->dlen],
862 core->mac[r->dh], core->mac[r->dt]);
863
864 if (core->mac[r->dh] <= core->mac[r->dt]) {
865 return core->mac[r->dt] - core->mac[r->dh];
866 }
867
868 if (core->mac[r->dh] > core->mac[r->dt]) {
869 return core->mac[r->dlen] / E1000_RING_DESC_LEN +
870 core->mac[r->dt] - core->mac[r->dh];
871 }
872
873 g_assert_not_reached();
874 return 0;
875 }
876
877 static inline bool
878 e1000e_ring_enabled(E1000ECore *core, const E1000E_RingInfo *r)
879 {
880 return core->mac[r->dlen] > 0;
881 }
882
883 static inline uint32_t
884 e1000e_ring_len(E1000ECore *core, const E1000E_RingInfo *r)
885 {
886 return core->mac[r->dlen];
887 }
888
889 typedef struct E1000E_TxRing_st {
890 const E1000E_RingInfo *i;
891 struct e1000e_tx *tx;
892 } E1000E_TxRing;
893
894 static inline int
895 e1000e_mq_queue_idx(int base_reg_idx, int reg_idx)
896 {
897 return (reg_idx - base_reg_idx) / (0x100 >> 2);
898 }
899
900 static inline void
901 e1000e_tx_ring_init(E1000ECore *core, E1000E_TxRing *txr, int idx)
902 {
903 static const E1000E_RingInfo i[E1000E_NUM_QUEUES] = {
904 { TDBAH, TDBAL, TDLEN, TDH, TDT, 0 },
905 { TDBAH1, TDBAL1, TDLEN1, TDH1, TDT1, 1 }
906 };
907
908 assert(idx < ARRAY_SIZE(i));
909
910 txr->i = &i[idx];
911 txr->tx = &core->tx[idx];
912 }
913
914 typedef struct E1000E_RxRing_st {
915 const E1000E_RingInfo *i;
916 } E1000E_RxRing;
917
918 static inline void
919 e1000e_rx_ring_init(E1000ECore *core, E1000E_RxRing *rxr, int idx)
920 {
921 static const E1000E_RingInfo i[E1000E_NUM_QUEUES] = {
922 { RDBAH0, RDBAL0, RDLEN0, RDH0, RDT0, 0 },
923 { RDBAH1, RDBAL1, RDLEN1, RDH1, RDT1, 1 }
924 };
925
926 assert(idx < ARRAY_SIZE(i));
927
928 rxr->i = &i[idx];
929 }
930
931 static void
932 e1000e_start_xmit(E1000ECore *core, const E1000E_TxRing *txr)
933 {
934 dma_addr_t base;
935 struct e1000_tx_desc desc;
936 bool ide = false;
937 const E1000E_RingInfo *txi = txr->i;
938 uint32_t cause = E1000_ICS_TXQE;
939
940 if (!(core->mac[TCTL] & E1000_TCTL_EN)) {
941 trace_e1000e_tx_disabled();
942 return;
943 }
944
945 while (!e1000e_ring_empty(core, txi)) {
946 base = e1000e_ring_head_descr(core, txi);
947
948 pci_dma_read(core->owner, base, &desc, sizeof(desc));
949
950 trace_e1000e_tx_descr((void *)(intptr_t)desc.buffer_addr,
951 desc.lower.data, desc.upper.data);
952
953 e1000e_process_tx_desc(core, txr->tx, &desc, txi->idx);
954 cause |= e1000e_txdesc_writeback(core, base, &desc, &ide, txi->idx);
955
956 e1000e_ring_advance(core, txi, 1);
957 }
958
959 if (!ide || !e1000e_intrmgr_delay_tx_causes(core, &cause)) {
960 e1000e_set_interrupt_cause(core, cause);
961 }
962
963 net_tx_pkt_reset(txr->tx->tx_pkt, net_tx_pkt_unmap_frag_pci, core->owner);
964 }
965
966 static bool
967 e1000e_has_rxbufs(E1000ECore *core, const E1000E_RingInfo *r,
968 size_t total_size)
969 {
970 uint32_t bufs = e1000e_ring_free_descr_num(core, r);
971
972 trace_e1000e_rx_has_buffers(r->idx, bufs, total_size,
973 core->rx_desc_buf_size);
974
975 return total_size <= bufs / (core->rx_desc_len / E1000_MIN_RX_DESC_LEN) *
976 core->rx_desc_buf_size;
977 }
978
979 void
980 e1000e_start_recv(E1000ECore *core)
981 {
982 int i;
983
984 trace_e1000e_rx_start_recv();
985
986 for (i = 0; i <= core->max_queue_num; i++) {
987 qemu_flush_queued_packets(qemu_get_subqueue(core->owner_nic, i));
988 }
989 }
990
991 bool
992 e1000e_can_receive(E1000ECore *core)
993 {
994 int i;
995
996 if (!e1000x_rx_ready(core->owner, core->mac)) {
997 return false;
998 }
999
1000 for (i = 0; i < E1000E_NUM_QUEUES; i++) {
1001 E1000E_RxRing rxr;
1002
1003 e1000e_rx_ring_init(core, &rxr, i);
1004 if (e1000e_ring_enabled(core, rxr.i) &&
1005 e1000e_has_rxbufs(core, rxr.i, 1)) {
1006 trace_e1000e_rx_can_recv();
1007 return true;
1008 }
1009 }
1010
1011 trace_e1000e_rx_can_recv_rings_full();
1012 return false;
1013 }
1014
1015 ssize_t
1016 e1000e_receive(E1000ECore *core, const uint8_t *buf, size_t size)
1017 {
1018 const struct iovec iov = {
1019 .iov_base = (uint8_t *)buf,
1020 .iov_len = size
1021 };
1022
1023 return e1000e_receive_iov(core, &iov, 1);
1024 }
1025
1026 static inline bool
1027 e1000e_rx_l3_cso_enabled(E1000ECore *core)
1028 {
1029 return !!(core->mac[RXCSUM] & E1000_RXCSUM_IPOFLD);
1030 }
1031
1032 static inline bool
1033 e1000e_rx_l4_cso_enabled(E1000ECore *core)
1034 {
1035 return !!(core->mac[RXCSUM] & E1000_RXCSUM_TUOFLD);
1036 }
1037
1038 static bool
1039 e1000e_receive_filter(E1000ECore *core, const void *buf)
1040 {
1041 return (!e1000x_is_vlan_packet(buf, core->mac[VET]) ||
1042 e1000x_rx_vlan_filter(core->mac, PKT_GET_VLAN_HDR(buf))) &&
1043 e1000x_rx_group_filter(core->mac, buf);
1044 }
1045
1046 static inline void
1047 e1000e_read_lgcy_rx_descr(E1000ECore *core, struct e1000_rx_desc *desc,
1048 hwaddr *buff_addr)
1049 {
1050 *buff_addr = le64_to_cpu(desc->buffer_addr);
1051 }
1052
1053 static inline void
1054 e1000e_read_ext_rx_descr(E1000ECore *core, union e1000_rx_desc_extended *desc,
1055 hwaddr *buff_addr)
1056 {
1057 *buff_addr = le64_to_cpu(desc->read.buffer_addr);
1058 }
1059
1060 static inline void
1061 e1000e_read_ps_rx_descr(E1000ECore *core,
1062 union e1000_rx_desc_packet_split *desc,
1063 hwaddr buff_addr[MAX_PS_BUFFERS])
1064 {
1065 int i;
1066
1067 for (i = 0; i < MAX_PS_BUFFERS; i++) {
1068 buff_addr[i] = le64_to_cpu(desc->read.buffer_addr[i]);
1069 }
1070
1071 trace_e1000e_rx_desc_ps_read(buff_addr[0], buff_addr[1],
1072 buff_addr[2], buff_addr[3]);
1073 }
1074
1075 static inline void
1076 e1000e_read_rx_descr(E1000ECore *core, union e1000_rx_desc_union *desc,
1077 hwaddr buff_addr[MAX_PS_BUFFERS])
1078 {
1079 if (e1000e_rx_use_legacy_descriptor(core)) {
1080 e1000e_read_lgcy_rx_descr(core, &desc->legacy, &buff_addr[0]);
1081 buff_addr[1] = buff_addr[2] = buff_addr[3] = 0;
1082 } else {
1083 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) {
1084 e1000e_read_ps_rx_descr(core, &desc->packet_split, buff_addr);
1085 } else {
1086 e1000e_read_ext_rx_descr(core, &desc->extended, &buff_addr[0]);
1087 buff_addr[1] = buff_addr[2] = buff_addr[3] = 0;
1088 }
1089 }
1090 }
1091
1092 static void
1093 e1000e_verify_csum_in_sw(E1000ECore *core,
1094 struct NetRxPkt *pkt,
1095 uint32_t *status_flags,
1096 EthL4HdrProto l4hdr_proto)
1097 {
1098 bool csum_valid;
1099 uint32_t csum_error;
1100
1101 if (e1000e_rx_l3_cso_enabled(core)) {
1102 if (!net_rx_pkt_validate_l3_csum(pkt, &csum_valid)) {
1103 trace_e1000e_rx_metadata_l3_csum_validation_failed();
1104 } else {
1105 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_IPE;
1106 *status_flags |= E1000_RXD_STAT_IPCS | csum_error;
1107 }
1108 } else {
1109 trace_e1000e_rx_metadata_l3_cso_disabled();
1110 }
1111
1112 if (!e1000e_rx_l4_cso_enabled(core)) {
1113 trace_e1000e_rx_metadata_l4_cso_disabled();
1114 return;
1115 }
1116
1117 if (!net_rx_pkt_validate_l4_csum(pkt, &csum_valid)) {
1118 trace_e1000e_rx_metadata_l4_csum_validation_failed();
1119 return;
1120 }
1121
1122 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_TCPE;
1123 *status_flags |= E1000_RXD_STAT_TCPCS | csum_error;
1124
1125 if (l4hdr_proto == ETH_L4_HDR_PROTO_UDP) {
1126 *status_flags |= E1000_RXD_STAT_UDPCS;
1127 }
1128 }
1129
1130 static inline bool
1131 e1000e_is_tcp_ack(E1000ECore *core, struct NetRxPkt *rx_pkt)
1132 {
1133 if (!net_rx_pkt_is_tcp_ack(rx_pkt)) {
1134 return false;
1135 }
1136
1137 if (core->mac[RFCTL] & E1000_RFCTL_ACK_DATA_DIS) {
1138 return !net_rx_pkt_has_tcp_data(rx_pkt);
1139 }
1140
1141 return true;
1142 }
1143
1144 static void
1145 e1000e_build_rx_metadata(E1000ECore *core,
1146 struct NetRxPkt *pkt,
1147 bool is_eop,
1148 const E1000E_RSSInfo *rss_info,
1149 uint32_t *rss, uint32_t *mrq,
1150 uint32_t *status_flags,
1151 uint16_t *ip_id,
1152 uint16_t *vlan_tag)
1153 {
1154 struct virtio_net_hdr *vhdr;
1155 bool hasip4, hasip6;
1156 EthL4HdrProto l4hdr_proto;
1157 uint32_t pkt_type;
1158
1159 *status_flags = E1000_RXD_STAT_DD;
1160
1161 /* No additional metadata needed for non-EOP descriptors */
1162 if (!is_eop) {
1163 goto func_exit;
1164 }
1165
1166 *status_flags |= E1000_RXD_STAT_EOP;
1167
1168 net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto);
1169 trace_e1000e_rx_metadata_protocols(hasip4, hasip6, l4hdr_proto);
1170
1171 /* VLAN state */
1172 if (net_rx_pkt_is_vlan_stripped(pkt)) {
1173 *status_flags |= E1000_RXD_STAT_VP;
1174 *vlan_tag = cpu_to_le16(net_rx_pkt_get_vlan_tag(pkt));
1175 trace_e1000e_rx_metadata_vlan(*vlan_tag);
1176 }
1177
1178 /* Packet parsing results */
1179 if ((core->mac[RXCSUM] & E1000_RXCSUM_PCSD) != 0) {
1180 if (rss_info->enabled) {
1181 *rss = cpu_to_le32(rss_info->hash);
1182 *mrq = cpu_to_le32(rss_info->type | (rss_info->queue << 8));
1183 trace_e1000e_rx_metadata_rss(*rss, *mrq);
1184 }
1185 } else if (hasip4) {
1186 *status_flags |= E1000_RXD_STAT_IPIDV;
1187 *ip_id = cpu_to_le16(net_rx_pkt_get_ip_id(pkt));
1188 trace_e1000e_rx_metadata_ip_id(*ip_id);
1189 }
1190
1191 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP && e1000e_is_tcp_ack(core, pkt)) {
1192 *status_flags |= E1000_RXD_STAT_ACK;
1193 trace_e1000e_rx_metadata_ack();
1194 }
1195
1196 if (hasip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_DIS)) {
1197 trace_e1000e_rx_metadata_ipv6_filtering_disabled();
1198 pkt_type = E1000_RXD_PKT_MAC;
1199 } else if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP ||
1200 l4hdr_proto == ETH_L4_HDR_PROTO_UDP) {
1201 pkt_type = hasip4 ? E1000_RXD_PKT_IP4_XDP : E1000_RXD_PKT_IP6_XDP;
1202 } else if (hasip4 || hasip6) {
1203 pkt_type = hasip4 ? E1000_RXD_PKT_IP4 : E1000_RXD_PKT_IP6;
1204 } else {
1205 pkt_type = E1000_RXD_PKT_MAC;
1206 }
1207
1208 *status_flags |= E1000_RXD_PKT_TYPE(pkt_type);
1209 trace_e1000e_rx_metadata_pkt_type(pkt_type);
1210
1211 /* RX CSO information */
1212 if (hasip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_XSUM_DIS)) {
1213 trace_e1000e_rx_metadata_ipv6_sum_disabled();
1214 goto func_exit;
1215 }
1216
1217 vhdr = net_rx_pkt_get_vhdr(pkt);
1218
1219 if (!(vhdr->flags & VIRTIO_NET_HDR_F_DATA_VALID) &&
1220 !(vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM)) {
1221 trace_e1000e_rx_metadata_virthdr_no_csum_info();
1222 e1000e_verify_csum_in_sw(core, pkt, status_flags, l4hdr_proto);
1223 goto func_exit;
1224 }
1225
1226 if (e1000e_rx_l3_cso_enabled(core)) {
1227 *status_flags |= hasip4 ? E1000_RXD_STAT_IPCS : 0;
1228 } else {
1229 trace_e1000e_rx_metadata_l3_cso_disabled();
1230 }
1231
1232 if (e1000e_rx_l4_cso_enabled(core)) {
1233 switch (l4hdr_proto) {
1234 case ETH_L4_HDR_PROTO_TCP:
1235 *status_flags |= E1000_RXD_STAT_TCPCS;
1236 break;
1237
1238 case ETH_L4_HDR_PROTO_UDP:
1239 *status_flags |= E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS;
1240 break;
1241
1242 default:
1243 break;
1244 }
1245 } else {
1246 trace_e1000e_rx_metadata_l4_cso_disabled();
1247 }
1248
1249 func_exit:
1250 trace_e1000e_rx_metadata_status_flags(*status_flags);
1251 *status_flags = cpu_to_le32(*status_flags);
1252 }
1253
1254 static inline void
1255 e1000e_write_lgcy_rx_descr(E1000ECore *core, struct e1000_rx_desc *desc,
1256 struct NetRxPkt *pkt,
1257 const E1000E_RSSInfo *rss_info,
1258 uint16_t length)
1259 {
1260 uint32_t status_flags, rss, mrq;
1261 uint16_t ip_id;
1262
1263 assert(!rss_info->enabled);
1264
1265 desc->length = cpu_to_le16(length);
1266 desc->csum = 0;
1267
1268 e1000e_build_rx_metadata(core, pkt, pkt != NULL,
1269 rss_info,
1270 &rss, &mrq,
1271 &status_flags, &ip_id,
1272 &desc->special);
1273 desc->errors = (uint8_t) (le32_to_cpu(status_flags) >> 24);
1274 desc->status = (uint8_t) le32_to_cpu(status_flags);
1275 }
1276
1277 static inline void
1278 e1000e_write_ext_rx_descr(E1000ECore *core, union e1000_rx_desc_extended *desc,
1279 struct NetRxPkt *pkt,
1280 const E1000E_RSSInfo *rss_info,
1281 uint16_t length)
1282 {
1283 memset(&desc->wb, 0, sizeof(desc->wb));
1284
1285 desc->wb.upper.length = cpu_to_le16(length);
1286
1287 e1000e_build_rx_metadata(core, pkt, pkt != NULL,
1288 rss_info,
1289 &desc->wb.lower.hi_dword.rss,
1290 &desc->wb.lower.mrq,
1291 &desc->wb.upper.status_error,
1292 &desc->wb.lower.hi_dword.csum_ip.ip_id,
1293 &desc->wb.upper.vlan);
1294 }
1295
1296 static inline void
1297 e1000e_write_ps_rx_descr(E1000ECore *core,
1298 union e1000_rx_desc_packet_split *desc,
1299 struct NetRxPkt *pkt,
1300 const E1000E_RSSInfo *rss_info,
1301 size_t ps_hdr_len,
1302 uint16_t(*written)[MAX_PS_BUFFERS])
1303 {
1304 int i;
1305
1306 memset(&desc->wb, 0, sizeof(desc->wb));
1307
1308 desc->wb.middle.length0 = cpu_to_le16((*written)[0]);
1309
1310 for (i = 0; i < PS_PAGE_BUFFERS; i++) {
1311 desc->wb.upper.length[i] = cpu_to_le16((*written)[i + 1]);
1312 }
1313
1314 e1000e_build_rx_metadata(core, pkt, pkt != NULL,
1315 rss_info,
1316 &desc->wb.lower.hi_dword.rss,
1317 &desc->wb.lower.mrq,
1318 &desc->wb.middle.status_error,
1319 &desc->wb.lower.hi_dword.csum_ip.ip_id,
1320 &desc->wb.middle.vlan);
1321
1322 desc->wb.upper.header_status =
1323 cpu_to_le16(ps_hdr_len | (ps_hdr_len ? E1000_RXDPS_HDRSTAT_HDRSP : 0));
1324
1325 trace_e1000e_rx_desc_ps_write((*written)[0], (*written)[1],
1326 (*written)[2], (*written)[3]);
1327 }
1328
1329 static inline void
1330 e1000e_write_rx_descr(E1000ECore *core, union e1000_rx_desc_union *desc,
1331 struct NetRxPkt *pkt, const E1000E_RSSInfo *rss_info,
1332 size_t ps_hdr_len, uint16_t(*written)[MAX_PS_BUFFERS])
1333 {
1334 if (e1000e_rx_use_legacy_descriptor(core)) {
1335 assert(ps_hdr_len == 0);
1336 e1000e_write_lgcy_rx_descr(core, &desc->legacy, pkt, rss_info,
1337 (*written)[0]);
1338 } else {
1339 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) {
1340 e1000e_write_ps_rx_descr(core, &desc->packet_split, pkt, rss_info,
1341 ps_hdr_len, written);
1342 } else {
1343 assert(ps_hdr_len == 0);
1344 e1000e_write_ext_rx_descr(core, &desc->extended, pkt, rss_info,
1345 (*written)[0]);
1346 }
1347 }
1348 }
1349
1350 static inline void
1351 e1000e_pci_dma_write_rx_desc(E1000ECore *core, dma_addr_t addr,
1352 union e1000_rx_desc_union *desc, dma_addr_t len)
1353 {
1354 PCIDevice *dev = core->owner;
1355
1356 if (e1000e_rx_use_legacy_descriptor(core)) {
1357 struct e1000_rx_desc *d = &desc->legacy;
1358 size_t offset = offsetof(struct e1000_rx_desc, status);
1359 uint8_t status = d->status;
1360
1361 d->status &= ~E1000_RXD_STAT_DD;
1362 pci_dma_write(dev, addr, desc, len);
1363
1364 if (status & E1000_RXD_STAT_DD) {
1365 d->status = status;
1366 pci_dma_write(dev, addr + offset, &status, sizeof(status));
1367 }
1368 } else {
1369 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) {
1370 union e1000_rx_desc_packet_split *d = &desc->packet_split;
1371 size_t offset = offsetof(union e1000_rx_desc_packet_split,
1372 wb.middle.status_error);
1373 uint32_t status = d->wb.middle.status_error;
1374
1375 d->wb.middle.status_error &= ~E1000_RXD_STAT_DD;
1376 pci_dma_write(dev, addr, desc, len);
1377
1378 if (status & E1000_RXD_STAT_DD) {
1379 d->wb.middle.status_error = status;
1380 pci_dma_write(dev, addr + offset, &status, sizeof(status));
1381 }
1382 } else {
1383 union e1000_rx_desc_extended *d = &desc->extended;
1384 size_t offset = offsetof(union e1000_rx_desc_extended,
1385 wb.upper.status_error);
1386 uint32_t status = d->wb.upper.status_error;
1387
1388 d->wb.upper.status_error &= ~E1000_RXD_STAT_DD;
1389 pci_dma_write(dev, addr, desc, len);
1390
1391 if (status & E1000_RXD_STAT_DD) {
1392 d->wb.upper.status_error = status;
1393 pci_dma_write(dev, addr + offset, &status, sizeof(status));
1394 }
1395 }
1396 }
1397 }
1398
1399 typedef struct e1000e_ba_state_st {
1400 uint16_t written[MAX_PS_BUFFERS];
1401 uint8_t cur_idx;
1402 } e1000e_ba_state;
1403
1404 static inline void
1405 e1000e_write_hdr_to_rx_buffers(E1000ECore *core,
1406 hwaddr ba[MAX_PS_BUFFERS],
1407 e1000e_ba_state *bastate,
1408 const char *data,
1409 dma_addr_t data_len)
1410 {
1411 assert(data_len <= core->rxbuf_sizes[0] - bastate->written[0]);
1412
1413 pci_dma_write(core->owner, ba[0] + bastate->written[0], data, data_len);
1414 bastate->written[0] += data_len;
1415
1416 bastate->cur_idx = 1;
1417 }
1418
1419 static void
1420 e1000e_write_to_rx_buffers(E1000ECore *core,
1421 hwaddr ba[MAX_PS_BUFFERS],
1422 e1000e_ba_state *bastate,
1423 const char *data,
1424 dma_addr_t data_len)
1425 {
1426 while (data_len > 0) {
1427 uint32_t cur_buf_len = core->rxbuf_sizes[bastate->cur_idx];
1428 uint32_t cur_buf_bytes_left = cur_buf_len -
1429 bastate->written[bastate->cur_idx];
1430 uint32_t bytes_to_write = MIN(data_len, cur_buf_bytes_left);
1431
1432 trace_e1000e_rx_desc_buff_write(bastate->cur_idx,
1433 ba[bastate->cur_idx],
1434 bastate->written[bastate->cur_idx],
1435 data,
1436 bytes_to_write);
1437
1438 pci_dma_write(core->owner,
1439 ba[bastate->cur_idx] + bastate->written[bastate->cur_idx],
1440 data, bytes_to_write);
1441
1442 bastate->written[bastate->cur_idx] += bytes_to_write;
1443 data += bytes_to_write;
1444 data_len -= bytes_to_write;
1445
1446 if (bastate->written[bastate->cur_idx] == cur_buf_len) {
1447 bastate->cur_idx++;
1448 }
1449
1450 assert(bastate->cur_idx < MAX_PS_BUFFERS);
1451 }
1452 }
1453
1454 static void
1455 e1000e_update_rx_stats(E1000ECore *core, size_t pkt_size, size_t pkt_fcs_size)
1456 {
1457 eth_pkt_types_e pkt_type = net_rx_pkt_get_packet_type(core->rx_pkt);
1458 e1000x_update_rx_total_stats(core->mac, pkt_type, pkt_size, pkt_fcs_size);
1459 }
1460
1461 static inline bool
1462 e1000e_rx_descr_threshold_hit(E1000ECore *core, const E1000E_RingInfo *rxi)
1463 {
1464 return e1000e_ring_free_descr_num(core, rxi) ==
1465 e1000e_ring_len(core, rxi) >> core->rxbuf_min_shift;
1466 }
1467
1468 static bool
1469 e1000e_do_ps(E1000ECore *core, struct NetRxPkt *pkt, size_t *hdr_len)
1470 {
1471 bool hasip4, hasip6;
1472 EthL4HdrProto l4hdr_proto;
1473 bool fragment;
1474
1475 if (!e1000e_rx_use_ps_descriptor(core)) {
1476 return false;
1477 }
1478
1479 net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto);
1480
1481 if (hasip4) {
1482 fragment = net_rx_pkt_get_ip4_info(pkt)->fragment;
1483 } else if (hasip6) {
1484 fragment = net_rx_pkt_get_ip6_info(pkt)->fragment;
1485 } else {
1486 return false;
1487 }
1488
1489 if (fragment && (core->mac[RFCTL] & E1000_RFCTL_IPFRSP_DIS)) {
1490 return false;
1491 }
1492
1493 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP ||
1494 l4hdr_proto == ETH_L4_HDR_PROTO_UDP) {
1495 *hdr_len = net_rx_pkt_get_l5_hdr_offset(pkt);
1496 } else {
1497 *hdr_len = net_rx_pkt_get_l4_hdr_offset(pkt);
1498 }
1499
1500 if ((*hdr_len > core->rxbuf_sizes[0]) ||
1501 (*hdr_len > net_rx_pkt_get_total_len(pkt))) {
1502 return false;
1503 }
1504
1505 return true;
1506 }
1507
1508 static void
1509 e1000e_write_packet_to_guest(E1000ECore *core, struct NetRxPkt *pkt,
1510 const E1000E_RxRing *rxr,
1511 const E1000E_RSSInfo *rss_info)
1512 {
1513 PCIDevice *d = core->owner;
1514 dma_addr_t base;
1515 union e1000_rx_desc_union desc;
1516 size_t desc_size;
1517 size_t desc_offset = 0;
1518 size_t iov_ofs = 0;
1519
1520 struct iovec *iov = net_rx_pkt_get_iovec(pkt);
1521 size_t size = net_rx_pkt_get_total_len(pkt);
1522 size_t total_size = size + e1000x_fcs_len(core->mac);
1523 const E1000E_RingInfo *rxi;
1524 size_t ps_hdr_len = 0;
1525 bool do_ps = e1000e_do_ps(core, pkt, &ps_hdr_len);
1526 bool is_first = true;
1527
1528 rxi = rxr->i;
1529
1530 do {
1531 hwaddr ba[MAX_PS_BUFFERS];
1532 e1000e_ba_state bastate = { { 0 } };
1533 bool is_last = false;
1534
1535 desc_size = total_size - desc_offset;
1536
1537 if (desc_size > core->rx_desc_buf_size) {
1538 desc_size = core->rx_desc_buf_size;
1539 }
1540
1541 if (e1000e_ring_empty(core, rxi)) {
1542 return;
1543 }
1544
1545 base = e1000e_ring_head_descr(core, rxi);
1546
1547 pci_dma_read(d, base, &desc, core->rx_desc_len);
1548
1549 trace_e1000e_rx_descr(rxi->idx, base, core->rx_desc_len);
1550
1551 e1000e_read_rx_descr(core, &desc, ba);
1552
1553 if (ba[0]) {
1554 if (desc_offset < size) {
1555 static const uint32_t fcs_pad;
1556 size_t iov_copy;
1557 size_t copy_size = size - desc_offset;
1558 if (copy_size > core->rx_desc_buf_size) {
1559 copy_size = core->rx_desc_buf_size;
1560 }
1561
1562 /* For PS mode copy the packet header first */
1563 if (do_ps) {
1564 if (is_first) {
1565 size_t ps_hdr_copied = 0;
1566 do {
1567 iov_copy = MIN(ps_hdr_len - ps_hdr_copied,
1568 iov->iov_len - iov_ofs);
1569
1570 e1000e_write_hdr_to_rx_buffers(core, ba, &bastate,
1571 iov->iov_base, iov_copy);
1572
1573 copy_size -= iov_copy;
1574 ps_hdr_copied += iov_copy;
1575
1576 iov_ofs += iov_copy;
1577 if (iov_ofs == iov->iov_len) {
1578 iov++;
1579 iov_ofs = 0;
1580 }
1581 } while (ps_hdr_copied < ps_hdr_len);
1582
1583 is_first = false;
1584 } else {
1585 /* Leave buffer 0 of each descriptor except first */
1586 /* empty as per spec 7.1.5.1 */
1587 e1000e_write_hdr_to_rx_buffers(core, ba, &bastate,
1588 NULL, 0);
1589 }
1590 }
1591
1592 /* Copy packet payload */
1593 while (copy_size) {
1594 iov_copy = MIN(copy_size, iov->iov_len - iov_ofs);
1595
1596 e1000e_write_to_rx_buffers(core, ba, &bastate,
1597 iov->iov_base + iov_ofs, iov_copy);
1598
1599 copy_size -= iov_copy;
1600 iov_ofs += iov_copy;
1601 if (iov_ofs == iov->iov_len) {
1602 iov++;
1603 iov_ofs = 0;
1604 }
1605 }
1606
1607 if (desc_offset + desc_size >= total_size) {
1608 /* Simulate FCS checksum presence in the last descriptor */
1609 e1000e_write_to_rx_buffers(core, ba, &bastate,
1610 (const char *) &fcs_pad, e1000x_fcs_len(core->mac));
1611 }
1612 }
1613 } else { /* as per intel docs; skip descriptors with null buf addr */
1614 trace_e1000e_rx_null_descriptor();
1615 }
1616 desc_offset += desc_size;
1617 if (desc_offset >= total_size) {
1618 is_last = true;
1619 }
1620
1621 e1000e_write_rx_descr(core, &desc, is_last ? core->rx_pkt : NULL,
1622 rss_info, do_ps ? ps_hdr_len : 0, &bastate.written);
1623 e1000e_pci_dma_write_rx_desc(core, base, &desc, core->rx_desc_len);
1624
1625 e1000e_ring_advance(core, rxi,
1626 core->rx_desc_len / E1000_MIN_RX_DESC_LEN);
1627
1628 } while (desc_offset < total_size);
1629
1630 e1000e_update_rx_stats(core, size, total_size);
1631 }
1632
1633 static inline void
1634 e1000e_rx_fix_l4_csum(E1000ECore *core, struct NetRxPkt *pkt)
1635 {
1636 struct virtio_net_hdr *vhdr = net_rx_pkt_get_vhdr(pkt);
1637
1638 if (vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM) {
1639 net_rx_pkt_fix_l4_csum(pkt);
1640 }
1641 }
1642
1643 ssize_t
1644 e1000e_receive_iov(E1000ECore *core, const struct iovec *iov, int iovcnt)
1645 {
1646 return e1000e_receive_internal(core, iov, iovcnt, core->has_vnet);
1647 }
1648
1649 static ssize_t
1650 e1000e_receive_internal(E1000ECore *core, const struct iovec *iov, int iovcnt,
1651 bool has_vnet)
1652 {
1653 uint32_t n = 0;
1654 uint8_t buf[ETH_ZLEN];
1655 struct iovec min_iov;
1656 size_t size, orig_size;
1657 size_t iov_ofs = 0;
1658 E1000E_RxRing rxr;
1659 E1000E_RSSInfo rss_info;
1660 size_t total_size;
1661 ssize_t retval;
1662 bool rdmts_hit;
1663
1664 trace_e1000e_rx_receive_iov(iovcnt);
1665
1666 if (!e1000x_hw_rx_enabled(core->mac)) {
1667 return -1;
1668 }
1669
1670 /* Pull virtio header in */
1671 if (has_vnet) {
1672 net_rx_pkt_set_vhdr_iovec(core->rx_pkt, iov, iovcnt);
1673 iov_ofs = sizeof(struct virtio_net_hdr);
1674 } else {
1675 net_rx_pkt_unset_vhdr(core->rx_pkt);
1676 }
1677
1678 orig_size = iov_size(iov, iovcnt);
1679 size = orig_size - iov_ofs;
1680
1681 /* Pad to minimum Ethernet frame length */
1682 if (size < sizeof(buf)) {
1683 iov_to_buf(iov, iovcnt, iov_ofs, buf, size);
1684 memset(&buf[size], 0, sizeof(buf) - size);
1685 e1000x_inc_reg_if_not_full(core->mac, RUC);
1686 min_iov.iov_base = buf;
1687 min_iov.iov_len = size = sizeof(buf);
1688 iovcnt = 1;
1689 iov = &min_iov;
1690 iov_ofs = 0;
1691 } else {
1692 iov_to_buf(iov, iovcnt, iov_ofs, buf, ETH_HLEN + 4);
1693 }
1694
1695 /* Discard oversized packets if !LPE and !SBP. */
1696 if (e1000x_is_oversized(core->mac, size)) {
1697 return orig_size;
1698 }
1699
1700 net_rx_pkt_set_packet_type(core->rx_pkt,
1701 get_eth_packet_type(PKT_GET_ETH_HDR(buf)));
1702
1703 if (!e1000e_receive_filter(core, buf)) {
1704 trace_e1000e_rx_flt_dropped();
1705 return orig_size;
1706 }
1707
1708 net_rx_pkt_attach_iovec_ex(core->rx_pkt, iov, iovcnt, iov_ofs,
1709 e1000x_vlan_enabled(core->mac), core->mac[VET]);
1710
1711 e1000e_rss_parse_packet(core, core->rx_pkt, &rss_info);
1712 e1000e_rx_ring_init(core, &rxr, rss_info.queue);
1713
1714 total_size = net_rx_pkt_get_total_len(core->rx_pkt) +
1715 e1000x_fcs_len(core->mac);
1716
1717 if (e1000e_has_rxbufs(core, rxr.i, total_size)) {
1718 e1000e_rx_fix_l4_csum(core, core->rx_pkt);
1719
1720 e1000e_write_packet_to_guest(core, core->rx_pkt, &rxr, &rss_info);
1721
1722 retval = orig_size;
1723
1724 /* Perform small receive detection (RSRPD) */
1725 if (total_size < core->mac[RSRPD]) {
1726 n |= E1000_ICS_SRPD;
1727 }
1728
1729 /* Perform ACK receive detection */
1730 if (!(core->mac[RFCTL] & E1000_RFCTL_ACK_DIS) &&
1731 (e1000e_is_tcp_ack(core, core->rx_pkt))) {
1732 n |= E1000_ICS_ACK;
1733 }
1734
1735 /* Check if receive descriptor minimum threshold hit */
1736 rdmts_hit = e1000e_rx_descr_threshold_hit(core, rxr.i);
1737 n |= e1000e_rx_wb_interrupt_cause(core, rxr.i->idx, rdmts_hit);
1738
1739 trace_e1000e_rx_written_to_guest(rxr.i->idx);
1740 } else {
1741 n |= E1000_ICS_RXO;
1742 retval = 0;
1743
1744 trace_e1000e_rx_not_written_to_guest(rxr.i->idx);
1745 }
1746
1747 if (!e1000e_intrmgr_delay_rx_causes(core, &n)) {
1748 trace_e1000e_rx_interrupt_set(n);
1749 e1000e_set_interrupt_cause(core, n);
1750 } else {
1751 trace_e1000e_rx_interrupt_delayed(n);
1752 }
1753
1754 return retval;
1755 }
1756
1757 static inline bool
1758 e1000e_have_autoneg(E1000ECore *core)
1759 {
1760 return core->phy[0][MII_BMCR] & MII_BMCR_AUTOEN;
1761 }
1762
1763 static void e1000e_update_flowctl_status(E1000ECore *core)
1764 {
1765 if (e1000e_have_autoneg(core) &&
1766 core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP) {
1767 trace_e1000e_link_autoneg_flowctl(true);
1768 core->mac[CTRL] |= E1000_CTRL_TFCE | E1000_CTRL_RFCE;
1769 } else {
1770 trace_e1000e_link_autoneg_flowctl(false);
1771 }
1772 }
1773
1774 static inline void
1775 e1000e_link_down(E1000ECore *core)
1776 {
1777 e1000x_update_regs_on_link_down(core->mac, core->phy[0]);
1778 e1000e_update_flowctl_status(core);
1779 }
1780
1781 static inline void
1782 e1000e_set_phy_ctrl(E1000ECore *core, int index, uint16_t val)
1783 {
1784 /* bits 0-5 reserved; MII_BMCR_[ANRESTART,RESET] are self clearing */
1785 core->phy[0][MII_BMCR] = val & ~(0x3f |
1786 MII_BMCR_RESET |
1787 MII_BMCR_ANRESTART);
1788
1789 if ((val & MII_BMCR_ANRESTART) &&
1790 e1000e_have_autoneg(core)) {
1791 e1000x_restart_autoneg(core->mac, core->phy[0], core->autoneg_timer);
1792 }
1793 }
1794
1795 static void
1796 e1000e_set_phy_oem_bits(E1000ECore *core, int index, uint16_t val)
1797 {
1798 core->phy[0][PHY_OEM_BITS] = val & ~BIT(10);
1799
1800 if (val & BIT(10)) {
1801 e1000x_restart_autoneg(core->mac, core->phy[0], core->autoneg_timer);
1802 }
1803 }
1804
1805 static void
1806 e1000e_set_phy_page(E1000ECore *core, int index, uint16_t val)
1807 {
1808 core->phy[0][PHY_PAGE] = val & PHY_PAGE_RW_MASK;
1809 }
1810
1811 void
1812 e1000e_core_set_link_status(E1000ECore *core)
1813 {
1814 NetClientState *nc = qemu_get_queue(core->owner_nic);
1815 uint32_t old_status = core->mac[STATUS];
1816
1817 trace_e1000e_link_status_changed(nc->link_down ? false : true);
1818
1819 if (nc->link_down) {
1820 e1000x_update_regs_on_link_down(core->mac, core->phy[0]);
1821 } else {
1822 if (e1000e_have_autoneg(core) &&
1823 !(core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP)) {
1824 e1000x_restart_autoneg(core->mac, core->phy[0],
1825 core->autoneg_timer);
1826 } else {
1827 e1000x_update_regs_on_link_up(core->mac, core->phy[0]);
1828 e1000e_start_recv(core);
1829 }
1830 }
1831
1832 if (core->mac[STATUS] != old_status) {
1833 e1000e_set_interrupt_cause(core, E1000_ICR_LSC);
1834 }
1835 }
1836
1837 static void
1838 e1000e_set_ctrl(E1000ECore *core, int index, uint32_t val)
1839 {
1840 trace_e1000e_core_ctrl_write(index, val);
1841
1842 /* RST is self clearing */
1843 core->mac[CTRL] = val & ~E1000_CTRL_RST;
1844 core->mac[CTRL_DUP] = core->mac[CTRL];
1845
1846 trace_e1000e_link_set_params(
1847 !!(val & E1000_CTRL_ASDE),
1848 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT,
1849 !!(val & E1000_CTRL_FRCSPD),
1850 !!(val & E1000_CTRL_FRCDPX),
1851 !!(val & E1000_CTRL_RFCE),
1852 !!(val & E1000_CTRL_TFCE));
1853
1854 if (val & E1000_CTRL_RST) {
1855 trace_e1000e_core_ctrl_sw_reset();
1856 e1000e_reset(core, true);
1857 }
1858
1859 if (val & E1000_CTRL_PHY_RST) {
1860 trace_e1000e_core_ctrl_phy_reset();
1861 core->mac[STATUS] |= E1000_STATUS_PHYRA;
1862 }
1863 }
1864
1865 static void
1866 e1000e_set_rfctl(E1000ECore *core, int index, uint32_t val)
1867 {
1868 trace_e1000e_rx_set_rfctl(val);
1869
1870 if (!(val & E1000_RFCTL_ISCSI_DIS)) {
1871 trace_e1000e_wrn_iscsi_filtering_not_supported();
1872 }
1873
1874 if (!(val & E1000_RFCTL_NFSW_DIS)) {
1875 trace_e1000e_wrn_nfsw_filtering_not_supported();
1876 }
1877
1878 if (!(val & E1000_RFCTL_NFSR_DIS)) {
1879 trace_e1000e_wrn_nfsr_filtering_not_supported();
1880 }
1881
1882 core->mac[RFCTL] = val;
1883 }
1884
1885 static void
1886 e1000e_calc_per_desc_buf_size(E1000ECore *core)
1887 {
1888 int i;
1889 core->rx_desc_buf_size = 0;
1890
1891 for (i = 0; i < ARRAY_SIZE(core->rxbuf_sizes); i++) {
1892 core->rx_desc_buf_size += core->rxbuf_sizes[i];
1893 }
1894 }
1895
1896 static void
1897 e1000e_parse_rxbufsize(E1000ECore *core)
1898 {
1899 uint32_t rctl = core->mac[RCTL];
1900
1901 memset(core->rxbuf_sizes, 0, sizeof(core->rxbuf_sizes));
1902
1903 if (rctl & E1000_RCTL_DTYP_MASK) {
1904 uint32_t bsize;
1905
1906 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE0_MASK;
1907 core->rxbuf_sizes[0] = (bsize >> E1000_PSRCTL_BSIZE0_SHIFT) * 128;
1908
1909 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE1_MASK;
1910 core->rxbuf_sizes[1] = (bsize >> E1000_PSRCTL_BSIZE1_SHIFT) * 1024;
1911
1912 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE2_MASK;
1913 core->rxbuf_sizes[2] = (bsize >> E1000_PSRCTL_BSIZE2_SHIFT) * 1024;
1914
1915 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE3_MASK;
1916 core->rxbuf_sizes[3] = (bsize >> E1000_PSRCTL_BSIZE3_SHIFT) * 1024;
1917 } else if (rctl & E1000_RCTL_FLXBUF_MASK) {
1918 int flxbuf = rctl & E1000_RCTL_FLXBUF_MASK;
1919 core->rxbuf_sizes[0] = (flxbuf >> E1000_RCTL_FLXBUF_SHIFT) * 1024;
1920 } else {
1921 core->rxbuf_sizes[0] = e1000x_rxbufsize(rctl);
1922 }
1923
1924 trace_e1000e_rx_desc_buff_sizes(core->rxbuf_sizes[0], core->rxbuf_sizes[1],
1925 core->rxbuf_sizes[2], core->rxbuf_sizes[3]);
1926
1927 e1000e_calc_per_desc_buf_size(core);
1928 }
1929
1930 static void
1931 e1000e_calc_rxdesclen(E1000ECore *core)
1932 {
1933 if (e1000e_rx_use_legacy_descriptor(core)) {
1934 core->rx_desc_len = sizeof(struct e1000_rx_desc);
1935 } else {
1936 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) {
1937 core->rx_desc_len = sizeof(union e1000_rx_desc_packet_split);
1938 } else {
1939 core->rx_desc_len = sizeof(union e1000_rx_desc_extended);
1940 }
1941 }
1942 trace_e1000e_rx_desc_len(core->rx_desc_len);
1943 }
1944
1945 static void
1946 e1000e_set_rx_control(E1000ECore *core, int index, uint32_t val)
1947 {
1948 core->mac[RCTL] = val;
1949 trace_e1000e_rx_set_rctl(core->mac[RCTL]);
1950
1951 if (val & E1000_RCTL_EN) {
1952 e1000e_parse_rxbufsize(core);
1953 e1000e_calc_rxdesclen(core);
1954 core->rxbuf_min_shift = ((val / E1000_RCTL_RDMTS_QUAT) & 3) + 1 +
1955 E1000_RING_DESC_LEN_SHIFT;
1956
1957 e1000e_start_recv(core);
1958 }
1959 }
1960
1961 static
1962 void(*e1000e_phyreg_writeops[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE])
1963 (E1000ECore *, int, uint16_t) = {
1964 [0] = {
1965 [MII_BMCR] = e1000e_set_phy_ctrl,
1966 [PHY_PAGE] = e1000e_set_phy_page,
1967 [PHY_OEM_BITS] = e1000e_set_phy_oem_bits
1968 }
1969 };
1970
1971 static inline void
1972 e1000e_clear_ims_bits(E1000ECore *core, uint32_t bits)
1973 {
1974 trace_e1000e_irq_clear_ims(bits, core->mac[IMS], core->mac[IMS] & ~bits);
1975 core->mac[IMS] &= ~bits;
1976 }
1977
1978 static inline bool
1979 e1000e_postpone_interrupt(E1000IntrDelayTimer *timer)
1980 {
1981 if (timer->running) {
1982 trace_e1000e_irq_postponed_by_xitr(timer->delay_reg << 2);
1983
1984 return true;
1985 }
1986
1987 if (timer->core->mac[timer->delay_reg] != 0) {
1988 e1000e_intrmgr_rearm_timer(timer);
1989 }
1990
1991 return false;
1992 }
1993
1994 static inline bool
1995 e1000e_itr_should_postpone(E1000ECore *core)
1996 {
1997 return e1000e_postpone_interrupt(&core->itr);
1998 }
1999
2000 static inline bool
2001 e1000e_eitr_should_postpone(E1000ECore *core, int idx)
2002 {
2003 return e1000e_postpone_interrupt(&core->eitr[idx]);
2004 }
2005
2006 static void
2007 e1000e_msix_notify_one(E1000ECore *core, uint32_t cause, uint32_t int_cfg)
2008 {
2009 uint32_t effective_eiac;
2010
2011 if (E1000_IVAR_ENTRY_VALID(int_cfg)) {
2012 uint32_t vec = E1000_IVAR_ENTRY_VEC(int_cfg);
2013 if (vec < E1000E_MSIX_VEC_NUM) {
2014 if (!e1000e_eitr_should_postpone(core, vec)) {
2015 trace_e1000e_irq_msix_notify_vec(vec);
2016 msix_notify(core->owner, vec);
2017 }
2018 } else {
2019 trace_e1000e_wrn_msix_vec_wrong(cause, int_cfg);
2020 }
2021 } else {
2022 trace_e1000e_wrn_msix_invalid(cause, int_cfg);
2023 }
2024
2025 if (core->mac[CTRL_EXT] & E1000_CTRL_EXT_EIAME) {
2026 trace_e1000e_irq_iam_clear_eiame(core->mac[IAM], cause);
2027 core->mac[IAM] &= ~cause;
2028 }
2029
2030 trace_e1000e_irq_icr_clear_eiac(core->mac[ICR], core->mac[EIAC]);
2031
2032 effective_eiac = core->mac[EIAC] & cause;
2033
2034 core->mac[ICR] &= ~effective_eiac;
2035 core->msi_causes_pending &= ~effective_eiac;
2036
2037 if (!(core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) {
2038 core->mac[IMS] &= ~effective_eiac;
2039 }
2040 }
2041
2042 static void
2043 e1000e_msix_notify(E1000ECore *core, uint32_t causes)
2044 {
2045 if (causes & E1000_ICR_RXQ0) {
2046 e1000e_msix_notify_one(core, E1000_ICR_RXQ0,
2047 E1000_IVAR_RXQ0(core->mac[IVAR]));
2048 }
2049
2050 if (causes & E1000_ICR_RXQ1) {
2051 e1000e_msix_notify_one(core, E1000_ICR_RXQ1,
2052 E1000_IVAR_RXQ1(core->mac[IVAR]));
2053 }
2054
2055 if (causes & E1000_ICR_TXQ0) {
2056 e1000e_msix_notify_one(core, E1000_ICR_TXQ0,
2057 E1000_IVAR_TXQ0(core->mac[IVAR]));
2058 }
2059
2060 if (causes & E1000_ICR_TXQ1) {
2061 e1000e_msix_notify_one(core, E1000_ICR_TXQ1,
2062 E1000_IVAR_TXQ1(core->mac[IVAR]));
2063 }
2064
2065 if (causes & E1000_ICR_OTHER) {
2066 e1000e_msix_notify_one(core, E1000_ICR_OTHER,
2067 E1000_IVAR_OTHER(core->mac[IVAR]));
2068 }
2069 }
2070
2071 static void
2072 e1000e_msix_clear_one(E1000ECore *core, uint32_t cause, uint32_t int_cfg)
2073 {
2074 if (E1000_IVAR_ENTRY_VALID(int_cfg)) {
2075 uint32_t vec = E1000_IVAR_ENTRY_VEC(int_cfg);
2076 if (vec < E1000E_MSIX_VEC_NUM) {
2077 trace_e1000e_irq_msix_pending_clearing(cause, int_cfg, vec);
2078 msix_clr_pending(core->owner, vec);
2079 } else {
2080 trace_e1000e_wrn_msix_vec_wrong(cause, int_cfg);
2081 }
2082 } else {
2083 trace_e1000e_wrn_msix_invalid(cause, int_cfg);
2084 }
2085 }
2086
2087 static void
2088 e1000e_msix_clear(E1000ECore *core, uint32_t causes)
2089 {
2090 if (causes & E1000_ICR_RXQ0) {
2091 e1000e_msix_clear_one(core, E1000_ICR_RXQ0,
2092 E1000_IVAR_RXQ0(core->mac[IVAR]));
2093 }
2094
2095 if (causes & E1000_ICR_RXQ1) {
2096 e1000e_msix_clear_one(core, E1000_ICR_RXQ1,
2097 E1000_IVAR_RXQ1(core->mac[IVAR]));
2098 }
2099
2100 if (causes & E1000_ICR_TXQ0) {
2101 e1000e_msix_clear_one(core, E1000_ICR_TXQ0,
2102 E1000_IVAR_TXQ0(core->mac[IVAR]));
2103 }
2104
2105 if (causes & E1000_ICR_TXQ1) {
2106 e1000e_msix_clear_one(core, E1000_ICR_TXQ1,
2107 E1000_IVAR_TXQ1(core->mac[IVAR]));
2108 }
2109
2110 if (causes & E1000_ICR_OTHER) {
2111 e1000e_msix_clear_one(core, E1000_ICR_OTHER,
2112 E1000_IVAR_OTHER(core->mac[IVAR]));
2113 }
2114 }
2115
2116 static inline void
2117 e1000e_fix_icr_asserted(E1000ECore *core)
2118 {
2119 core->mac[ICR] &= ~E1000_ICR_ASSERTED;
2120 if (core->mac[ICR]) {
2121 core->mac[ICR] |= E1000_ICR_ASSERTED;
2122 }
2123
2124 trace_e1000e_irq_fix_icr_asserted(core->mac[ICR]);
2125 }
2126
2127 static void
2128 e1000e_send_msi(E1000ECore *core, bool msix)
2129 {
2130 uint32_t causes = core->mac[ICR] & core->mac[IMS] & ~E1000_ICR_ASSERTED;
2131
2132 core->msi_causes_pending &= causes;
2133 causes ^= core->msi_causes_pending;
2134 if (causes == 0) {
2135 return;
2136 }
2137 core->msi_causes_pending |= causes;
2138
2139 if (msix) {
2140 e1000e_msix_notify(core, causes);
2141 } else {
2142 if (!e1000e_itr_should_postpone(core)) {
2143 trace_e1000e_irq_msi_notify(causes);
2144 msi_notify(core->owner, 0);
2145 }
2146 }
2147 }
2148
2149 static void
2150 e1000e_update_interrupt_state(E1000ECore *core)
2151 {
2152 bool interrupts_pending;
2153 bool is_msix = msix_enabled(core->owner);
2154
2155 /* Set ICR[OTHER] for MSI-X */
2156 if (is_msix) {
2157 if (core->mac[ICR] & E1000_ICR_OTHER_CAUSES) {
2158 core->mac[ICR] |= E1000_ICR_OTHER;
2159 trace_e1000e_irq_add_msi_other(core->mac[ICR]);
2160 }
2161 }
2162
2163 e1000e_fix_icr_asserted(core);
2164
2165 /*
2166 * Make sure ICR and ICS registers have the same value.
2167 * The spec says that the ICS register is write-only. However in practice,
2168 * on real hardware ICS is readable, and for reads it has the same value as
2169 * ICR (except that ICS does not have the clear on read behaviour of ICR).
2170 *
2171 * The VxWorks PRO/1000 driver uses this behaviour.
2172 */
2173 core->mac[ICS] = core->mac[ICR];
2174
2175 interrupts_pending = (core->mac[IMS] & core->mac[ICR]) ? true : false;
2176 if (!interrupts_pending) {
2177 core->msi_causes_pending = 0;
2178 }
2179
2180 trace_e1000e_irq_pending_interrupts(core->mac[ICR] & core->mac[IMS],
2181 core->mac[ICR], core->mac[IMS]);
2182
2183 if (is_msix || msi_enabled(core->owner)) {
2184 if (interrupts_pending) {
2185 e1000e_send_msi(core, is_msix);
2186 }
2187 } else {
2188 if (interrupts_pending) {
2189 if (!e1000e_itr_should_postpone(core)) {
2190 e1000e_raise_legacy_irq(core);
2191 }
2192 } else {
2193 e1000e_lower_legacy_irq(core);
2194 }
2195 }
2196 }
2197
2198 static void
2199 e1000e_set_interrupt_cause(E1000ECore *core, uint32_t val)
2200 {
2201 trace_e1000e_irq_set_cause_entry(val, core->mac[ICR]);
2202
2203 val |= e1000e_intmgr_collect_delayed_causes(core);
2204 core->mac[ICR] |= val;
2205
2206 trace_e1000e_irq_set_cause_exit(val, core->mac[ICR]);
2207
2208 e1000e_update_interrupt_state(core);
2209 }
2210
2211 static inline void
2212 e1000e_autoneg_timer(void *opaque)
2213 {
2214 E1000ECore *core = opaque;
2215 if (!qemu_get_queue(core->owner_nic)->link_down) {
2216 e1000x_update_regs_on_autoneg_done(core->mac, core->phy[0]);
2217 e1000e_start_recv(core);
2218
2219 e1000e_update_flowctl_status(core);
2220 /* signal link status change to the guest */
2221 e1000e_set_interrupt_cause(core, E1000_ICR_LSC);
2222 }
2223 }
2224
2225 static inline uint16_t
2226 e1000e_get_reg_index_with_offset(const uint16_t *mac_reg_access, hwaddr addr)
2227 {
2228 uint16_t index = (addr & 0x1ffff) >> 2;
2229 return index + (mac_reg_access[index] & 0xfffe);
2230 }
2231
2232 static const char e1000e_phy_regcap[E1000E_PHY_PAGES][0x20] = {
2233 [0] = {
2234 [MII_BMCR] = PHY_ANYPAGE | PHY_RW,
2235 [MII_BMSR] = PHY_ANYPAGE | PHY_R,
2236 [MII_PHYID1] = PHY_ANYPAGE | PHY_R,
2237 [MII_PHYID2] = PHY_ANYPAGE | PHY_R,
2238 [MII_ANAR] = PHY_ANYPAGE | PHY_RW,
2239 [MII_ANLPAR] = PHY_ANYPAGE | PHY_R,
2240 [MII_ANER] = PHY_ANYPAGE | PHY_R,
2241 [MII_ANNP] = PHY_ANYPAGE | PHY_RW,
2242 [MII_ANLPRNP] = PHY_ANYPAGE | PHY_R,
2243 [MII_CTRL1000] = PHY_ANYPAGE | PHY_RW,
2244 [MII_STAT1000] = PHY_ANYPAGE | PHY_R,
2245 [MII_EXTSTAT] = PHY_ANYPAGE | PHY_R,
2246 [PHY_PAGE] = PHY_ANYPAGE | PHY_RW,
2247
2248 [PHY_COPPER_CTRL1] = PHY_RW,
2249 [PHY_COPPER_STAT1] = PHY_R,
2250 [PHY_COPPER_CTRL3] = PHY_RW,
2251 [PHY_RX_ERR_CNTR] = PHY_R,
2252 [PHY_OEM_BITS] = PHY_RW,
2253 [PHY_BIAS_1] = PHY_RW,
2254 [PHY_BIAS_2] = PHY_RW,
2255 [PHY_COPPER_INT_ENABLE] = PHY_RW,
2256 [PHY_COPPER_STAT2] = PHY_R,
2257 [PHY_COPPER_CTRL2] = PHY_RW
2258 },
2259 [2] = {
2260 [PHY_MAC_CTRL1] = PHY_RW,
2261 [PHY_MAC_INT_ENABLE] = PHY_RW,
2262 [PHY_MAC_STAT] = PHY_R,
2263 [PHY_MAC_CTRL2] = PHY_RW
2264 },
2265 [3] = {
2266 [PHY_LED_03_FUNC_CTRL1] = PHY_RW,
2267 [PHY_LED_03_POL_CTRL] = PHY_RW,
2268 [PHY_LED_TIMER_CTRL] = PHY_RW,
2269 [PHY_LED_45_CTRL] = PHY_RW
2270 },
2271 [5] = {
2272 [PHY_1000T_SKEW] = PHY_R,
2273 [PHY_1000T_SWAP] = PHY_R
2274 },
2275 [6] = {
2276 [PHY_CRC_COUNTERS] = PHY_R
2277 }
2278 };
2279
2280 static bool
2281 e1000e_phy_reg_check_cap(E1000ECore *core, uint32_t addr,
2282 char cap, uint8_t *page)
2283 {
2284 *page =
2285 (e1000e_phy_regcap[0][addr] & PHY_ANYPAGE) ? 0
2286 : core->phy[0][PHY_PAGE];
2287
2288 if (*page >= E1000E_PHY_PAGES) {
2289 return false;
2290 }
2291
2292 return e1000e_phy_regcap[*page][addr] & cap;
2293 }
2294
2295 static void
2296 e1000e_phy_reg_write(E1000ECore *core, uint8_t page,
2297 uint32_t addr, uint16_t data)
2298 {
2299 assert(page < E1000E_PHY_PAGES);
2300 assert(addr < E1000E_PHY_PAGE_SIZE);
2301
2302 if (e1000e_phyreg_writeops[page][addr]) {
2303 e1000e_phyreg_writeops[page][addr](core, addr, data);
2304 } else {
2305 core->phy[page][addr] = data;
2306 }
2307 }
2308
2309 static void
2310 e1000e_set_mdic(E1000ECore *core, int index, uint32_t val)
2311 {
2312 uint32_t data = val & E1000_MDIC_DATA_MASK;
2313 uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
2314 uint8_t page;
2315
2316 if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) { /* phy # */
2317 val = core->mac[MDIC] | E1000_MDIC_ERROR;
2318 } else if (val & E1000_MDIC_OP_READ) {
2319 if (!e1000e_phy_reg_check_cap(core, addr, PHY_R, &page)) {
2320 trace_e1000e_core_mdic_read_unhandled(page, addr);
2321 val |= E1000_MDIC_ERROR;
2322 } else {
2323 val = (val ^ data) | core->phy[page][addr];
2324 trace_e1000e_core_mdic_read(page, addr, val);
2325 }
2326 } else if (val & E1000_MDIC_OP_WRITE) {
2327 if (!e1000e_phy_reg_check_cap(core, addr, PHY_W, &page)) {
2328 trace_e1000e_core_mdic_write_unhandled(page, addr);
2329 val |= E1000_MDIC_ERROR;
2330 } else {
2331 trace_e1000e_core_mdic_write(page, addr, data);
2332 e1000e_phy_reg_write(core, page, addr, data);
2333 }
2334 }
2335 core->mac[MDIC] = val | E1000_MDIC_READY;
2336
2337 if (val & E1000_MDIC_INT_EN) {
2338 e1000e_set_interrupt_cause(core, E1000_ICR_MDAC);
2339 }
2340 }
2341
2342 static void
2343 e1000e_set_rdt(E1000ECore *core, int index, uint32_t val)
2344 {
2345 core->mac[index] = val & 0xffff;
2346 trace_e1000e_rx_set_rdt(e1000e_mq_queue_idx(RDT0, index), val);
2347 e1000e_start_recv(core);
2348 }
2349
2350 static void
2351 e1000e_set_status(E1000ECore *core, int index, uint32_t val)
2352 {
2353 if ((val & E1000_STATUS_PHYRA) == 0) {
2354 core->mac[index] &= ~E1000_STATUS_PHYRA;
2355 }
2356 }
2357
2358 static void
2359 e1000e_set_ctrlext(E1000ECore *core, int index, uint32_t val)
2360 {
2361 trace_e1000e_link_set_ext_params(!!(val & E1000_CTRL_EXT_ASDCHK),
2362 !!(val & E1000_CTRL_EXT_SPD_BYPS));
2363
2364 /* Zero self-clearing bits */
2365 val &= ~(E1000_CTRL_EXT_ASDCHK | E1000_CTRL_EXT_EE_RST);
2366 core->mac[CTRL_EXT] = val;
2367 }
2368
2369 static void
2370 e1000e_set_pbaclr(E1000ECore *core, int index, uint32_t val)
2371 {
2372 int i;
2373
2374 core->mac[PBACLR] = val & E1000_PBACLR_VALID_MASK;
2375
2376 if (!msix_enabled(core->owner)) {
2377 return;
2378 }
2379
2380 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
2381 if (core->mac[PBACLR] & BIT(i)) {
2382 msix_clr_pending(core->owner, i);
2383 }
2384 }
2385 }
2386
2387 static void
2388 e1000e_set_fcrth(E1000ECore *core, int index, uint32_t val)
2389 {
2390 core->mac[FCRTH] = val & 0xFFF8;
2391 }
2392
2393 static void
2394 e1000e_set_fcrtl(E1000ECore *core, int index, uint32_t val)
2395 {
2396 core->mac[FCRTL] = val & 0x8000FFF8;
2397 }
2398
2399 #define E1000E_LOW_BITS_SET_FUNC(num) \
2400 static void \
2401 e1000e_set_##num##bit(E1000ECore *core, int index, uint32_t val) \
2402 { \
2403 core->mac[index] = val & (BIT(num) - 1); \
2404 }
2405
2406 E1000E_LOW_BITS_SET_FUNC(4)
2407 E1000E_LOW_BITS_SET_FUNC(6)
2408 E1000E_LOW_BITS_SET_FUNC(11)
2409 E1000E_LOW_BITS_SET_FUNC(12)
2410 E1000E_LOW_BITS_SET_FUNC(13)
2411 E1000E_LOW_BITS_SET_FUNC(16)
2412
2413 static void
2414 e1000e_set_vet(E1000ECore *core, int index, uint32_t val)
2415 {
2416 core->mac[VET] = val & 0xffff;
2417 trace_e1000e_vlan_vet(core->mac[VET]);
2418 }
2419
2420 static void
2421 e1000e_set_dlen(E1000ECore *core, int index, uint32_t val)
2422 {
2423 core->mac[index] = val & E1000_XDLEN_MASK;
2424 }
2425
2426 static void
2427 e1000e_set_dbal(E1000ECore *core, int index, uint32_t val)
2428 {
2429 core->mac[index] = val & E1000_XDBAL_MASK;
2430 }
2431
2432 static void
2433 e1000e_set_tctl(E1000ECore *core, int index, uint32_t val)
2434 {
2435 E1000E_TxRing txr;
2436 core->mac[index] = val;
2437
2438 if (core->mac[TARC0] & E1000_TARC_ENABLE) {
2439 e1000e_tx_ring_init(core, &txr, 0);
2440 e1000e_start_xmit(core, &txr);
2441 }
2442
2443 if (core->mac[TARC1] & E1000_TARC_ENABLE) {
2444 e1000e_tx_ring_init(core, &txr, 1);
2445 e1000e_start_xmit(core, &txr);
2446 }
2447 }
2448
2449 static void
2450 e1000e_set_tdt(E1000ECore *core, int index, uint32_t val)
2451 {
2452 E1000E_TxRing txr;
2453 int qidx = e1000e_mq_queue_idx(TDT, index);
2454 uint32_t tarc_reg = (qidx == 0) ? TARC0 : TARC1;
2455
2456 core->mac[index] = val & 0xffff;
2457
2458 if (core->mac[tarc_reg] & E1000_TARC_ENABLE) {
2459 e1000e_tx_ring_init(core, &txr, qidx);
2460 e1000e_start_xmit(core, &txr);
2461 }
2462 }
2463
2464 static void
2465 e1000e_set_ics(E1000ECore *core, int index, uint32_t val)
2466 {
2467 trace_e1000e_irq_write_ics(val);
2468 e1000e_set_interrupt_cause(core, val);
2469 }
2470
2471 static void
2472 e1000e_set_icr(E1000ECore *core, int index, uint32_t val)
2473 {
2474 uint32_t icr = 0;
2475 if ((core->mac[ICR] & E1000_ICR_ASSERTED) &&
2476 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) {
2477 trace_e1000e_irq_icr_process_iame();
2478 e1000e_clear_ims_bits(core, core->mac[IAM]);
2479 }
2480
2481 icr = core->mac[ICR] & ~val;
2482 /*
2483 * Windows driver expects that the "receive overrun" bit and other
2484 * ones to be cleared when the "Other" bit (#24) is cleared.
2485 */
2486 icr = (val & E1000_ICR_OTHER) ? (icr & ~E1000_ICR_OTHER_CAUSES) : icr;
2487 trace_e1000e_irq_icr_write(val, core->mac[ICR], icr);
2488 core->mac[ICR] = icr;
2489 e1000e_update_interrupt_state(core);
2490 }
2491
2492 static void
2493 e1000e_set_imc(E1000ECore *core, int index, uint32_t val)
2494 {
2495 trace_e1000e_irq_ims_clear_set_imc(val);
2496 e1000e_clear_ims_bits(core, val);
2497 e1000e_update_interrupt_state(core);
2498 }
2499
2500 static void
2501 e1000e_set_ims(E1000ECore *core, int index, uint32_t val)
2502 {
2503 static const uint32_t ims_ext_mask =
2504 E1000_IMS_RXQ0 | E1000_IMS_RXQ1 |
2505 E1000_IMS_TXQ0 | E1000_IMS_TXQ1 |
2506 E1000_IMS_OTHER;
2507
2508 static const uint32_t ims_valid_mask =
2509 E1000_IMS_TXDW | E1000_IMS_TXQE | E1000_IMS_LSC |
2510 E1000_IMS_RXDMT0 | E1000_IMS_RXO | E1000_IMS_RXT0 |
2511 E1000_IMS_MDAC | E1000_IMS_TXD_LOW | E1000_IMS_SRPD |
2512 E1000_IMS_ACK | E1000_IMS_MNG | E1000_IMS_RXQ0 |
2513 E1000_IMS_RXQ1 | E1000_IMS_TXQ0 | E1000_IMS_TXQ1 |
2514 E1000_IMS_OTHER;
2515
2516 uint32_t valid_val = val & ims_valid_mask;
2517
2518 trace_e1000e_irq_set_ims(val, core->mac[IMS], core->mac[IMS] | valid_val);
2519 core->mac[IMS] |= valid_val;
2520
2521 if ((valid_val & ims_ext_mask) &&
2522 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_PBA_CLR) &&
2523 msix_enabled(core->owner)) {
2524 e1000e_msix_clear(core, valid_val);
2525 }
2526
2527 if ((valid_val == ims_valid_mask) &&
2528 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_INT_TIMERS_CLEAR_ENA)) {
2529 trace_e1000e_irq_fire_all_timers(val);
2530 e1000e_intrmgr_fire_all_timers(core);
2531 }
2532
2533 e1000e_update_interrupt_state(core);
2534 }
2535
2536 static void
2537 e1000e_set_rdtr(E1000ECore *core, int index, uint32_t val)
2538 {
2539 e1000e_set_16bit(core, index, val);
2540
2541 if ((val & E1000_RDTR_FPD) && (core->rdtr.running)) {
2542 trace_e1000e_irq_rdtr_fpd_running();
2543 e1000e_intrmgr_fire_delayed_interrupts(core);
2544 } else {
2545 trace_e1000e_irq_rdtr_fpd_not_running();
2546 }
2547 }
2548
2549 static void
2550 e1000e_set_tidv(E1000ECore *core, int index, uint32_t val)
2551 {
2552 e1000e_set_16bit(core, index, val);
2553
2554 if ((val & E1000_TIDV_FPD) && (core->tidv.running)) {
2555 trace_e1000e_irq_tidv_fpd_running();
2556 e1000e_intrmgr_fire_delayed_interrupts(core);
2557 } else {
2558 trace_e1000e_irq_tidv_fpd_not_running();
2559 }
2560 }
2561
2562 static uint32_t
2563 e1000e_mac_readreg(E1000ECore *core, int index)
2564 {
2565 return core->mac[index];
2566 }
2567
2568 static uint32_t
2569 e1000e_mac_ics_read(E1000ECore *core, int index)
2570 {
2571 trace_e1000e_irq_read_ics(core->mac[ICS]);
2572 return core->mac[ICS];
2573 }
2574
2575 static uint32_t
2576 e1000e_mac_ims_read(E1000ECore *core, int index)
2577 {
2578 trace_e1000e_irq_read_ims(core->mac[IMS]);
2579 return core->mac[IMS];
2580 }
2581
2582 static uint32_t
2583 e1000e_mac_swsm_read(E1000ECore *core, int index)
2584 {
2585 uint32_t val = core->mac[SWSM];
2586 core->mac[SWSM] = val | E1000_SWSM_SMBI;
2587 return val;
2588 }
2589
2590 static uint32_t
2591 e1000e_mac_itr_read(E1000ECore *core, int index)
2592 {
2593 return core->itr_guest_value;
2594 }
2595
2596 static uint32_t
2597 e1000e_mac_eitr_read(E1000ECore *core, int index)
2598 {
2599 return core->eitr_guest_value[index - EITR];
2600 }
2601
2602 static uint32_t
2603 e1000e_mac_icr_read(E1000ECore *core, int index)
2604 {
2605 uint32_t ret = core->mac[ICR];
2606 trace_e1000e_irq_icr_read_entry(ret);
2607
2608 if (core->mac[IMS] == 0) {
2609 trace_e1000e_irq_icr_clear_zero_ims();
2610 core->mac[ICR] = 0;
2611 }
2612
2613 if (!msix_enabled(core->owner)) {
2614 trace_e1000e_irq_icr_clear_nonmsix_icr_read();
2615 core->mac[ICR] = 0;
2616 }
2617
2618 if ((core->mac[ICR] & E1000_ICR_ASSERTED) &&
2619 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) {
2620 trace_e1000e_irq_icr_clear_iame();
2621 core->mac[ICR] = 0;
2622 trace_e1000e_irq_icr_process_iame();
2623 e1000e_clear_ims_bits(core, core->mac[IAM]);
2624 }
2625
2626 trace_e1000e_irq_icr_read_exit(core->mac[ICR]);
2627 e1000e_update_interrupt_state(core);
2628 return ret;
2629 }
2630
2631 static uint32_t
2632 e1000e_mac_read_clr4(E1000ECore *core, int index)
2633 {
2634 uint32_t ret = core->mac[index];
2635
2636 core->mac[index] = 0;
2637 return ret;
2638 }
2639
2640 static uint32_t
2641 e1000e_mac_read_clr8(E1000ECore *core, int index)
2642 {
2643 uint32_t ret = core->mac[index];
2644
2645 core->mac[index] = 0;
2646 core->mac[index - 1] = 0;
2647 return ret;
2648 }
2649
2650 static uint32_t
2651 e1000e_get_ctrl(E1000ECore *core, int index)
2652 {
2653 uint32_t val = core->mac[CTRL];
2654
2655 trace_e1000e_link_read_params(
2656 !!(val & E1000_CTRL_ASDE),
2657 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT,
2658 !!(val & E1000_CTRL_FRCSPD),
2659 !!(val & E1000_CTRL_FRCDPX),
2660 !!(val & E1000_CTRL_RFCE),
2661 !!(val & E1000_CTRL_TFCE));
2662
2663 return val;
2664 }
2665
2666 static uint32_t
2667 e1000e_get_status(E1000ECore *core, int index)
2668 {
2669 uint32_t res = core->mac[STATUS];
2670
2671 if (!(core->mac[CTRL] & E1000_CTRL_GIO_MASTER_DISABLE)) {
2672 res |= E1000_STATUS_GIO_MASTER_ENABLE;
2673 }
2674
2675 if (core->mac[CTRL] & E1000_CTRL_FRCDPX) {
2676 res |= (core->mac[CTRL] & E1000_CTRL_FD) ? E1000_STATUS_FD : 0;
2677 } else {
2678 res |= E1000_STATUS_FD;
2679 }
2680
2681 if ((core->mac[CTRL] & E1000_CTRL_FRCSPD) ||
2682 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_SPD_BYPS)) {
2683 switch (core->mac[CTRL] & E1000_CTRL_SPD_SEL) {
2684 case E1000_CTRL_SPD_10:
2685 res |= E1000_STATUS_SPEED_10;
2686 break;
2687 case E1000_CTRL_SPD_100:
2688 res |= E1000_STATUS_SPEED_100;
2689 break;
2690 case E1000_CTRL_SPD_1000:
2691 default:
2692 res |= E1000_STATUS_SPEED_1000;
2693 break;
2694 }
2695 } else {
2696 res |= E1000_STATUS_SPEED_1000;
2697 }
2698
2699 trace_e1000e_link_status(
2700 !!(res & E1000_STATUS_LU),
2701 !!(res & E1000_STATUS_FD),
2702 (res & E1000_STATUS_SPEED_MASK) >> E1000_STATUS_SPEED_SHIFT,
2703 (res & E1000_STATUS_ASDV) >> E1000_STATUS_ASDV_SHIFT);
2704
2705 return res;
2706 }
2707
2708 static uint32_t
2709 e1000e_get_tarc(E1000ECore *core, int index)
2710 {
2711 return core->mac[index] & ((BIT(11) - 1) |
2712 BIT(27) |
2713 BIT(28) |
2714 BIT(29) |
2715 BIT(30));
2716 }
2717
2718 static void
2719 e1000e_mac_writereg(E1000ECore *core, int index, uint32_t val)
2720 {
2721 core->mac[index] = val;
2722 }
2723
2724 static void
2725 e1000e_mac_setmacaddr(E1000ECore *core, int index, uint32_t val)
2726 {
2727 uint32_t macaddr[2];
2728
2729 core->mac[index] = val;
2730
2731 macaddr[0] = cpu_to_le32(core->mac[RA]);
2732 macaddr[1] = cpu_to_le32(core->mac[RA + 1]);
2733 qemu_format_nic_info_str(qemu_get_queue(core->owner_nic),
2734 (uint8_t *) macaddr);
2735
2736 trace_e1000e_mac_set_sw(MAC_ARG(macaddr));
2737 }
2738
2739 static void
2740 e1000e_set_eecd(E1000ECore *core, int index, uint32_t val)
2741 {
2742 static const uint32_t ro_bits = E1000_EECD_PRES |
2743 E1000_EECD_AUTO_RD |
2744 E1000_EECD_SIZE_EX_MASK;
2745
2746 core->mac[EECD] = (core->mac[EECD] & ro_bits) | (val & ~ro_bits);
2747 }
2748
2749 static void
2750 e1000e_set_eerd(E1000ECore *core, int index, uint32_t val)
2751 {
2752 uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK;
2753 uint32_t flags = 0;
2754 uint32_t data = 0;
2755
2756 if ((addr < E1000E_EEPROM_SIZE) && (val & E1000_EERW_START)) {
2757 data = core->eeprom[addr];
2758 flags = E1000_EERW_DONE;
2759 }
2760
2761 core->mac[EERD] = flags |
2762 (addr << E1000_EERW_ADDR_SHIFT) |
2763 (data << E1000_EERW_DATA_SHIFT);
2764 }
2765
2766 static void
2767 e1000e_set_eewr(E1000ECore *core, int index, uint32_t val)
2768 {
2769 uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK;
2770 uint32_t data = (val >> E1000_EERW_DATA_SHIFT) & E1000_EERW_DATA_MASK;
2771 uint32_t flags = 0;
2772
2773 if ((addr < E1000E_EEPROM_SIZE) && (val & E1000_EERW_START)) {
2774 core->eeprom[addr] = data;
2775 flags = E1000_EERW_DONE;
2776 }
2777
2778 core->mac[EERD] = flags |
2779 (addr << E1000_EERW_ADDR_SHIFT) |
2780 (data << E1000_EERW_DATA_SHIFT);
2781 }
2782
2783 static void
2784 e1000e_set_rxdctl(E1000ECore *core, int index, uint32_t val)
2785 {
2786 core->mac[RXDCTL] = core->mac[RXDCTL1] = val;
2787 }
2788
2789 static void
2790 e1000e_set_itr(E1000ECore *core, int index, uint32_t val)
2791 {
2792 uint32_t interval = val & 0xffff;
2793
2794 trace_e1000e_irq_itr_set(val);
2795
2796 core->itr_guest_value = interval;
2797 core->mac[index] = MAX(interval, E1000E_MIN_XITR);
2798 }
2799
2800 static void
2801 e1000e_set_eitr(E1000ECore *core, int index, uint32_t val)
2802 {
2803 uint32_t interval = val & 0xffff;
2804 uint32_t eitr_num = index - EITR;
2805
2806 trace_e1000e_irq_eitr_set(eitr_num, val);
2807
2808 core->eitr_guest_value[eitr_num] = interval;
2809 core->mac[index] = MAX(interval, E1000E_MIN_XITR);
2810 }
2811
2812 static void
2813 e1000e_set_psrctl(E1000ECore *core, int index, uint32_t val)
2814 {
2815 if (core->mac[RCTL] & E1000_RCTL_DTYP_MASK) {
2816
2817 if ((val & E1000_PSRCTL_BSIZE0_MASK) == 0) {
2818 qemu_log_mask(LOG_GUEST_ERROR,
2819 "e1000e: PSRCTL.BSIZE0 cannot be zero");
2820 return;
2821 }
2822
2823 if ((val & E1000_PSRCTL_BSIZE1_MASK) == 0) {
2824 qemu_log_mask(LOG_GUEST_ERROR,
2825 "e1000e: PSRCTL.BSIZE1 cannot be zero");
2826 return;
2827 }
2828 }
2829
2830 core->mac[PSRCTL] = val;
2831 }
2832
2833 static void
2834 e1000e_update_rx_offloads(E1000ECore *core)
2835 {
2836 int cso_state = e1000e_rx_l4_cso_enabled(core);
2837
2838 trace_e1000e_rx_set_cso(cso_state);
2839
2840 if (core->has_vnet) {
2841 qemu_set_offload(qemu_get_queue(core->owner_nic)->peer,
2842 cso_state, 0, 0, 0, 0);
2843 }
2844 }
2845
2846 static void
2847 e1000e_set_rxcsum(E1000ECore *core, int index, uint32_t val)
2848 {
2849 core->mac[RXCSUM] = val;
2850 e1000e_update_rx_offloads(core);
2851 }
2852
2853 static void
2854 e1000e_set_gcr(E1000ECore *core, int index, uint32_t val)
2855 {
2856 uint32_t ro_bits = core->mac[GCR] & E1000_GCR_RO_BITS;
2857 core->mac[GCR] = (val & ~E1000_GCR_RO_BITS) | ro_bits;
2858 }
2859
2860 static uint32_t e1000e_get_systiml(E1000ECore *core, int index)
2861 {
2862 e1000x_timestamp(core->mac, core->timadj, SYSTIML, SYSTIMH);
2863 return core->mac[SYSTIML];
2864 }
2865
2866 static uint32_t e1000e_get_rxsatrh(E1000ECore *core, int index)
2867 {
2868 core->mac[TSYNCRXCTL] &= ~E1000_TSYNCRXCTL_VALID;
2869 return core->mac[RXSATRH];
2870 }
2871
2872 static uint32_t e1000e_get_txstmph(E1000ECore *core, int index)
2873 {
2874 core->mac[TSYNCTXCTL] &= ~E1000_TSYNCTXCTL_VALID;
2875 return core->mac[TXSTMPH];
2876 }
2877
2878 static void e1000e_set_timinca(E1000ECore *core, int index, uint32_t val)
2879 {
2880 e1000x_set_timinca(core->mac, &core->timadj, val);
2881 }
2882
2883 static void e1000e_set_timadjh(E1000ECore *core, int index, uint32_t val)
2884 {
2885 core->mac[TIMADJH] = val;
2886 core->timadj += core->mac[TIMADJL] | ((int64_t)core->mac[TIMADJH] << 32);
2887 }
2888
2889 #define e1000e_getreg(x) [x] = e1000e_mac_readreg
2890 typedef uint32_t (*readops)(E1000ECore *, int);
2891 static const readops e1000e_macreg_readops[] = {
2892 e1000e_getreg(PBA),
2893 e1000e_getreg(WUFC),
2894 e1000e_getreg(MANC),
2895 e1000e_getreg(TOTL),
2896 e1000e_getreg(RDT0),
2897 e1000e_getreg(RDBAH0),
2898 e1000e_getreg(TDBAL1),
2899 e1000e_getreg(RDLEN0),
2900 e1000e_getreg(RDH1),
2901 e1000e_getreg(LATECOL),
2902 e1000e_getreg(SEQEC),
2903 e1000e_getreg(XONTXC),
2904 e1000e_getreg(AIT),
2905 e1000e_getreg(TDFH),
2906 e1000e_getreg(TDFT),
2907 e1000e_getreg(TDFHS),
2908 e1000e_getreg(TDFTS),
2909 e1000e_getreg(TDFPC),
2910 e1000e_getreg(WUS),
2911 e1000e_getreg(PBS),
2912 e1000e_getreg(RDFH),
2913 e1000e_getreg(RDFT),
2914 e1000e_getreg(RDFHS),
2915 e1000e_getreg(RDFTS),
2916 e1000e_getreg(RDFPC),
2917 e1000e_getreg(GORCL),
2918 e1000e_getreg(MGTPRC),
2919 e1000e_getreg(EERD),
2920 e1000e_getreg(EIAC),
2921 e1000e_getreg(PSRCTL),
2922 e1000e_getreg(MANC2H),
2923 e1000e_getreg(RXCSUM),
2924 e1000e_getreg(GSCL_3),
2925 e1000e_getreg(GSCN_2),
2926 e1000e_getreg(RSRPD),
2927 e1000e_getreg(RDBAL1),
2928 e1000e_getreg(FCAH),
2929 e1000e_getreg(FCRTH),
2930 e1000e_getreg(FLOP),
2931 e1000e_getreg(FLASHT),
2932 e1000e_getreg(RXSTMPH),
2933 e1000e_getreg(TXSTMPL),
2934 e1000e_getreg(TIMADJL),
2935 e1000e_getreg(TXDCTL),
2936 e1000e_getreg(RDH0),
2937 e1000e_getreg(TDT1),
2938 e1000e_getreg(TNCRS),
2939 e1000e_getreg(RJC),
2940 e1000e_getreg(IAM),
2941 e1000e_getreg(GSCL_2),
2942 e1000e_getreg(RDBAH1),
2943 e1000e_getreg(FLSWDATA),
2944 e1000e_getreg(TIPG),
2945 e1000e_getreg(FLMNGCTL),
2946 e1000e_getreg(FLMNGCNT),
2947 e1000e_getreg(TSYNCTXCTL),
2948 e1000e_getreg(EXTCNF_SIZE),
2949 e1000e_getreg(EXTCNF_CTRL),
2950 e1000e_getreg(EEMNGDATA),
2951 e1000e_getreg(CTRL_EXT),
2952 e1000e_getreg(SYSTIMH),
2953 e1000e_getreg(EEMNGCTL),
2954 e1000e_getreg(FLMNGDATA),
2955 e1000e_getreg(TSYNCRXCTL),
2956 e1000e_getreg(TDH),
2957 e1000e_getreg(LEDCTL),
2958 e1000e_getreg(TCTL),
2959 e1000e_getreg(TDBAL),
2960 e1000e_getreg(TDLEN),
2961 e1000e_getreg(TDH1),
2962 e1000e_getreg(RADV),
2963 e1000e_getreg(ECOL),
2964 e1000e_getreg(DC),
2965 e1000e_getreg(RLEC),
2966 e1000e_getreg(XOFFTXC),
2967 e1000e_getreg(RFC),
2968 e1000e_getreg(RNBC),
2969 e1000e_getreg(MGTPTC),
2970 e1000e_getreg(TIMINCA),
2971 e1000e_getreg(RXCFGL),
2972 e1000e_getreg(MFUTP01),
2973 e1000e_getreg(FACTPS),
2974 e1000e_getreg(GSCL_1),
2975 e1000e_getreg(GSCN_0),
2976 e1000e_getreg(GCR2),
2977 e1000e_getreg(RDT1),
2978 e1000e_getreg(PBACLR),
2979 e1000e_getreg(FCTTV),
2980 e1000e_getreg(EEWR),
2981 e1000e_getreg(FLSWCTL),
2982 e1000e_getreg(RXDCTL1),
2983 e1000e_getreg(RXSATRL),
2984 e1000e_getreg(RXUDP),
2985 e1000e_getreg(TORL),
2986 e1000e_getreg(TDLEN1),
2987 e1000e_getreg(MCC),
2988 e1000e_getreg(WUC),
2989 e1000e_getreg(EECD),
2990 e1000e_getreg(MFUTP23),
2991 e1000e_getreg(RAID),
2992 e1000e_getreg(FCRTV),
2993 e1000e_getreg(TXDCTL1),
2994 e1000e_getreg(RCTL),
2995 e1000e_getreg(TDT),
2996 e1000e_getreg(MDIC),
2997 e1000e_getreg(FCRUC),
2998 e1000e_getreg(VET),
2999 e1000e_getreg(RDBAL0),
3000 e1000e_getreg(TDBAH1),
3001 e1000e_getreg(RDTR),
3002 e1000e_getreg(SCC),
3003 e1000e_getreg(COLC),
3004 e1000e_getreg(CEXTERR),
3005 e1000e_getreg(XOFFRXC),
3006 e1000e_getreg(IPAV),
3007 e1000e_getreg(GOTCL),
3008 e1000e_getreg(MGTPDC),
3009 e1000e_getreg(GCR),
3010 e1000e_getreg(IVAR),
3011 e1000e_getreg(POEMB),
3012 e1000e_getreg(MFVAL),
3013 e1000e_getreg(FUNCTAG),
3014 e1000e_getreg(GSCL_4),
3015 e1000e_getreg(GSCN_3),
3016 e1000e_getreg(MRQC),
3017 e1000e_getreg(RDLEN1),
3018 e1000e_getreg(FCT),
3019 e1000e_getreg(FLA),
3020 e1000e_getreg(FLOL),
3021 e1000e_getreg(RXDCTL),
3022 e1000e_getreg(RXSTMPL),
3023 e1000e_getreg(TIMADJH),
3024 e1000e_getreg(FCRTL),
3025 e1000e_getreg(TDBAH),
3026 e1000e_getreg(TADV),
3027 e1000e_getreg(XONRXC),
3028 e1000e_getreg(TSCTFC),
3029 e1000e_getreg(RFCTL),
3030 e1000e_getreg(GSCN_1),
3031 e1000e_getreg(FCAL),
3032 e1000e_getreg(FLSWCNT),
3033
3034 [TOTH] = e1000e_mac_read_clr8,
3035 [GOTCH] = e1000e_mac_read_clr8,
3036 [PRC64] = e1000e_mac_read_clr4,
3037 [PRC255] = e1000e_mac_read_clr4,
3038 [PRC1023] = e1000e_mac_read_clr4,
3039 [PTC64] = e1000e_mac_read_clr4,
3040 [PTC255] = e1000e_mac_read_clr4,
3041 [PTC1023] = e1000e_mac_read_clr4,
3042 [GPRC] = e1000e_mac_read_clr4,
3043 [TPT] = e1000e_mac_read_clr4,
3044 [RUC] = e1000e_mac_read_clr4,
3045 [BPRC] = e1000e_mac_read_clr4,
3046 [MPTC] = e1000e_mac_read_clr4,
3047 [IAC] = e1000e_mac_read_clr4,
3048 [ICR] = e1000e_mac_icr_read,
3049 [STATUS] = e1000e_get_status,
3050 [TARC0] = e1000e_get_tarc,
3051 [ICS] = e1000e_mac_ics_read,
3052 [TORH] = e1000e_mac_read_clr8,
3053 [GORCH] = e1000e_mac_read_clr8,
3054 [PRC127] = e1000e_mac_read_clr4,
3055 [PRC511] = e1000e_mac_read_clr4,
3056 [PRC1522] = e1000e_mac_read_clr4,
3057 [PTC127] = e1000e_mac_read_clr4,
3058 [PTC511] = e1000e_mac_read_clr4,
3059 [PTC1522] = e1000e_mac_read_clr4,
3060 [GPTC] = e1000e_mac_read_clr4,
3061 [TPR] = e1000e_mac_read_clr4,
3062 [ROC] = e1000e_mac_read_clr4,
3063 [MPRC] = e1000e_mac_read_clr4,
3064 [BPTC] = e1000e_mac_read_clr4,
3065 [TSCTC] = e1000e_mac_read_clr4,
3066 [ITR] = e1000e_mac_itr_read,
3067 [CTRL] = e1000e_get_ctrl,
3068 [TARC1] = e1000e_get_tarc,
3069 [SWSM] = e1000e_mac_swsm_read,
3070 [IMS] = e1000e_mac_ims_read,
3071 [SYSTIML] = e1000e_get_systiml,
3072 [RXSATRH] = e1000e_get_rxsatrh,
3073 [TXSTMPH] = e1000e_get_txstmph,
3074
3075 [CRCERRS ... MPC] = e1000e_mac_readreg,
3076 [IP6AT ... IP6AT + 3] = e1000e_mac_readreg,
3077 [IP4AT ... IP4AT + 6] = e1000e_mac_readreg,
3078 [RA ... RA + 31] = e1000e_mac_readreg,
3079 [WUPM ... WUPM + 31] = e1000e_mac_readreg,
3080 [MTA ... MTA + E1000_MC_TBL_SIZE - 1] = e1000e_mac_readreg,
3081 [VFTA ... VFTA + E1000_VLAN_FILTER_TBL_SIZE - 1] = e1000e_mac_readreg,
3082 [FFMT ... FFMT + 254] = e1000e_mac_readreg,
3083 [FFVT ... FFVT + 254] = e1000e_mac_readreg,
3084 [MDEF ... MDEF + 7] = e1000e_mac_readreg,
3085 [FFLT ... FFLT + 10] = e1000e_mac_readreg,
3086 [FTFT ... FTFT + 254] = e1000e_mac_readreg,
3087 [PBM ... PBM + 10239] = e1000e_mac_readreg,
3088 [RETA ... RETA + 31] = e1000e_mac_readreg,
3089 [RSSRK ... RSSRK + 31] = e1000e_mac_readreg,
3090 [MAVTV0 ... MAVTV3] = e1000e_mac_readreg,
3091 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = e1000e_mac_eitr_read
3092 };
3093 enum { E1000E_NREADOPS = ARRAY_SIZE(e1000e_macreg_readops) };
3094
3095 #define e1000e_putreg(x) [x] = e1000e_mac_writereg
3096 typedef void (*writeops)(E1000ECore *, int, uint32_t);
3097 static const writeops e1000e_macreg_writeops[] = {
3098 e1000e_putreg(PBA),
3099 e1000e_putreg(SWSM),
3100 e1000e_putreg(WUFC),
3101 e1000e_putreg(RDBAH1),
3102 e1000e_putreg(TDBAH),
3103 e1000e_putreg(TXDCTL),
3104 e1000e_putreg(RDBAH0),
3105 e1000e_putreg(LEDCTL),
3106 e1000e_putreg(FCAL),
3107 e1000e_putreg(FCRUC),
3108 e1000e_putreg(WUC),
3109 e1000e_putreg(WUS),
3110 e1000e_putreg(IPAV),
3111 e1000e_putreg(TDBAH1),
3112 e1000e_putreg(IAM),
3113 e1000e_putreg(EIAC),
3114 e1000e_putreg(IVAR),
3115 e1000e_putreg(TARC0),
3116 e1000e_putreg(TARC1),
3117 e1000e_putreg(FLSWDATA),
3118 e1000e_putreg(POEMB),
3119 e1000e_putreg(MFUTP01),
3120 e1000e_putreg(MFUTP23),
3121 e1000e_putreg(MANC),
3122 e1000e_putreg(MANC2H),
3123 e1000e_putreg(MFVAL),
3124 e1000e_putreg(EXTCNF_CTRL),
3125 e1000e_putreg(FACTPS),
3126 e1000e_putreg(FUNCTAG),
3127 e1000e_putreg(GSCL_1),
3128 e1000e_putreg(GSCL_2),
3129 e1000e_putreg(GSCL_3),
3130 e1000e_putreg(GSCL_4),
3131 e1000e_putreg(GSCN_0),
3132 e1000e_putreg(GSCN_1),
3133 e1000e_putreg(GSCN_2),
3134 e1000e_putreg(GSCN_3),
3135 e1000e_putreg(GCR2),
3136 e1000e_putreg(MRQC),
3137 e1000e_putreg(FLOP),
3138 e1000e_putreg(FLOL),
3139 e1000e_putreg(FLSWCTL),
3140 e1000e_putreg(FLSWCNT),
3141 e1000e_putreg(FLA),
3142 e1000e_putreg(RXDCTL1),
3143 e1000e_putreg(TXDCTL1),
3144 e1000e_putreg(TIPG),
3145 e1000e_putreg(RXSTMPH),
3146 e1000e_putreg(RXSTMPL),
3147 e1000e_putreg(RXSATRL),
3148 e1000e_putreg(RXSATRH),
3149 e1000e_putreg(TXSTMPL),
3150 e1000e_putreg(TXSTMPH),
3151 e1000e_putreg(SYSTIML),
3152 e1000e_putreg(SYSTIMH),
3153 e1000e_putreg(TIMADJL),
3154 e1000e_putreg(RXUDP),
3155 e1000e_putreg(RXCFGL),
3156 e1000e_putreg(TSYNCRXCTL),
3157 e1000e_putreg(TSYNCTXCTL),
3158 e1000e_putreg(EXTCNF_SIZE),
3159 e1000e_putreg(EEMNGCTL),
3160 e1000e_putreg(RA),
3161
3162 [TDH1] = e1000e_set_16bit,
3163 [TDT1] = e1000e_set_tdt,
3164 [TCTL] = e1000e_set_tctl,
3165 [TDT] = e1000e_set_tdt,
3166 [MDIC] = e1000e_set_mdic,
3167 [ICS] = e1000e_set_ics,
3168 [TDH] = e1000e_set_16bit,
3169 [RDH0] = e1000e_set_16bit,
3170 [RDT0] = e1000e_set_rdt,
3171 [IMC] = e1000e_set_imc,
3172 [IMS] = e1000e_set_ims,
3173 [ICR] = e1000e_set_icr,
3174 [EECD] = e1000e_set_eecd,
3175 [RCTL] = e1000e_set_rx_control,
3176 [CTRL] = e1000e_set_ctrl,
3177 [RDTR] = e1000e_set_rdtr,
3178 [RADV] = e1000e_set_16bit,
3179 [TADV] = e1000e_set_16bit,
3180 [ITR] = e1000e_set_itr,
3181 [EERD] = e1000e_set_eerd,
3182 [AIT] = e1000e_set_16bit,
3183 [TDFH] = e1000e_set_13bit,
3184 [TDFT] = e1000e_set_13bit,
3185 [TDFHS] = e1000e_set_13bit,
3186 [TDFTS] = e1000e_set_13bit,
3187 [TDFPC] = e1000e_set_13bit,
3188 [RDFH] = e1000e_set_13bit,
3189 [RDFHS] = e1000e_set_13bit,
3190 [RDFT] = e1000e_set_13bit,
3191 [RDFTS] = e1000e_set_13bit,
3192 [RDFPC] = e1000e_set_13bit,
3193 [PBS] = e1000e_set_6bit,
3194 [GCR] = e1000e_set_gcr,
3195 [PSRCTL] = e1000e_set_psrctl,
3196 [RXCSUM] = e1000e_set_rxcsum,
3197 [RAID] = e1000e_set_16bit,
3198 [RSRPD] = e1000e_set_12bit,
3199 [TIDV] = e1000e_set_tidv,
3200 [TDLEN1] = e1000e_set_dlen,
3201 [TDLEN] = e1000e_set_dlen,
3202 [RDLEN0] = e1000e_set_dlen,
3203 [RDLEN1] = e1000e_set_dlen,
3204 [TDBAL] = e1000e_set_dbal,
3205 [TDBAL1] = e1000e_set_dbal,
3206 [RDBAL0] = e1000e_set_dbal,
3207 [RDBAL1] = e1000e_set_dbal,
3208 [RDH1] = e1000e_set_16bit,
3209 [RDT1] = e1000e_set_rdt,
3210 [STATUS] = e1000e_set_status,
3211 [PBACLR] = e1000e_set_pbaclr,
3212 [CTRL_EXT] = e1000e_set_ctrlext,
3213 [FCAH] = e1000e_set_16bit,
3214 [FCT] = e1000e_set_16bit,
3215 [FCTTV] = e1000e_set_16bit,
3216 [FCRTV] = e1000e_set_16bit,
3217 [FCRTH] = e1000e_set_fcrth,
3218 [FCRTL] = e1000e_set_fcrtl,
3219 [VET] = e1000e_set_vet,
3220 [RXDCTL] = e1000e_set_rxdctl,
3221 [FLASHT] = e1000e_set_16bit,
3222 [EEWR] = e1000e_set_eewr,
3223 [CTRL_DUP] = e1000e_set_ctrl,
3224 [RFCTL] = e1000e_set_rfctl,
3225 [RA + 1] = e1000e_mac_setmacaddr,
3226 [TIMINCA] = e1000e_set_timinca,
3227 [TIMADJH] = e1000e_set_timadjh,
3228
3229 [IP6AT ... IP6AT + 3] = e1000e_mac_writereg,
3230 [IP4AT ... IP4AT + 6] = e1000e_mac_writereg,
3231 [RA + 2 ... RA + 31] = e1000e_mac_writereg,
3232 [WUPM ... WUPM + 31] = e1000e_mac_writereg,
3233 [MTA ... MTA + E1000_MC_TBL_SIZE - 1] = e1000e_mac_writereg,
3234 [VFTA ... VFTA + E1000_VLAN_FILTER_TBL_SIZE - 1] = e1000e_mac_writereg,
3235 [FFMT ... FFMT + 254] = e1000e_set_4bit,
3236 [FFVT ... FFVT + 254] = e1000e_mac_writereg,
3237 [PBM ... PBM + 10239] = e1000e_mac_writereg,
3238 [MDEF ... MDEF + 7] = e1000e_mac_writereg,
3239 [FFLT ... FFLT + 10] = e1000e_set_11bit,
3240 [FTFT ... FTFT + 254] = e1000e_mac_writereg,
3241 [RETA ... RETA + 31] = e1000e_mac_writereg,
3242 [RSSRK ... RSSRK + 31] = e1000e_mac_writereg,
3243 [MAVTV0 ... MAVTV3] = e1000e_mac_writereg,
3244 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = e1000e_set_eitr
3245 };
3246 enum { E1000E_NWRITEOPS = ARRAY_SIZE(e1000e_macreg_writeops) };
3247
3248 enum { MAC_ACCESS_PARTIAL = 1 };
3249
3250 /*
3251 * The array below combines alias offsets of the index values for the
3252 * MAC registers that have aliases, with the indication of not fully
3253 * implemented registers (lowest bit). This combination is possible
3254 * because all of the offsets are even.
3255 */
3256 static const uint16_t mac_reg_access[E1000E_MAC_SIZE] = {
3257 /* Alias index offsets */
3258 [FCRTL_A] = 0x07fe, [FCRTH_A] = 0x0802,
3259 [RDH0_A] = 0x09bc, [RDT0_A] = 0x09bc, [RDTR_A] = 0x09c6,
3260 [RDFH_A] = 0xe904, [RDFT_A] = 0xe904,
3261 [TDH_A] = 0x0cf8, [TDT_A] = 0x0cf8, [TIDV_A] = 0x0cf8,
3262 [TDFH_A] = 0xed00, [TDFT_A] = 0xed00,
3263 [RA_A ... RA_A + 31] = 0x14f0,
3264 [VFTA_A ... VFTA_A + E1000_VLAN_FILTER_TBL_SIZE - 1] = 0x1400,
3265 [RDBAL0_A ... RDLEN0_A] = 0x09bc,
3266 [TDBAL_A ... TDLEN_A] = 0x0cf8,
3267 /* Access options */
3268 [RDFH] = MAC_ACCESS_PARTIAL, [RDFT] = MAC_ACCESS_PARTIAL,
3269 [RDFHS] = MAC_ACCESS_PARTIAL, [RDFTS] = MAC_ACCESS_PARTIAL,
3270 [RDFPC] = MAC_ACCESS_PARTIAL,
3271 [TDFH] = MAC_ACCESS_PARTIAL, [TDFT] = MAC_ACCESS_PARTIAL,
3272 [TDFHS] = MAC_ACCESS_PARTIAL, [TDFTS] = MAC_ACCESS_PARTIAL,
3273 [TDFPC] = MAC_ACCESS_PARTIAL, [EECD] = MAC_ACCESS_PARTIAL,
3274 [PBM] = MAC_ACCESS_PARTIAL, [FLA] = MAC_ACCESS_PARTIAL,
3275 [FCAL] = MAC_ACCESS_PARTIAL, [FCAH] = MAC_ACCESS_PARTIAL,
3276 [FCT] = MAC_ACCESS_PARTIAL, [FCTTV] = MAC_ACCESS_PARTIAL,
3277 [FCRTV] = MAC_ACCESS_PARTIAL, [FCRTL] = MAC_ACCESS_PARTIAL,
3278 [FCRTH] = MAC_ACCESS_PARTIAL, [TXDCTL] = MAC_ACCESS_PARTIAL,
3279 [TXDCTL1] = MAC_ACCESS_PARTIAL,
3280 [MAVTV0 ... MAVTV3] = MAC_ACCESS_PARTIAL
3281 };
3282
3283 void
3284 e1000e_core_write(E1000ECore *core, hwaddr addr, uint64_t val, unsigned size)
3285 {
3286 uint16_t index = e1000e_get_reg_index_with_offset(mac_reg_access, addr);
3287
3288 if (index < E1000E_NWRITEOPS && e1000e_macreg_writeops[index]) {
3289 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) {
3290 trace_e1000e_wrn_regs_write_trivial(index << 2);
3291 }
3292 trace_e1000e_core_write(index << 2, size, val);
3293 e1000e_macreg_writeops[index](core, index, val);
3294 } else if (index < E1000E_NREADOPS && e1000e_macreg_readops[index]) {
3295 trace_e1000e_wrn_regs_write_ro(index << 2, size, val);
3296 } else {
3297 trace_e1000e_wrn_regs_write_unknown(index << 2, size, val);
3298 }
3299 }
3300
3301 uint64_t
3302 e1000e_core_read(E1000ECore *core, hwaddr addr, unsigned size)
3303 {
3304 uint64_t val;
3305 uint16_t index = e1000e_get_reg_index_with_offset(mac_reg_access, addr);
3306
3307 if (index < E1000E_NREADOPS && e1000e_macreg_readops[index]) {
3308 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) {
3309 trace_e1000e_wrn_regs_read_trivial(index << 2);
3310 }
3311 val = e1000e_macreg_readops[index](core, index);
3312 trace_e1000e_core_read(index << 2, size, val);
3313 return val;
3314 } else {
3315 trace_e1000e_wrn_regs_read_unknown(index << 2, size);
3316 }
3317 return 0;
3318 }
3319
3320 static inline void
3321 e1000e_autoneg_pause(E1000ECore *core)
3322 {
3323 timer_del(core->autoneg_timer);
3324 }
3325
3326 static void
3327 e1000e_autoneg_resume(E1000ECore *core)
3328 {
3329 if (e1000e_have_autoneg(core) &&
3330 !(core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP)) {
3331 qemu_get_queue(core->owner_nic)->link_down = false;
3332 timer_mod(core->autoneg_timer,
3333 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 500);
3334 }
3335 }
3336
3337 static void
3338 e1000e_vm_state_change(void *opaque, bool running, RunState state)
3339 {
3340 E1000ECore *core = opaque;
3341
3342 if (running) {
3343 trace_e1000e_vm_state_running();
3344 e1000e_intrmgr_resume(core);
3345 e1000e_autoneg_resume(core);
3346 } else {
3347 trace_e1000e_vm_state_stopped();
3348 e1000e_autoneg_pause(core);
3349 e1000e_intrmgr_pause(core);
3350 }
3351 }
3352
3353 void
3354 e1000e_core_pci_realize(E1000ECore *core,
3355 const uint16_t *eeprom_templ,
3356 uint32_t eeprom_size,
3357 const uint8_t *macaddr)
3358 {
3359 int i;
3360
3361 core->autoneg_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL,
3362 e1000e_autoneg_timer, core);
3363 e1000e_intrmgr_pci_realize(core);
3364
3365 core->vmstate =
3366 qemu_add_vm_change_state_handler(e1000e_vm_state_change, core);
3367
3368 for (i = 0; i < E1000E_NUM_QUEUES; i++) {
3369 net_tx_pkt_init(&core->tx[i].tx_pkt, E1000E_MAX_TX_FRAGS);
3370 }
3371
3372 net_rx_pkt_init(&core->rx_pkt);
3373
3374 e1000x_core_prepare_eeprom(core->eeprom,
3375 eeprom_templ,
3376 eeprom_size,
3377 PCI_DEVICE_GET_CLASS(core->owner)->device_id,
3378 macaddr);
3379 e1000e_update_rx_offloads(core);
3380 }
3381
3382 void
3383 e1000e_core_pci_uninit(E1000ECore *core)
3384 {
3385 int i;
3386
3387 timer_free(core->autoneg_timer);
3388
3389 e1000e_intrmgr_pci_unint(core);
3390
3391 qemu_del_vm_change_state_handler(core->vmstate);
3392
3393 for (i = 0; i < E1000E_NUM_QUEUES; i++) {
3394 net_tx_pkt_uninit(core->tx[i].tx_pkt);
3395 }
3396
3397 net_rx_pkt_uninit(core->rx_pkt);
3398 }
3399
3400 static const uint16_t
3401 e1000e_phy_reg_init[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE] = {
3402 [0] = {
3403 [MII_BMCR] = MII_BMCR_SPEED1000 |
3404 MII_BMCR_FD |
3405 MII_BMCR_AUTOEN,
3406
3407 [MII_BMSR] = MII_BMSR_EXTCAP |
3408 MII_BMSR_LINK_ST |
3409 MII_BMSR_AUTONEG |
3410 MII_BMSR_MFPS |
3411 MII_BMSR_EXTSTAT |
3412 MII_BMSR_10T_HD |
3413 MII_BMSR_10T_FD |
3414 MII_BMSR_100TX_HD |
3415 MII_BMSR_100TX_FD,
3416
3417 [MII_PHYID1] = 0x141,
3418 [MII_PHYID2] = E1000_PHY_ID2_82574x,
3419 [MII_ANAR] = MII_ANAR_CSMACD | MII_ANAR_10 |
3420 MII_ANAR_10FD | MII_ANAR_TX |
3421 MII_ANAR_TXFD | MII_ANAR_PAUSE |
3422 MII_ANAR_PAUSE_ASYM,
3423 [MII_ANLPAR] = MII_ANLPAR_10 | MII_ANLPAR_10FD |
3424 MII_ANLPAR_TX | MII_ANLPAR_TXFD |
3425 MII_ANLPAR_T4 | MII_ANLPAR_PAUSE,
3426 [MII_ANER] = MII_ANER_NP | MII_ANER_NWAY,
3427 [MII_ANNP] = 1 | MII_ANNP_MP,
3428 [MII_CTRL1000] = MII_CTRL1000_HALF | MII_CTRL1000_FULL |
3429 MII_CTRL1000_PORT | MII_CTRL1000_MASTER,
3430 [MII_STAT1000] = MII_STAT1000_HALF | MII_STAT1000_FULL |
3431 MII_STAT1000_ROK | MII_STAT1000_LOK,
3432 [MII_EXTSTAT] = MII_EXTSTAT_1000T_HD | MII_EXTSTAT_1000T_FD,
3433
3434 [PHY_COPPER_CTRL1] = BIT(5) | BIT(6) | BIT(8) | BIT(9) |
3435 BIT(12) | BIT(13),
3436 [PHY_COPPER_STAT1] = BIT(3) | BIT(10) | BIT(11) | BIT(13) | BIT(15)
3437 },
3438 [2] = {
3439 [PHY_MAC_CTRL1] = BIT(3) | BIT(7),
3440 [PHY_MAC_CTRL2] = BIT(1) | BIT(2) | BIT(6) | BIT(12)
3441 },
3442 [3] = {
3443 [PHY_LED_TIMER_CTRL] = BIT(0) | BIT(2) | BIT(14)
3444 }
3445 };
3446
3447 static const uint32_t e1000e_mac_reg_init[] = {
3448 [PBA] = 0x00140014,
3449 [LEDCTL] = BIT(1) | BIT(8) | BIT(9) | BIT(15) | BIT(17) | BIT(18),
3450 [EXTCNF_CTRL] = BIT(3),
3451 [EEMNGCTL] = BIT(31),
3452 [FLASHT] = 0x2,
3453 [FLSWCTL] = BIT(30) | BIT(31),
3454 [FLOL] = BIT(0),
3455 [RXDCTL] = BIT(16),
3456 [RXDCTL1] = BIT(16),
3457 [TIPG] = 0x8 | (0x8 << 10) | (0x6 << 20),
3458 [RXCFGL] = 0x88F7,
3459 [RXUDP] = 0x319,
3460 [CTRL] = E1000_CTRL_FD | E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN0 |
3461 E1000_CTRL_SPD_1000 | E1000_CTRL_SLU |
3462 E1000_CTRL_ADVD3WUC,
3463 [STATUS] = E1000_STATUS_ASDV_1000 | E1000_STATUS_LU,
3464 [PSRCTL] = (2 << E1000_PSRCTL_BSIZE0_SHIFT) |
3465 (4 << E1000_PSRCTL_BSIZE1_SHIFT) |
3466 (4 << E1000_PSRCTL_BSIZE2_SHIFT),
3467 [TARC0] = 0x3 | E1000_TARC_ENABLE,
3468 [TARC1] = 0x3 | E1000_TARC_ENABLE,
3469 [EECD] = E1000_EECD_AUTO_RD | E1000_EECD_PRES,
3470 [EERD] = E1000_EERW_DONE,
3471 [EEWR] = E1000_EERW_DONE,
3472 [GCR] = E1000_L0S_ADJUST |
3473 E1000_L1_ENTRY_LATENCY_MSB |
3474 E1000_L1_ENTRY_LATENCY_LSB,
3475 [TDFH] = 0x600,
3476 [TDFT] = 0x600,
3477 [TDFHS] = 0x600,
3478 [TDFTS] = 0x600,
3479 [POEMB] = 0x30D,
3480 [PBS] = 0x028,
3481 [MANC] = E1000_MANC_DIS_IP_CHK_ARP,
3482 [FACTPS] = E1000_FACTPS_LAN0_ON | 0x20000000,
3483 [SWSM] = 1,
3484 [RXCSUM] = E1000_RXCSUM_IPOFLD | E1000_RXCSUM_TUOFLD,
3485 [ITR] = E1000E_MIN_XITR,
3486 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = E1000E_MIN_XITR,
3487 };
3488
3489 static void e1000e_reset(E1000ECore *core, bool sw)
3490 {
3491 int i;
3492
3493 timer_del(core->autoneg_timer);
3494
3495 e1000e_intrmgr_reset(core);
3496
3497 memset(core->phy, 0, sizeof core->phy);
3498 memcpy(core->phy, e1000e_phy_reg_init, sizeof e1000e_phy_reg_init);
3499
3500 for (i = 0; i < E1000E_MAC_SIZE; i++) {
3501 if (sw && (i == PBA || i == PBS || i == FLA)) {
3502 continue;
3503 }
3504
3505 core->mac[i] = i < ARRAY_SIZE(e1000e_mac_reg_init) ?
3506 e1000e_mac_reg_init[i] : 0;
3507 }
3508
3509 core->rxbuf_min_shift = 1 + E1000_RING_DESC_LEN_SHIFT;
3510
3511 if (qemu_get_queue(core->owner_nic)->link_down) {
3512 e1000e_link_down(core);
3513 }
3514
3515 e1000x_reset_mac_addr(core->owner_nic, core->mac, core->permanent_mac);
3516
3517 for (i = 0; i < ARRAY_SIZE(core->tx); i++) {
3518 memset(&core->tx[i].props, 0, sizeof(core->tx[i].props));
3519 core->tx[i].skip_cp = false;
3520 }
3521 }
3522
3523 void
3524 e1000e_core_reset(E1000ECore *core)
3525 {
3526 e1000e_reset(core, false);
3527 }
3528
3529 void e1000e_core_pre_save(E1000ECore *core)
3530 {
3531 int i;
3532 NetClientState *nc = qemu_get_queue(core->owner_nic);
3533
3534 /*
3535 * If link is down and auto-negotiation is supported and ongoing,
3536 * complete auto-negotiation immediately. This allows us to look
3537 * at MII_BMSR_AN_COMP to infer link status on load.
3538 */
3539 if (nc->link_down && e1000e_have_autoneg(core)) {
3540 core->phy[0][MII_BMSR] |= MII_BMSR_AN_COMP;
3541 e1000e_update_flowctl_status(core);
3542 }
3543
3544 for (i = 0; i < ARRAY_SIZE(core->tx); i++) {
3545 if (net_tx_pkt_has_fragments(core->tx[i].tx_pkt)) {
3546 core->tx[i].skip_cp = true;
3547 }
3548 }
3549 }
3550
3551 int
3552 e1000e_core_post_load(E1000ECore *core)
3553 {
3554 NetClientState *nc = qemu_get_queue(core->owner_nic);
3555
3556 /*
3557 * nc.link_down can't be migrated, so infer link_down according
3558 * to link status bit in core.mac[STATUS].
3559 */
3560 nc->link_down = (core->mac[STATUS] & E1000_STATUS_LU) == 0;
3561
3562 return 0;
3563 }
armbru's QEMU hackery