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RISC-V: Use atomic_cmpxchg to update PLIC bitmaps
2018-09-04
Michael Clark
RI
S
C-V:
U
se at
o
m
ic_
c
mpx
c
hg t
o
update PLIC bitm
a
ps
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-09-04
Michael Clark
RISC
-
V
:
Impro
v
e
p
age table
w
alker
spec comp
l
iance
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-09-04
M
i
ch
a
el Clark
RIS
C
-V: Update
a
ddress bits to support sv39 and sv48
commit
|
commitdiff
|
tree
2018-05-05
Michael Clark
R
I
SC
-
V: M
a
rk ROM read-only after cop
y
in
g
in c
o
d
e
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-05-05
Michael Clark
RISC-V
:
No
traps on wri
t
es to misa,min
s
tret,mcycle
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-05-05
Mi
c
hael Clark
RIS
C
-V: Make mtvec/stvec ignore vectored traps
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-05-05
Mich
a
el Cla
r
k
RISC-V: Add mcycl
e
/min
s
tret support for -icount auto
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-05-05
Michael Cla
r
k
RISC
-
V
:
Us
e
[ms]coun
t
eren CSRs wh
e
n
p
riv IS
A
>=
v
1
.
10
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-05-05
M
i
chael Clark
R
I
S
C-V: Allow S-mode mxr ac
c
es
s
when priv ISA >=
v1
.
1
0
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-05-05
Michael Cla
r
k
R
ISC
-
V: Clear mtval/stval on exceptio
n
s without inf
o
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-05-05
M
i
chael Clark
RISC
-
V: Hardwire
s
a
tp
to 0 for no-mmu case
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-05-05
M
ic
h
ael Clark
R
I
S
C
-
V: Update E and I ext
e
nsion or
d
er
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-05-05
M
i
ch
a
el
Clark
RISC-V: Re
m
ove e
r
rone
o
us
c
omm
e
nt fro
m
translate
.
c
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-05-05
Michael Clark
RISC
-
V: Remove EM_R
I
SCV EL
F
_MACHINE indirection
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-05-05
M
i
ch
a
el Clark
RISC-V: Make vi
r
t header comment t
i
tl
e
co
n
sistent
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-05-05
Michael Clark
RISC-V: M
a
ke some
h
e
a
d
e
r guards more
s
pecific
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-05-05
M
ichael Clark
R
ISC-V: Fix missing break st
a
t
ement in disassembler
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-05-05
Mic
h
ael Clar
k
RI
S
C-V
:
Include instruction hex in
disassemb
l
y
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-05-05
Mic
h
ae
l
Clark
R
I
S
C
-
V: Re
m
ove unu
s
ed class
d
efinitio
n
s
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-05-05
Michae
l
Clark
RISC-V: Remov
e
ident
i
ty_t
r
anslate from load_elf
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-05-05
M
ichae
l
Clark
RISC-V: Use RO
M
b
a
s
e ad
d
re
s
s
and siz
e
from memma
p
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-05-05
Michael Clark
RISC-V:
Make virt board description match spike
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-05-05
Micha
e
l Cl
a
rk
RISC
-
V: Replace hardcoded constants with enum values
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-29
Mich
a
el Clar
k
RISC-V: Wor
k
around for
critica
l
mstatus
.
FS bug
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-28
Michael Cla
r
k
RISC-
V
: Fix in
c
orrect
di
s
asse
m
b
l
y fo
r
addiw
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-28
M
ichael Clark
RIS
C
-
V
: Convert cpu definition to future model
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-20
Michael Clark
RISC-
V
:
Fix riscv_i
s
a_st
r
ing memory
s
ize
bug
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Michael Cl
a
rk
R
ISC-V
B
uild Infr
a
s
t
ructure
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Mi
c
h
ael Cla
r
k
SiFive Freedo
m
U Se
r
i
es RISC-V
M
achine
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Mich
a
e
l
Clark
SiFive Fr
e
edom E
Ser
i
es RISC-V
M
achine
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Michael
C
lark
Si
F
ive R
I
SC-V PRC
I
Block
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Micha
e
l Clark
SiFive RISC-V UAR
T
Device
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Michael Clark
RISC-V VirtIO Machine
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Mi
c
hael Clark
SiFive RI
S
C-V Te
s
t Fi
n
isher
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
M
i
cha
e
l Clark
RISC-
V
Spike Machine
s
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Michael Clark
SiF
i
ve RISC-V PLIC Block
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Michael Clark
SiFive RIS
C
-V CL
I
NT Block
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
M
i
c
hael Clark
RISC
-
V HAR
T
A
rray
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Mic
h
ael Cla
r
k
R
I
S
C
-
V
HTIF Console
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Mich
a
el Clar
k
Add symbol table callback
interface to load_elf
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Michael Clark
RI
S
C-V Linux User Emulatio
n
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Micha
e
l Clark
RISC-
V
Physical
Memory Pr
o
tection
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Mich
a
el Clark
R
ISC-V TCG Code Ge
n
era
t
ion
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Mic
h
ael Clark
RISC-V GD
B
Stub
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Micha
e
l C
l
ark
RIS
C
-V FPU Supp
o
rt
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Mi
c
h
ael Clark
RISC-V CPU Helpers
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Michael
C
lark
R
I
SC-V Disassembler
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Micha
e
l Clark
RISC-V
CPU
Core Defin
i
t
ion
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Michael
C
lar
k
RISC-V ELF Machine Definition
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Michael Cla
r
k
RISC-V Maintainers
Add
Michael Clark
, Palmer Dabbelt, Sagar Karandikar...
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree