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target/openrisc: Fix cpu_mmu_index
2018-07-02 Richard Hendersontarget/openrisc: Fix cpu_mmu_index
Signed-off-by: Stafford Horne <shorne@gmail.com>
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2018-07-02 Richard Hendersontarget/openrisc: Fix tlb flushing in mtspr
Signed-off-by: Stafford Horne <shorne@gmail.com>
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2018-07-02 Richard Hendersontarget/openrisc: Reduce tlb to a single dimension
Signed-off-by: Stafford Horne <shorne@gmail.com>
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2018-07-02 Richard Hendersontarget/openrisc: Merge mmu_helper.c into mmu.c
Signed-off-by: Stafford Horne <shorne@gmail.com>
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2018-07-02 Richard Hendersontarget/openrisc: Remove indirect function calls for mmu
Signed-off-by: Stafford Horne <shorne@gmail.com>
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2018-07-02 Richard Hendersontarget/openrisc: Merge tlb allocation into CPUOpenRISCState
Reviewed-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Stafford Horne <shorne@gmail.com>
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2018-07-02 Richard Hendersontarget/openrisc: Form the spr index from tcg
Signed-off-by: Stafford Horne <shorne@gmail.com>
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2018-07-02 Richard Hendersontarget/openrisc: Exit the TB after l.mtspr
Signed-off-by: Stafford Horne <shorne@gmail.com>
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2018-07-02 Richard Hendersontarget/openrisc: Split out is_user
Reviewed-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Stafford Horne <shorne@gmail.com>
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2018-07-02 Richard Hendersontarget/openrisc: Link more translation blocks
Reviewed-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Stafford Horne <shorne@gmail.com>
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2018-07-02 Richard Hendersontarget/openrisc: Fix singlestep_enabled
Reviewed-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Stafford Horne <shorne@gmail.com>
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2018-07-02 Richard Hendersontarget/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTB
Reviewed-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Stafford Horne <shorne@gmail.com>
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2018-07-02 Richard Hendersontarget/openrisc: Remove DISAS_JUMP & DISAS_TB_JUMP
Reviewed-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Stafford Horne <shorne@gmail.com>
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2018-07-02 Richard Hendersontarget/openrisc: Log interrupts
Signed-off-by: Stafford Horne <shorne@gmail.com>
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2018-07-02 Richard Hendersontarget/openrisc: Add print_insn_or1k
Signed-off-by: Stafford Horne <shorne@gmail.com>
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2018-07-02 Richard Hendersontarget/openrisc: Fix mtspr shadow gprs
Signed-off-by: Stafford Horne <shorne@gmail.com>
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2017-10-20 Stafford Horneopenrisc: Only kick cpu on timeout, not on update
Signed-off-by: Stafford Horne <shorne@gmail.com>
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2017-10-20 Stafford Horneopenrisc: Initial SMP support
Signed-off-by: Stafford Horne <shorne@gmail.com>
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2017-10-20 Stafford Horneopenrisc/cputimer: Perparation for Multicore
Signed-off-by: Stafford Horne <shorne@gmail.com>
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2017-10-20 Stafford Hornetarget/openrisc: Make coreid and numcores variable
Signed-off-by: Stafford Horne <shorne@gmail.com>
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2017-10-20 Stafford Horneopenrisc/ompic: Add OpenRISC Multicore PIC (OMPIC)
Signed-off-by: Stafford Horne <shorne@gmail.com>
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2017-05-04 Stafford Hornetarget/openrisc: Support non-busy idle state using...
Signed-off-by: Stafford Horne <shorne@gmail.com>
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2017-05-04 Stafford Hornetarget/openrisc: Remove duplicate features property
Signed-off-by: Stafford Horne <shorne@gmail.com>
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2017-05-04 Stafford Hornetarget/openrisc: Implement full vmstate serialization
Signed-off-by: Stafford Horne <shorne@gmail.com>
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2017-05-04 Stafford Hornemigration: Add VMSTATE_STRUCT_2DARRAY()
Signed-off-by: Stafford Horne <shorne@gmail.com>
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2017-05-04 Stafford Hornetarget/openrisc: implement shadow registers
Signed-off-by: Stafford Horne <shorne@gmail.com>
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2017-05-04 Stafford Hornemigration: Add VMSTATE_UINTTL_2DARRAY()
Signed-off-by: Stafford Horne <shorne@gmail.com>
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2017-05-04 Stafford Hornetarget/openrisc: add numcores and coreid support
Signed-off-by: Stafford Horne <shorne@gmail.com>
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2017-05-04 Stafford Hornetarget/openrisc: Fixes for memory debugging
Signed-off-by: Stafford Horne <shorne@gmail.com>
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2017-04-21 Tim 'mithro' Anselltarget/openrisc: Implement EPH bit
Signed-off-by: Stafford Horne <shorne@gmail.com>
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2017-04-21 Tim 'mithro' Anselltarget/openrisc: Implement EVBAR register
Signed-off-by: Stafford Horne <shorne@gmail.com>
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2017-04-21 Stafford HorneMAINTAINERS: Add myself as openrisc maintainer
Signed-off-by: Stafford Horne <shorne@gmail.com>
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AR7 emulation for QEMU