| commit | 455d45d22cc3b2c29c7840f2478647a0a3d9d8b4 | |
| author | Richard Henderson <richard.henderson@linaro.org> | |
| Tue, 22 May 2018 23:28:33 +0000 (22 16:28 -0700) | ||
| committer | Stafford Horne <shorne@gmail.com> | |
| Mon, 2 Jul 2018 15:05:28 +0000 (3 00:05 +0900) | ||
| tree | 102125b4dbd24e276261d7bba40c08e4f076488a | treesnapshot (tar.gz zip) |
| parent | c28fa81f915b03834b00187e43604e42768f15fa | commitdiff |
target/openrisc: Merge tlb allocation into CPUOpenRISCState
There is no reason to allocate this separately. This was probably
copied from target/mips which makes the same mistake.
While doing so, move tlb into the clear-on-reset range. While not
all of the TLB bits are guaranteed zero on reset, all of the valid
bits are cleared, and the rest of the bits are unspecified.
Therefore clearing the whole of the TLB is correct.
Reviewed-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
There is no reason to allocate this separately. This was probably
copied from target/mips which makes the same mistake.
While doing so, move tlb into the clear-on-reset range. While not
all of the TLB bits are guaranteed zero on reset, all of the valid
bits are cleared, and the rest of the bits are unspecified.
Therefore clearing the whole of the TLB is correct.
Reviewed-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>