target/openrisc/sys_helper.c

   1 /*
   2  * OpenRISC system instructions helper routines
   3  *
   4  * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
   5  *                         Zhizhou Zhang <etouzh@gmail.com>
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "cpu.h"
  23 #include "exec/exec-all.h"
  24 #include "exec/helper-proto.h"
  25 #include "exception.h"
  26 #include "sysemu/sysemu.h"
  27
  28 #define TO_SPR(group, number) (((group) << 11) + (number))
  29
  30 void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
  31 {
  32 #ifndef CONFIG_USER_ONLY
  33     OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
  34     CPUState *cs = CPU(cpu);
  35     int idx;
  36
  37     switch (spr) {
  38     case TO_SPR(0, 0): /* VR */
  39         env->vr = rb;
  40         break;
  41
  42     case TO_SPR(0, 11): /* EVBAR */
  43         env->evbar = rb;
  44         break;
  45
  46     case TO_SPR(0, 16): /* NPC */
  47         cpu_restore_state(cs, GETPC(), true);
  48         /* ??? Mirror or1ksim in not trashing delayed branch state
  49            when "jumping" to the current instruction.  */
  50         if (env->pc != rb) {
  51             env->pc = rb;
  52             env->dflag = 0;
  53             cpu_loop_exit(cs);
  54         }
  55         break;
  56
  57     case TO_SPR(0, 17): /* SR */
  58         if ((env->sr & (SR_IME | SR_DME | SR_SM)) ^
  59             (rb & (SR_IME | SR_DME | SR_SM))) {
  60             tlb_flush(cs);
  61         }
  62         cpu_set_sr(env, rb);
  63         if (env->sr & SR_DME) {
  64             env->tlb.cpu_openrisc_map_address_data =
  65                 &cpu_openrisc_get_phys_data;
  66         } else {
  67             env->tlb.cpu_openrisc_map_address_data =
  68                 &cpu_openrisc_get_phys_nommu;
  69         }
  70
  71         if (env->sr & SR_IME) {
  72             env->tlb.cpu_openrisc_map_address_code =
  73                 &cpu_openrisc_get_phys_code;
  74         } else {
  75             env->tlb.cpu_openrisc_map_address_code =
  76                 &cpu_openrisc_get_phys_nommu;
  77         }
  78         break;
  79
  80     case TO_SPR(0, 18): /* PPC */
  81         env->ppc = rb;
  82         break;
  83
  84     case TO_SPR(0, 32): /* EPCR */
  85         env->epcr = rb;
  86         break;
  87
  88     case TO_SPR(0, 48): /* EEAR */
  89         env->eear = rb;
  90         break;
  91
  92     case TO_SPR(0, 64): /* ESR */
  93         env->esr = rb;
  94         break;
  95
  96     case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */
  97         idx = (spr - 1024);
  98         env->shadow_gpr[idx / 32][idx % 32] = rb;
  99         break;
 100
 101     case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
 102         idx = spr - TO_SPR(1, 512);
 103         if (!(rb & 1)) {
 104             tlb_flush_page(cs, env->tlb.dtlb[0][idx].mr & TARGET_PAGE_MASK);
 105         }
 106         env->tlb.dtlb[0][idx].mr = rb;
 107         break;
 108
 109     case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */
 110         idx = spr - TO_SPR(1, 640);
 111         env->tlb.dtlb[0][idx].tr = rb;
 112         break;
 113     case TO_SPR(1, 768) ... TO_SPR(1, 895):   /* DTLBW1MR 0-127 */
 114     case TO_SPR(1, 896) ... TO_SPR(1, 1023):  /* DTLBW1TR 0-127 */
 115     case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */
 116     case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */
 117     case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
 118     case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
 119         break;
 120     case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1):   /* ITLBW0MR 0-127 */
 121         idx = spr - TO_SPR(2, 512);
 122         if (!(rb & 1)) {
 123             tlb_flush_page(cs, env->tlb.itlb[0][idx].mr & TARGET_PAGE_MASK);
 124         }
 125         env->tlb.itlb[0][idx].mr = rb;
 126         break;
 127
 128     case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */
 129         idx = spr - TO_SPR(2, 640);
 130         env->tlb.itlb[0][idx].tr = rb;
 131         break;
 132     case TO_SPR(2, 768) ... TO_SPR(2, 895):   /* ITLBW1MR 0-127 */
 133     case TO_SPR(2, 896) ... TO_SPR(2, 1023):  /* ITLBW1TR 0-127 */
 134     case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */
 135     case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */
 136     case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */
 137     case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
 138         break;
 139     case TO_SPR(5, 1):  /* MACLO */
 140         env->mac = deposit64(env->mac, 0, 32, rb);
 141         break;
 142     case TO_SPR(5, 2):  /* MACHI */
 143         env->mac = deposit64(env->mac, 32, 32, rb);
 144         break;
 145     case TO_SPR(8, 0):  /* PMR */
 146         env->pmr = rb;
 147         if (env->pmr & PMR_DME || env->pmr & PMR_SME) {
 148             cpu_restore_state(cs, GETPC(), true);
 149             env->pc += 4;
 150             cs->halted = 1;
 151             raise_exception(cpu, EXCP_HALTED);
 152         }
 153         break;
 154     case TO_SPR(9, 0):  /* PICMR */
 155         env->picmr |= rb;
 156         break;
 157     case TO_SPR(9, 2):  /* PICSR */
 158         env->picsr &= ~rb;
 159         break;
 160     case TO_SPR(10, 0): /* TTMR */
 161         {
 162             if ((env->ttmr & TTMR_M) ^ (rb & TTMR_M)) {
 163                 switch (rb & TTMR_M) {
 164                 case TIMER_NONE:
 165                     cpu_openrisc_count_stop(cpu);
 166                     break;
 167                 case TIMER_INTR:
 168                 case TIMER_SHOT:
 169                 case TIMER_CONT:
 170                     cpu_openrisc_count_start(cpu);
 171                     break;
 172                 default:
 173                     break;
 174                 }
 175             }
 176
 177             int ip = env->ttmr & TTMR_IP;
 178
 179             if (rb & TTMR_IP) {    /* Keep IP bit.  */
 180                 env->ttmr = (rb & ~TTMR_IP) | ip;
 181             } else {    /* Clear IP bit.  */
 182                 env->ttmr = rb & ~TTMR_IP;
 183                 cs->interrupt_request &= ~CPU_INTERRUPT_TIMER;
 184             }
 185
 186             cpu_openrisc_timer_update(cpu);
 187         }
 188         break;
 189
 190     case TO_SPR(10, 1): /* TTCR */
 191         cpu_openrisc_count_set(cpu, rb);
 192         if (env->ttmr & TIMER_NONE) {
 193             return;
 194         }
 195         cpu_openrisc_timer_update(cpu);
 196         break;
 197     default:
 198         break;
 199     }
 200 #endif
 201 }
 202
 203 target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd,
 204                            target_ulong spr)
 205 {
 206 #ifndef CONFIG_USER_ONLY
 207     OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
 208     CPUState *cs = CPU(cpu);
 209     int idx;
 210
 211     switch (spr) {
 212     case TO_SPR(0, 0): /* VR */
 213         return env->vr & SPR_VR;
 214
 215     case TO_SPR(0, 1): /* UPR */
 216         return env->upr;    /* TT, DM, IM, UP present */
 217
 218     case TO_SPR(0, 2): /* CPUCFGR */
 219         return env->cpucfgr;
 220
 221     case TO_SPR(0, 3): /* DMMUCFGR */
 222         return env->dmmucfgr;    /* 1Way, 64 entries */
 223
 224     case TO_SPR(0, 4): /* IMMUCFGR */
 225         return env->immucfgr;
 226
 227     case TO_SPR(0, 11): /* EVBAR */
 228         return env->evbar;
 229
 230     case TO_SPR(0, 16): /* NPC (equals PC) */
 231         cpu_restore_state(cs, GETPC(), false);
 232         return env->pc;
 233
 234     case TO_SPR(0, 17): /* SR */
 235         return cpu_get_sr(env);
 236
 237     case TO_SPR(0, 18): /* PPC */
 238         cpu_restore_state(cs, GETPC(), false);
 239         return env->ppc;
 240
 241     case TO_SPR(0, 32): /* EPCR */
 242         return env->epcr;
 243
 244     case TO_SPR(0, 48): /* EEAR */
 245         return env->eear;
 246
 247     case TO_SPR(0, 64): /* ESR */
 248         return env->esr;
 249
 250     case TO_SPR(0, 128): /* COREID */
 251         return cpu->parent_obj.cpu_index;
 252
 253     case TO_SPR(0, 129): /* NUMCORES */
 254         return max_cpus;
 255
 256     case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */
 257         idx = (spr - 1024);
 258         return env->shadow_gpr[idx / 32][idx % 32];
 259
 260     case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
 261         idx = spr - TO_SPR(1, 512);
 262         return env->tlb.dtlb[0][idx].mr;
 263
 264     case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */
 265         idx = spr - TO_SPR(1, 640);
 266         return env->tlb.dtlb[0][idx].tr;
 267
 268     case TO_SPR(1, 768) ... TO_SPR(1, 895):   /* DTLBW1MR 0-127 */
 269     case TO_SPR(1, 896) ... TO_SPR(1, 1023):  /* DTLBW1TR 0-127 */
 270     case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */
 271     case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */
 272     case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
 273     case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
 274         break;
 275
 276     case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */
 277         idx = spr - TO_SPR(2, 512);
 278         return env->tlb.itlb[0][idx].mr;
 279
 280     case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */
 281         idx = spr - TO_SPR(2, 640);
 282         return env->tlb.itlb[0][idx].tr;
 283
 284     case TO_SPR(2, 768) ... TO_SPR(2, 895):   /* ITLBW1MR 0-127 */
 285     case TO_SPR(2, 896) ... TO_SPR(2, 1023):  /* ITLBW1TR 0-127 */
 286     case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */
 287     case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */
 288     case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */
 289     case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
 290         break;
 291
 292     case TO_SPR(5, 1):  /* MACLO */
 293         return (uint32_t)env->mac;
 294         break;
 295     case TO_SPR(5, 2):  /* MACHI */
 296         return env->mac >> 32;
 297         break;
 298
 299     case TO_SPR(8, 0):  /* PMR */
 300         return env->pmr;
 301
 302     case TO_SPR(9, 0):  /* PICMR */
 303         return env->picmr;
 304
 305     case TO_SPR(9, 2):  /* PICSR */
 306         return env->picsr;
 307
 308     case TO_SPR(10, 0): /* TTMR */
 309         return env->ttmr;
 310
 311     case TO_SPR(10, 1): /* TTCR */
 312         cpu_openrisc_count_update(cpu);
 313         return cpu_openrisc_count_get(cpu);
 314
 315     default:
 316         break;
 317     }
 318 #endif
 319
 320     /* for rd is passed in, if rd unchanged, just keep it back.  */
 321     return rd;
 322 }