| commit | 356a2db3c6f84e8e79e5afa3913514184bff5f50 | |
| author | Tim 'mithro' Ansell <mithro@mithis.com> | |
| Tue, 18 Apr 2017 06:15:50 +0000 (18 16:15 +1000) | ||
| committer | Stafford Horne <shorne@gmail.com> | |
| Fri, 21 Apr 2017 14:55:48 +0000 (21 23:55 +0900) | ||
| tree | 08c1c57091a126f8834bb6a06f8971304b28959a | treesnapshot (tar.gz zip) |
| parent | 1d7cf18d79c85031998cc8e628414eac292ca694 | commitdiff |
target/openrisc: Implement EVBAR register
Exception Vector Base Address Register (EVBAR) - This optional register
can be used to apply an offset to the exception vector addresses.
The significant bits (31-12) of the vector offset address for each
exception depend on the setting of the Supervision Register (SR)'s EPH
bit and the Exception Vector Base Address Register (EVBAR).
Its presence is indicated by the EVBARP bit in the CPU Configuration
Register (CPUCFGR).
Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
Signed-off-by: Stafford Horne <shorne@gmail.com>
Exception Vector Base Address Register (EVBAR) - This optional register
can be used to apply an offset to the exception vector addresses.
The significant bits (31-12) of the vector offset address for each
exception depend on the setting of the Supervision Register (SR)'s EPH
bit and the Exception Vector Base Address Register (EVBAR).
Its presence is indicated by the EVBARP bit in the CPU Configuration
Register (CPUCFGR).
Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
Signed-off-by: Stafford Horne <shorne@gmail.com>
| target/openrisc/cpu.c | diffblobblamehistory | |
| target/openrisc/cpu.h | diffblobblamehistory | |
| target/openrisc/interrupt.c | diffblobblamehistory | |
| target/openrisc/sys_helper.c | diffblobblamehistory |