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target/riscv: rvv:1.0: add translation-time nan-box helper function
2021-12-20 Frank Changtarget/riscv: rvv:1.0: add translation-time nan-box...
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2021-12-20 Frank Changtarget/riscv: introduce more imm value modes in translator...
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: update check functions
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: add VMA and VTA
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: add fractional LMUL
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: remove MLEN calculations
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: check MSTATUS_VS when accessing...
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2021-12-20 Greentime Hutarget/riscv: rvv-1.0: add vlenb register
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2021-12-20 LIU Zhiweitarget/riscv: rvv-1.0: add vcsr register
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: remove rvv related codes from...
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: add translation-time vector...
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: introduce writable misa.v field
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2021-12-20 LIU Zhiweitarget/riscv: rvv-1.0: add sstatus VS field
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: set mstatus.SD bit if mstatus...
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2021-12-20 LIU Zhiweitarget/riscv: rvv-1.0: add mstatus VS field
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2021-12-20 Frank Changtarget/riscv: Use FIELD_EX32() to extract wd field
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2021-12-20 Frank Changtarget/riscv: drop vector 0.7.1 and add 1.0 support
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2021-12-20 Frank Changtarget/riscv: zfh: add Zfhmin cpu property
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2021-12-20 Frank Changtarget/riscv: zfh: implement zfhmin extension
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2021-12-20 Frank Changtarget/riscv: zfh: add Zfh cpu property
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2021-12-20 Kito Chengtarget/riscv: zfh: half-precision floating-point classify
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2021-12-20 Kito Chengtarget/riscv: zfh: half-precision floating-point compare
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2021-12-20 Kito Chengtarget/riscv: zfh: half-precision convert and move
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2021-12-20 Kito Chengtarget/riscv: zfh: half-precision computational
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2021-12-20 Kito Chengtarget/riscv: zfh: half-precision load and store
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2021-11-22 Philippe Mathieu... hw/misc/sifive_u_otp: Do not reset OTP content on hardware...
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2021-11-22 Thomas Huthhw/misc/sifive_u_otp: Use IF_PFLASH for the OTP device...
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2021-11-17 Richard Hendersonmeson.build: Merge riscv32 and riscv64 cpu family
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2021-11-17 Bin Mengtarget/riscv: machine: Sort the .subsections
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2021-10-29 Chih-Min Chaotarget/riscv: change the api for RVF/RVD fmin/fmax
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2021-10-29 Chih-Min Chaosoftfloat: add APIs to handle alternative sNaN propagation...
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2021-10-28 Alexey Baturotarget/riscv: Allow experimental J-ext to be turned on
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2021-10-28 Anatoly Parshintsevtarget/riscv: Implement address masking functions required...
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2021-10-28 Alexey Baturotarget/riscv: Support pointer masking for RISC-V for...
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2021-10-28 Alexey Baturotarget/riscv: Print new PM CSRs in QEMU logs
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2021-10-28 Alexey Baturotarget/riscv: Add J extension state description
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2021-10-28 Alexey Baturotarget/riscv: Support CSRs required for RISC-V PM extension...
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2021-10-28 Alexey Baturotarget/riscv: Add CSR defines for RISC-V PM extension
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2021-10-28 Alexey Baturotarget/riscv: Add J-extension into RISC-V
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2021-10-28 Alistair Francishw/riscv: opentitan: Fixup the PLIC context addresses
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2021-10-28 Alistair Francishw/riscv: virt: Use the PLIC config helper function
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2021-10-28 Alistair Francishw/riscv: microchip_pfsoc: Use the PLIC config helper...
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2021-10-28 Alistair Francishw/riscv: sifive_u: Use the PLIC config helper function
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2021-10-28 Alistair Francishw/riscv: boot: Add a PLIC config string function
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2021-10-28 Alistair Francishw/riscv: virt: Don't use a macro for the PLIC configuration
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2021-10-22 Bin Menghw/riscv: spike: Use MachineState::ram and MachineClass...
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2021-10-22 Bin Menghw/riscv: sifive_u: Use MachineState::ram and MachineClass...
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2021-10-22 Bin Menghw/riscv: sifive_e: Use MachineState::ram and MachineClass...
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2021-10-22 Bin Menghw/riscv: shakti_c: Use MachineState::ram and MachineClass...
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2021-10-22 Bin Menghw/riscv: opentitan: Use MachineState::ram and MachineClass...
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2021-10-22 Bin Menghw/riscv: microchip_pfsoc: Use MachineState::ram and...
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2021-10-22 Alistair Francishw/intc: sifive_plic: Cleanup the irq_request function
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-22 Alistair Francishw/intc: sifive_plic: Cleanup the realize function
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...3349b1ac794c23102ef471.1634524691.git.alistair.francis@wdc.com
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2021-10-22 Alistair Francishw/intc: sifive_plic: Move the properties
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2021-10-22 Alistair Francishw/intc: Remove the Ibex PLIC
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...1b6d21e6514e019593662e.1634524691.git.alistair.francis@wdc.com
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2021-10-22 Alistair Francishw/riscv: opentitan: Update to the latest build
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2021-10-22 Richard Hendersontarget/riscv: Compute mstatus.sd on demand
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2021-10-22 Richard Hendersontarget/riscv: Use riscv_csrrw_debug for cpu_dump
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2021-10-22 Richard Hendersontarget/riscv: Use gen_shift*_per_ol for RVB, RVI
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2021-10-22 Richard Hendersontarget/riscv: Use gen_unary_per_ol for RVB
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2021-10-22 Richard Hendersontarget/riscv: Adjust trans_rev8_32 for riscv64
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2021-10-22 Richard Hendersontarget/riscv: Use gen_arith_per_ol for RVM
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2021-10-06 Alistair Francishw/riscv: shakti_c: Mark as not user creatable
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2021-10-06 Bin Menghw/dma: sifive_pdma: Don't run DMA when channel is...
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2021-10-06 Bin Menghw/dma: sifive_pdma: Fix Control.claim bit detection
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2021-10-06 Philippe Mathieu... hw/char/mchp_pfsoc_mmuart: QOM'ify PolarFire MMUART
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2021-10-06 Philippe Mathieu... hw/char/mchp_pfsoc_mmuart: Use a MemoryRegion container
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2021-10-06 Philippe Mathieu... hw/char/mchp_pfsoc_mmuart: Simplify MCHP_PFSOC_MMUART_REG...
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2021-10-06 Bin Menghw/char: sifive_uart: Register device in 'input' category
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2021-10-06 Bin Menghw/char: shakti_uart: Register device in 'input' category
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2021-10-06 Bin Menghw/char: ibex_uart: Register device in 'input' category
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2021-10-06 Frank Changtarget/riscv: Set mstatus_hs.[SD|FS] bits if Clean...
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2021-10-06 Philipp Tomsichdisas/riscv: Add Zb[abcs] instructions
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2021-10-06 Philipp Tomsichtarget/riscv: Remove RVB (replaced by Zb[abcs])
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2021-10-06 Philipp Tomsichtarget/riscv: Add zext.h instructions to Zbb, removing...
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2021-10-06 Philipp Tomsichtarget/riscv: Add rev8 instruction, removing grev/grevi
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2021-10-06 Philipp Tomsichtarget/riscv: Add a REQUIRE_32BIT macro
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2021-10-06 Philipp Tomsichtarget/riscv: Add orc.b instruction for Zbb, removing...
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2021-10-06 Philipp Tomsichtarget/riscv: Reassign instructions to the Zbb-extension
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2021-10-06 Philipp Tomsichtarget/riscv: Add instructions of the Zbc-extension
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2021-10-06 Philipp Tomsichtarget/riscv: Reassign instructions to the Zbs-extension
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2021-10-06 Philipp Tomsichtarget/riscv: Remove shift-one instructions (proposed...
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2021-10-06 Philipp Tomsichtarget/riscv: Remove the W-form instructions from Zbs
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2021-10-06 Philipp Tomsichtarget/riscv: Reassign instructions to the Zba-extension
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-06 Philipp Tomsichtarget/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties
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2021-10-06 Philipp Tomsichtarget/riscv: clwz must ignore high bits (use shift...
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2021-10-06 Philipp Tomsichtarget/riscv: fix clzw implementation to operate on...
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2021-10-06 Philipp Tomsichtarget/riscv: Introduce temporary in gen_add_uw()
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2021-09-21 Alistair Francishw/riscv: opentitan: Correct the USB Dev address
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...17d7075b750ece3acb1535.1631767043.git.alistair.francis@wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-21 Bin Mengtarget/riscv: csr: Rename HCOUNTEREN_CY and friends
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-21 Frank Changtarget/riscv: Backup/restore mstatus.SD bit when virtual...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Bin Mengdocs/system/riscv: sifive_u: Update U-Boot instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Frank Changhw/dma: sifive_pdma: don't set Control.error if 0 bytes...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Green Wanhw/dma: sifive_pdma: allow non-multiple transaction...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Frank Changhw/dma: sifive_pdma: claim bit must be set before DMA...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Frank Changhw/dma: sifive_pdma: reset Next* registers when Control...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Anup Patelhw/riscv: virt: Add optional ACLINT support to virt...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Anup Patelhw/riscv: virt: Re-factor FDT generation
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Anup Patelhw/intc: Upgrade the SiFive CLINT implementation to...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Anup Patelhw/intc: Rename sifive_clint sources to riscv_aclint...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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AR7 emulation for QEMU