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hw/riscv: shakti_c: Mark as not user creatable
2021-09-20
Anup Pa
t
el
hw/ris
c
v: v
i
rt: Add opt
i
on
a
l ACLINT support to vi
r
t
.
.
.
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2021-09-20
Anup
P
atel
hw
/
r
iscv: virt: Re-factor FDT generat
i
on
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2021-09-20
Anup Patel
hw/intc: Upgr
a
de the SiFive CLIN
T
implementation to
.
.
.
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2021-09-20
Anu
p
P
a
tel
h
w/intc: Rena
m
e
sifive_c
l
int sources to
riscv_a
c
l
int
.
.
.
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Anup Patel
hw/riscv: sifi
v
e_
u
: Add UA
R
T1 D
T
nod
e
in the gener
a
ted D
T
B
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-11-03
Anup Patel
hw/riscv: virt: Allow pa
s
sing custom DTB
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-11-03
Anup Patel
hw/riscv: s
i
f
ive_u: Allow pa
s
sing
cust
o
m DTB
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
A
nup
Patel
hw/riscv: virt
:
Al
l
ow cre
a
ting multiple NUMA sockets
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Anup Patel
hw/risc
v
: spike: Allow c
r
ea
t
ing multiple NUMA sockets
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
A
nup Patel
hw/risc
v
: Add helpers for RISC-V mul
t
i-so
c
ket NUM
A
.
.
.
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Anup Patel
hw/riscv: Allow creating multi
p
l
e instances of PLIC
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Anup Pate
l
hw/riscv: Al
l
ow
c
reating multiple instances of C
L
I
NT
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-04-29
Anup Pa
t
el
hw/ris
c
v/spike
:
All
o
w mor
e
tha
n
one C
P
Us
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-04-29
A
n
up Patel
h
w/
r
iscv/spike: Allow
l
o
a
ding firmwa
r
e
separately using
.
.
.
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-04-29
Anup
P
atel
h
w/riscv:
A
dd option
a
l symbol callback p
t
r to riscv_load_fir
.
.
.
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-04-29
Anup Pate
l
riscv
:
Fix Stage2 SV32 page table walk
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Anup Patel
hw/riscv: Pr
o
vi
d
e rdtime call
b
ack fo
r
TCG in CL
I
NT
.
.
.
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
A
n
up Patel
target/riscv: Em
u
late TIME CSRs fo
r
p
r
i
vilege
d
mode
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-02-10
Anu
p
Patel
MA
I
NT
A
INERS: Add ma
i
ntainer entr
y
for Goldfish RTC
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-02-10
Anup Patel
riscv: v
i
rt
:
Use Goldfish R
T
C device
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-02-10
Anup Patel
hw:
rtc: Add Goldfish RT
C
device
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-02-10
Anup Patel
riscv
/
v
irt: Add syscon r
e
boot and poweroff DT n
o
d
e
s
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2018-12-20
A
nup Patel
target/riscv/pmp
.
c: Fix pmp_decode_na
p
ot(
)
Signed-off-by:
Anup Patel
<anup@brainfault.org>
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2018-12-20
A
n
up P
a
tel
sifive_u: Se
t
'cl
o
ck-fr
e
quency' DT property for SiFive
.
.
.
Signed-off-by:
Anup Patel
<anup@brainfault.org>
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2018-12-20
Anup Patel
sifiv
e
_u: Add cloc
k
D
T node
for GEM ethe
r
net
Signed-off-by:
Anup Patel
<anup@brainfault.org>
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree