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target/arm: Make M-profile VTOR loads on reset handle memory aliasing
2021-03-10
Xuzh
o
u Cheng
hw/ssi: x
i
li
n
x_spips: Remove DMA relate
d
dead codes
.
.
.
Signed-off-by:
Xuzhou Cheng
<xuzhou.cheng@windriver.com>
commit
|
commitdiff
|
tree
2021-03-10
Xuzhou Cheng
h
w/ssi: xilin
x
_spips: C
l
ean up coding conve
n
tion issues
Signed-off-by:
Xuzhou Cheng
<xuzhou.cheng@windriver.com>
commit
|
commitdiff
|
tree
2021-03-10
X
u
z
hou Cheng
h
w/arm:
x
l
nx-zynqmp: Connec
t
a
Xilinx CSU
D
MA module
.
.
.
Signed-off-by:
Xuzhou Cheng
<xuzhou.cheng@windriver.com>
commit
|
commitdiff
|
tree
2021-03-10
Xuzhou Cheng
hw/arm:
xlnx-zynqmp: Clean up c
o
ding conventi
o
n
issues
Signed-off-by:
Xuzhou Cheng
<xuzhou.cheng@windriver.com>
commit
|
commitdiff
|
tree
2021-03-08
Xuzhou Cheng
hw/dma: Im
p
lement a
X
ilinx
C
S
U
DMA
m
odel
Signed-off-by:
Xuzhou Cheng
<xuzhou.cheng@windriver.com>
commit
|
commitdiff
|
tree
2021-02-02
Xuzhou Cheng
hw
/
ssi: imx_s
p
i:
D
i
sabl
e
c
hip
se
l
ects when control
l
er
.
.
.
Signed-off-by:
Xuzhou Cheng
<xuzhou.cheng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-16
X
u
zh
o
u
Cheng
hw/block: m
2
5p80: Im
p
lement AAI-WP
com
m
a
nd support
.
.
.
Signed-off-by:
Xuzhou Cheng
<xuzhou.cheng@windriver.com>
commit
|
commitdiff
|
tree