| commit | d6bafaf45c5ff31ad7d7d87c3c3d37ae675684cc | |
| author | Xuzhou Cheng <xuzhou.cheng@windriver.com> | |
| Wed, 3 Mar 2021 13:52:54 +0000 (3 21:52 +0800) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Wed, 10 Mar 2021 13:54:51 +0000 (10 13:54 +0000) | ||
| tree | 11d351da4584db126b023c018a58a85263ffa741 | treesnapshot (tar.gz zip) |
| parent | 3754eed4206f2472b5f4e4c3d84a1d39f0cd5d7c | commitdiff |
hw/ssi: xilinx_spips: Remove DMA related dead codes from zynqmp_spips
Now that the Xilinx CSU DMA model is implemented, the existing
DMA related dead codes in the ZynqMP QSPI are useless and should
be removed. The maximum register number is also updated to only
include the QSPI registers.
Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20210303135254.3970-6-bmeng.cn@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Now that the Xilinx CSU DMA model is implemented, the existing
DMA related dead codes in the ZynqMP QSPI are useless and should
be removed. The maximum register number is also updated to only
include the QSPI registers.
Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20210303135254.3970-6-bmeng.cn@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| hw/ssi/xilinx_spips.c | diffblobblamehistory | |
| include/hw/ssi/xilinx_spips.h | diffblobblamehistory |