| commit | 668351a54883b6283e7ae94daf4d4eca1a071158 | |
| author | Xuzhou Cheng <xuzhou.cheng@windriver.com> | |
| Wed, 3 Mar 2021 13:52:52 +0000 (3 21:52 +0800) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Wed, 10 Mar 2021 13:54:51 +0000 (10 13:54 +0000) | ||
| tree | d44541fb944bcb9d809bf9df774a141072f88dd2 | treesnapshot (tar.gz zip) |
| parent | 21bce3717e2cb70e3bea06e8684bae111c9f4dda | commitdiff |
hw/arm: xlnx-zynqmp: Connect a Xilinx CSU DMA module for QSPI
Add a Xilinx CSU DMA module to ZynqMP SoC, and connent the stream
link of GQSPI to CSU DMA.
Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20210303135254.3970-4-bmeng.cn@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Add a Xilinx CSU DMA module to ZynqMP SoC, and connent the stream
link of GQSPI to CSU DMA.
Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20210303135254.3970-4-bmeng.cn@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| hw/arm/Kconfig | diffblobblamehistory | |
| hw/arm/xlnx-zynqmp.c | diffblobblamehistory | |
| include/hw/arm/xlnx-zynqmp.h | diffblobblamehistory |