2021-09-01 | LIU Zhiwei | target/riscv: Add User CSRs read-only check Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-01 | LIU Zhiwei | target/riscv: Don't wrongly override isa version Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-01 | Bin Meng | target/riscv: Correct a comment in riscv_csrrw() Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-01 | Bin Meng | hw/riscv: virt: Move flash node to root Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-01 | Vijai Kumar K | hw/char: Add config for shakti uart Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-07-14 | Alistair Francis | hw/riscv/boot: Check the error of fdt_pack() Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...9f76094e4bc5296e0643b9.1626303527.git.alistair.francis@wdc.com |
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2021-07-14 | Alistair Francis | hw/riscv: opentitan: Add the flash alias Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...877b8ea4d6dcfce60db5e9.1625801868.git.alistair.francis@wdc.com |
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2021-07-14 | Alistair Francis | hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...6a32fd79b70fecfb54ff82.1625801868.git.alistair.francis@wdc.com |
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2021-07-14 | Alistair Francis | char: ibex_uart: Update the register layout Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...a862c8a5092f8a9e3f9928.1625801868.git.alistair.francis@wdc.com |
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2021-07-14 | Bin Meng | hw/riscv: sifive_u: Make sure firmware info is 8-byte... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-07-14 | Bin Meng | hw/riscv: sifive_u: Correct the CLINT timebase frequency Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-07-14 | Bin Meng | docs/system: riscv: Update Microchip Icicle Kit for... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-07-14 | Jose Martins | target/riscv: hardwire bits in hideleg and hedeleg Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-07-14 | Bin Meng | docs/system: riscv: Add documentation for virt machine Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-07-14 | Bin Meng | docs/system: riscv: Fix CLINT name in the sifive_u doc Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-07-14 | Bin Meng | target/riscv: csr: Remove redundant check in fp csr... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-07-14 | Bin Meng | target/riscv: pmp: Fix some typos Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-24 | Alistair Francis | hw/riscv: OpenTitan: Connect the mtime and mtimecmp... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...b8db1264b840b56ef2a929.1624001156.git.alistair.francis@wdc.com |
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2021-06-24 | Alistair Francis | hw/timer: Initial commit of Ibex Timer Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...a2c46fe69467d013c03147.1624001156.git.alistair.francis@wdc.com |
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2021-06-24 | Alistair Francis | hw/char/ibex_uart: Make the register layout private Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...0387a3ba2fad7d116a4986.1624001156.git.alistair.francis@wdc.com |
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2021-06-24 | Lukas Jünger | hw/char: QOMify sifive_uart Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-24 | Lukas Jünger | hw/char: Consistent function names for sifive_uart Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-24 | Bin Meng | target/riscv: gdbstub: Fix dynamic CSR XML generation Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-24 | Alistair Francis | target/riscv: Use target_ulong for the DisasContext... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...e3eec320b6a683ab56f705.1622435221.git.alistair.francis@wdc.com |
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2021-06-07 | Frank Chang | target/riscv: rvb: add b-ext version cpu option Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-07 | Kito Cheng | target/riscv: rvb: support and turn on B-extension... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-07 | Kito Cheng | target/riscv: rvb: add/shift with prefix zero-extend Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-07 | Kito Cheng | target/riscv: rvb: address calculation Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-07 | Frank Chang | target/riscv: rvb: generalized or-combine Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-07 | Frank Chang | target/riscv: rvb: generalized reverse Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-07 | Kito Cheng | target/riscv: rvb: rotate (left/right) Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-07 | Kito Cheng | target/riscv: rvb: shift ones Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-07 | Frank Chang | target/riscv: rvb: single-bit instructions Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-07 | Frank Chang | target/riscv: add gen_shifti() and gen_shiftiw() helper... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-07 | Kito Cheng | target/riscv: rvb: sign-extend instructions Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-07 | Kito Cheng | target/riscv: rvb: min/max instructions Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-07 | Kito Cheng | target/riscv: rvb: pack two words into one register Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-07 | Kito Cheng | target/riscv: rvb: logic-with-negate Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-07 | Frank Chang | target/riscv: rvb: count bits set Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-07 | Kito Cheng | target/riscv: rvb: count leading/trailing zeros Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-07 | Kito Cheng | target/riscv: reformat @sh format encoding for B-extension Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-07 | LIU Zhiwei | target/riscv: Pass the same value to oprsz and maxsz. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-07 | Alistair Francis | target/riscv/pmp: Add assert for ePMP operations Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...8c82fcb1f6805ee61dde82.1621550996.git.alistair.francis@wdc.com |
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2021-06-07 | Changbin Du | target/riscv: Dump CSR mscratch/sscratch/satp Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-07 | Bin Meng | target/riscv: Remove unnecessary riscv_*_names[] declaration Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-07 | Philippe Mathieu... | target/riscv: Do not include 'pmp.h' in user emulation Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-07 | Alistair Francis | docs/system: Move the RISC-V -bios information to removed Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...bb8926d85fe1d35e48ea5b.1620081256.git.alistair.francis@wdc.com |
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2021-06-07 | Jose Martins | target/riscv: fix wfi exception behavior Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-07 | Bin Meng | hw/riscv: microchip_pfsoc: Support direct kernel boot Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-07 | Bin Meng | hw/riscv: Use macros for BIOS image names Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-07 | Bin Meng | docs/system/riscv: sifive_u: Document '-dtb' usage Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-07 | Bin Meng | docs/system/riscv: Correct the indentation level of... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-07 | Bin Meng | hw/riscv: Support the official PLIC DT bindings Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-07 | Bin Meng | hw/riscv: Support the official CLINT DT bindings Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-07 | Bin Meng | hw/riscv: virt: Switch to use qemu_fdt_setprop_string_array... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-07 | Bin Meng | hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_ar... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-05-11 | Alistair Francis | target/riscv: Fix the RV64H decode comment Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...4b253512428c4baca7e4ba.1619234854.git.alistair.francis@wdc.com |
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2021-05-11 | Alistair Francis | target/riscv: Consolidate RV32/64 16-bit instructions Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...ebf133c2cde6a7a37224d7.1619234854.git.alistair.francis@wdc.com |
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2021-05-11 | Alistair Francis | target/riscv: Consolidate RV32/64 32-bit instructions Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...c6483ab973fe4791aefa77.1619234854.git.alistair.francis@wdc.com |
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2021-05-11 | Alistair Francis | target/riscv: Remove an unused CASE_OP_32_64 macro Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...0120c74ad892f60cec35ff.1619234854.git.alistair.francis@wdc.com |
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2021-05-11 | Alistair Francis | target/riscv: Remove the unused HSTATUS_WPRI macro Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...822958f04dfc732d7beb7e.1619234854.git.alistair.francis@wdc.com |
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2021-05-11 | Alistair Francis | target/riscv: Remove the hardcoded SATP_MODE macro Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...1739334198e36a64fe04df.1619234854.git.alistair.francis@wdc.com |
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2021-05-11 | Alistair Francis | target/riscv: Remove the hardcoded MSTATUS_SD macro Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...817c9dd6068dc36478fc53.1619234854.git.alistair.francis@wdc.com |
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2021-05-11 | Alistair Francis | target/riscv: Remove the hardcoded HGATP_MODE macro Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...265004b07de7489c77a766.1619234854.git.alistair.francis@wdc.com |
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2021-05-11 | Alistair Francis | target/riscv: Remove the hardcoded SSTATUS_SD macro Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...172790f5b5fc058b40f2f1.1619234854.git.alistair.francis@wdc.com |
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2021-05-11 | Alistair Francis | target/riscv: Remove the hardcoded RVXLEN macro Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...4f93cbc5d0acc31ed3344a.1619234854.git.alistair.francis@wdc.com |
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2021-05-11 | Emmanuel Blot | target/riscv: fix a typo with interrupt names Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-05-11 | Frank Chang | fpu/softfloat: set invalid excp flag for RISC-V muladd... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-05-11 | Alexander Wagner | hw/riscv: Fix OT IBEX reset vector Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-05-11 | Emmanuel Blot | target/riscv: fix exception index on instruction access... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-05-11 | Frank Chang | target/riscv: fix vrgather macro index variable type bug Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-05-11 | Alistair Francis | target/riscv: Add ePMP support for the Ibex CPU Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...2e989dbe416e417a551fd1.1618812899.git.alistair.francis@wdc.com |
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2021-05-11 | Alistair Francis | target/riscv/pmp: Remove outdated comment Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...9a78fdba85280cab4dd27f.1618812899.git.alistair.francis@wdc.com |
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2021-05-11 | Hou Weiying | target/riscv: Add a config option for ePMP Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...35d3b323f966623f8af020.1618812899.git.alistair.francis@wdc.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-05-11 | Hou Weiying | target/riscv: Implementation of enhanced PMP (ePMP) Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...4e7c98b168bdec5d297bb1.1618812899.git.alistair.francis@wdc.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-05-11 | Hou Weiying | target/riscv: Add ePMP CSR access functions Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...eeb99a774cf49f7da9cc32.1618812899.git.alistair.francis@wdc.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-05-11 | Alistair Francis | target/riscv: Add the ePMP feature Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...c3ae009f5467e2b3960ce0.1618812899.git.alistair.francis@wdc.com |
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2021-05-11 | Hou Weiying | target/riscv: Define ePMP mseccfg Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...d4f930136d2d7fd7f99c78.1618812899.git.alistair.francis@wdc.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-05-11 | Alistair Francis | target/riscv: Fix the PMP is locked check when using TOR Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...89bd59c59990247265b0c6.1618812899.git.alistair.francis@wdc.com |
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2021-05-11 | Vijai Kumar K | docs: Add documentation for shakti_c machine Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-05-11 | LIU Zhiwei | target/riscv: Fixup saturate subtract function Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-05-11 | Jade Fink | riscv: don't look at SUM when accessing memory from... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-05-11 | Alistair Francis | hw/riscv: Enable VIRTIO_VGA for RISC-V virt machine Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...0640f3233f8ad1ab270e1e.1617367317.git.alistair.francis@wdc.com |
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2021-05-11 | Alistair Francis | hw/opentitan: Update the interrupt layout Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...10da2e9f23c414db5a6960.1617202791.git.alistair.francis@wdc.com |
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2021-05-11 | Alistair Francis | MAINTAINERS: Update the RISC-V CPU Maintainers Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...d28f43be69d8eb5cf4b56b.1617749142.git.alistair.francis@wdc.com |
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2021-05-11 | Alistair Francis | target/riscv: Use RISCVException enum for CSR access Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...11b351b5c9f43039ca8ea3.1617290165.git.alistair.francis@wdc.com |
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2021-05-11 | Alistair Francis | target/riscv: Use the RISCVException enum for CSR operations Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...ae8fc2429f906a459f17ce.1617290165.git.alistair.francis@wdc.com |
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2021-05-11 | Alistair Francis | target/riscv: Fix 32-bit HS mode access permissions Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...ce3cf4f6622588f9c09149.1617290165.git.alistair.francis@wdc.com |
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2021-05-11 | Alistair Francis | target/riscv: Use the RISCVException enum for CSR predicates Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...5aa482adb2a558c02a7cad.1617290165.git.alistair.francis@wdc.com |
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2021-05-11 | Alistair Francis | target/riscv: Convert the RISC-V exceptions to an enum Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...e743a7c7f824d68879a527.1617290165.git.alistair.francis@wdc.com |
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2021-05-11 | Vijai Kumar K | hw/riscv: Connect Shakti UART to Shakti platform Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-05-11 | Vijai Kumar K | hw/char: Add Shakti UART emulation Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-05-11 | Vijai Kumar K | riscv: Add initial support for Shakti C machine Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-05-11 | Vijai Kumar K | target/riscv: Add Shakti C class CPU Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-05-11 | Bin Meng | hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[] Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-05-11 | Dylan Jhong | target/riscv: Align the data type of reset vector address Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-05-11 | Axel Heider | docs/system/generic-loader.rst: Fix style Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-05-11 | Atish Patra | target/riscv: Remove privilege v1.9 specific CSR related... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-23 | Georg Kotheimer | target/riscv: Prevent lost illegal instruction exceptions Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-23 | Bin Meng | docs/system: riscv: Add documentation for 'microchip... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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