target/riscv: hardwire bits in hideleg and hedeleg
commitbc083a51cafff73ad6113fcc81f2f40639d7c8c6
authorJose Martins <josemartins90@gmail.com>
Sat, 22 May 2021 15:59:02 +0000 (22 16:59 +0100)
committerAlistair Francis <alistair.francis@wdc.com>
Wed, 14 Jul 2021 22:56:00 +0000 (15 08:56 +1000)
treea9be349b019217791b6bbf3f7a73af4b46b7f380
parent85198f189e41c9d9ebe340d2feecf7d668499bc4
target/riscv: hardwire bits in hideleg and hedeleg

The specification mandates for certain bits to be hardwired in the
hypervisor delegation registers. This was not being enforced.

Signed-off-by: Jose Martins <josemartins90@gmail.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210522155902.374439-1-josemartins90@gmail.com
[ Changes by AF:
 - Improve indentation
 - Convert delegable_excps to a #define to avoid failures with GCC 8
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/csr.c