| 2019-06-27 | Bin Meng | riscv: sifive_u: Do not create hard-coded phandles... Signed-off-by: Bin Meng <bmeng.cn@gmail.com> |
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| 2019-06-24 | Bin Meng | riscv: virt: Correct pci "bus-range" encoding Signed-off-by: Bin Meng <bmeng.cn@gmail.com> |
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| 2019-03-19 | Bin Meng | riscv: sifive_u: Correct UART0's IRQ in the device... Signed-off-by: Bin Meng <bmeng.cn@gmail.com> |
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| 2019-03-19 | Bin Meng | riscv: sifive_uart: Generate TX interrupt Signed-off-by: Bin Meng <bmeng.cn@gmail.com> |
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