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opensbi: Upgrade from v0.4 to v0.5
2019-11-14 Alistair Francisopensbi: Upgrade from v0.4 to v0.5
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-11-14 Alistair Francistarget/riscv: Remove atomic accesses to MIP CSR
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-10-28 Alistair Francisriscv/boot: Fix possible memory leak
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-10-28 Alistair Francisriscv/virt: Jump to pflash if specified
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-10-28 Alistair Francisriscv/virt: Add the PFlash CFI01 device
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-10-28 Alistair Francisriscv/virt: Manually define the machine
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-10-28 Alistair Francisriscv/sifive_u: Add the start-in-flash property
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-10-28 Alistair Francisriscv/sifive_u: Manually define the machine
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-10-28 Alistair Francisriscv/sifive_u: Add QSPI memory region
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-10-28 Alistair Francisriscv/sifive_u: Add L2-LIM cache memory
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-09-17 Alistair Francistarget/riscv: Use TB_FLAGS_MSTATUS_FS for floating...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-09-17 Alistair Francistarget/riscv: Fix mstatus dirty mask
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-09-17 Alistair Francistarget/riscv: Update the Hypervisor CSRs to v0.4
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-09-17 Alistair Francistarget/riscv: Create function to test if FP is enabled
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-09-17 Alistair Francisriscv: plic: Remove unused interrupt functions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-07-26 Alistair Francisriscv/boot: Fixup the RISC-V firmware warning
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-07-18 Alistair Francishw/riscv: Load OpenSBI as the default firmware
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-07-18 Alistair Francisroms: Add OpenSBI version 0.4
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-07-09 Alistair Francistcg/riscv: Fix RISC-VH host build failure
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...5c4aa0aa8a52847af70c0f.1561039316.git.alistair.francis@wdc.com>
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2019-06-27 Alistair Francishw/riscv: Extend the kernel loading support
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-06-27 Alistair Francishw/riscv: Add support for loading a firmware
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-06-27 Alistair Francishw/riscv: Split out the boot functions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-06-25 Alistair Francistarget/riscv: Add support for disabling/enabling Counters
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-06-25 Alistair Francistarget/riscv: Remove user version information
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-06-25 Alistair Francistarget/riscv: Require either I or E base extension
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-06-25 Alistair Francisqemu-deprecated.texi: Deprecate the RISC-V privledge...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-06-25 Alistair Francistarget/riscv: Set privledge spec 1.11.0 as default
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-06-25 Alistair Francistarget/riscv: Add the mcountinhibit CSR
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-06-24 Alistair Francistarget/riscv: Add the privledge spec version 1.11.0
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-06-24 Alistair Francistarget/riscv: Restructure deprecatd CPUs
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-06-24 Alistair Francistarget/riscv: Allow setting ISA extensions via CPU...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-05-24 Alistair Francistarget/riscv: Add the HGATP register masks
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-05-24 Alistair Francistarget/riscv: Add the HSTATUS register masks
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-05-24 Alistair Francistarget/riscv: Add Hypervisor CSR macros
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-05-24 Alistair Francistarget/riscv: Allow setting mstatus virtulisation bits
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-05-24 Alistair Francistarget/riscv: Add the MPV and MTL mstatus bits
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-05-24 Alistair Francistarget/riscv: Improve the scause logic
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-05-24 Alistair Francistarget/riscv: Trigger interrupt on MIP update asynchronously
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-05-24 Alistair Francistarget/riscv: Mark privilege level 2 as reserved
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-05-24 Alistair Francisriscv: spike: Add a generic spike machine
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-05-24 Alistair Francistarget/riscv: Deprecate the generic no MMU CPUs
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-05-24 Alistair Francistarget/riscv: Add a base 32 and 64 bit CPU
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-05-24 Alistair Francistarget/riscv: Create settable CPU properties
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-05-24 Alistair Francisriscv: virt: Allow specifying a CPU via commandline
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-05-24 Alistair Francislinux-user/riscv: Add the CPU type as a comment
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-05-23 Alistair Francistarget/arm: Fix vector operation segfault
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...4087e476f7df5b04d42ddb.1558021877.git.alistair.francis@wdc.com
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2019-05-09 Alistair Francislinux-user/elfload: Fix GCC 9 build warnings
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...00b91361af9302823a72a9.1556666645.git.alistair.francis@wdc.com>
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2019-04-04 Alistair Francisriscv: plic: Log guest errors
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-04-04 Alistair Francisriscv: plic: Fix incorrect irq calculation
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-03-27 Alistair FrancisMAINTAINERS: Update the device tree maintainers
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-03-19 Alistair Francistarget/riscv: Remove unused struct
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-03-19 Alistair Francisriscv: sifive_u: Allow up to 4 CPUs to be created
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-03-19 Alistair Francisriscv: pmp: Log pmp access errors as guest errors
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-03-18 Alistair Francisriscv: plic: Set msi_nonbroken as true
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...159b0f4a4fc0d95c050660.1552679970.git.alistair.francis@wdc.com>
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2019-02-11 Alistair Francisriscv: Ensure the kernel start address is correctly...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-02-11 Alistair FrancisRISC-V: Add priv_ver to DisasContext
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2019-01-10 Alistair Francisdefault-configs: Enable USB support for RISC-V machines
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2018-12-25 Alistair Francisconfigure: Add support for building RISC-V host
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...c43a412fa3e74ddd6277fb.1545246859.git.alistair.francis@wdc.com>
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2018-12-25 Alistair Francisdisas: Add RISC-V support
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...4bb9582017cdf0ea192208.1545246859.git.alistair.francis@wdc.com>
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2018-12-25 Alistair Francistcg: Add RISC-V cpu signal handler
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...fd862a55628907f0093194.1545246859.git.alistair.francis@wdc.com>
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2018-12-25 Alistair Francistcg/riscv: Add the target init code
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...8fd91f904f6de26ab5d697.1545246859.git.alistair.francis@wdc.com>
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2018-12-25 Alistair Francistcg/riscv: Add the prologue generation and register...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...8d1eabdf5de6c0e8f8c228.1545246859.git.alistair.francis@wdc.com>
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2018-12-25 Alistair Francistcg/riscv: Add the out op decoder
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...0456e0704b4076a5d943ab.1545246859.git.alistair.francis@wdc.com>
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2018-12-25 Alistair Francistcg/riscv: Add direct load and store instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...cda024c095e29b0ac4c43e.1545246859.git.alistair.francis@wdc.com>
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2018-12-25 Alistair Francistcg/riscv: Add slowpath load and store instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...2c5efa5c07c9be17efdec6.1545246859.git.alistair.francis@wdc.com>
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2018-12-25 Alistair Francistcg/riscv: Add branch and jump instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...b5b012b7e21e4efbbe83f3.1545246859.git.alistair.francis@wdc.com>
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2018-12-25 Alistair Francistcg/riscv: Add the add2 and sub2 instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...5e8e98fdab898853af37b8.1545246859.git.alistair.francis@wdc.com>
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2018-12-25 Alistair Francistcg/riscv: Add the out load and store instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...368bbdbd18815d59cef6a0.1545246859.git.alistair.francis@wdc.com>
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2018-12-25 Alistair Francistcg/riscv: Add the extract instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...8cf3205fcedbb9a5fa411f.1545246859.git.alistair.francis@wdc.com>
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2018-12-25 Alistair Francistcg/riscv: Add the mov and movi instruction
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...a2fe590a6bb8ee422b9683.1545246859.git.alistair.francis@wdc.com>
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2018-12-25 Alistair Francistcg/riscv: Add the relocation functions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...e9a3b8b47ee9f7b3711494.1545246859.git.alistair.francis@wdc.com>
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2018-12-25 Alistair Francistcg/riscv: Add the instruction emitters
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...9cf3ce7b9e8b9d431ca694.1545246859.git.alistair.francis@wdc.com>
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2018-12-25 Alistair Francistcg/riscv: Add the immediate encoders
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...d53869de2dbb59b111c7ca.1545246859.git.alistair.francis@wdc.com>
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2018-12-25 Alistair Francistcg/riscv: Add support for the constraints
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...3f72d47ccf98f1cc612b8a.1545246859.git.alistair.francis@wdc.com>
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2018-12-25 Alistair Francistcg/riscv: Add the tcg target registers
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...bc9439820d0e7701f2d47e.1545246859.git.alistair.francis@wdc.com>
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2018-12-25 Alistair Francistcg/riscv: Add the tcg-target.h file
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...93a519d4d654da27785254.1545246859.git.alistair.francis@wdc.com>
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2018-12-25 Alistair Francisexec: Add RISC-V GCC poison macro
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...f8dc69ac93d1eb63df949c.1545246859.git.alistair.francis@wdc.com>
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2018-12-25 Alistair Francislinux-user: Add host dependency for RISC-V 64-bit
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...4f3834dcfc3bd28e052ccd.1545246859.git.alistair.francis@wdc.com>
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2018-12-25 Alistair Francislinux-user: Add host dependency for RISC-V 32-bit
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...e883e897dec8cfef669799.1545246859.git.alistair.francis@wdc.com>
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2018-12-25 Alistair Franciself.h: Add the RISCV ELF magic numbers
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...396bee5afd3d327941f0c9.1545246859.git.alistair.francis@wdc.com>
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2018-12-20 Alistair Francisriscv: Enable VGA and PCIE_VGA
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2018-12-20 Alistair Francishw/riscv/virt: Connect the gpex PCIe
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2018-12-20 Alistair Francishw/riscv/virt: Adjust memory layout spacing
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2018-12-20 Alistair Francishw/riscv/virt: Increase the number of interrupts
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2018-12-17 Alistair Francistcg/mips: Improve the add2/sub2 command to use TCG_TARGET_RE...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...aa79011ddb342c3cc17ec3.1544648105.git.alistair.francis@wdc.com>
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2018-11-13 Alistair Francishw/riscv/virt: Free the test device tree node name
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2018-11-08 Alistair Francisriscv: spike: Fix memory leak in the board init
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2018-09-05 Alistair Francishw/riscv/spike: Set the soc device tree node as a simple-bus
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2018-09-05 Alistair Francishw/riscv/virtio: Set the soc device tree node as a...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2018-07-19 Alistair Francisspike: Fix crash when introspecting the device
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2018-07-19 Alistair Francisriscv_hart: Fix crash when introspecting the device
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2018-07-19 Alistair Francisvirt: Fix crash when introspecting the device
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2018-07-19 Alistair Francissifive_u: Fix crash when introspecting the device
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2018-07-19 Alistair Francissifive_e: Fix crash when introspecting the device
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2018-07-05 Alistair Francishw/riscv/sifive_u: Connect the Cadence GEM Ethernet...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2018-07-05 Alistair Francishw/riscv/sifive_u: Move the uart device tree node under...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2018-07-05 Alistair Francishw/riscv/sifive_u: Set the interrupt controller number...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2018-07-05 Alistair Francishw/riscv/sifive_u: Set the soc device tree node as...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2018-07-05 Alistair Francishw/riscv/sifive_plic: Use gpios instead of irqs
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2018-07-05 Alistair Francishw/riscv/sifive_e: Create a SiFive E SoC object
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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AR7 emulation for QEMU