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target/riscv: Expose interrupt pending bits as GPIO lines
2021-09-20 Alistair Francistarget/riscv: Expose interrupt pending bits as GPIO...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...5a44e73f6442b11c703c53.1630301632.git.alistair.francis@wdc.com
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2021-09-20 LIU Zhiweitarget/riscv: Fix satp write
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Alistair Francistarget/riscv: Update the ePMP CSR address
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...0e63d113885c98586053f3.1630543194.git.alistair.francis@wdc.com
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2021-09-01 Richard Hendersontarget/riscv: Use {get,dest}_gpr for RVV
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Richard Hendersontarget/riscv: Tidy trans_rvh.c.inc
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Richard Hendersontarget/riscv: Use {get,dest}_gpr for RVD
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Richard Hendersontarget/riscv: Use {get,dest}_gpr for RVF
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Richard Hendersontarget/riscv: Use gen_shift_imm_fn for slli_uw
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2021-09-01 Richard Hendersontarget/riscv: Use {get,dest}_gpr for RVA
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2021-09-01 Richard Hendersontarget/riscv: Reorg csr instructions
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2021-09-01 Richard Hendersontarget/riscv: Fix hgeie, hgeip
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2021-09-01 Richard Hendersontarget/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write...
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2021-09-01 Richard Hendersontarget/riscv: Use {get, dest}_gpr for integer load...
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2021-09-01 Richard Hendersontarget/riscv: Use get_gpr in branches
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2021-09-01 Richard Hendersontarget/riscv: Use extracts for sraiw and srliw
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2021-09-01 Richard Hendersontarget/riscv: Use DisasExtend in shift operations
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2021-09-01 Richard Hendersontarget/riscv: Add DisasExtend to gen_unary
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2021-09-01 Richard Hendersontarget/riscv: Move gen_* helpers for RVB
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2021-09-01 Richard Hendersontarget/riscv: Move gen_* helpers for RVM
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2021-09-01 Richard Hendersontarget/riscv: Use gen_arith for mulh and mulhu
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2021-09-01 Richard Hendersontarget/riscv: Remove gen_arith_div*
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2021-09-01 Richard Hendersontarget/riscv: Add DisasExtend to gen_arith*
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2021-09-01 Richard Hendersontarget/riscv: Introduce DisasExtend and new helpers
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2021-09-01 Richard Hendersontarget/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr
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2021-09-01 Richard Hendersontarget/riscv: Clean up division helpers
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Richard Hendersontests/tcg/riscv64: Add test for division
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Richard Hendersontarget/riscv: Use tcg_constant_*
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Joe Komlodihw/registerfields: Use 64-bit bitfield for FIELD_DP64
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Joe Komlodihw/core/register: Add more 64-bit utilities
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 David Hoppenbrouwershw/intc/sifive_clint: Fix muldiv64 overflow in sifive_clint_...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Peter Maydellhw/riscv/virt.c: Assemble plic_hart_config string with...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 LIU Zhiweitarget/riscv: Add User CSRs read-only check
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 LIU Zhiweitarget/riscv: Don't wrongly override isa version
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Bin Mengtarget/riscv: Correct a comment in riscv_csrrw()
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Bin Menghw/riscv: virt: Move flash node to root
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Vijai Kumar Khw/char: Add config for shakti uart
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-07-14 Alistair Francishw/riscv/boot: Check the error of fdt_pack()
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...9f76094e4bc5296e0643b9.1626303527.git.alistair.francis@wdc.com
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2021-07-14 Alistair Francishw/riscv: opentitan: Add the flash alias
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...877b8ea4d6dcfce60db5e9.1625801868.git.alistair.francis@wdc.com
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2021-07-14 Alistair Francishw/riscv: opentitan: Add the unimplement rv_core_ibex_peri
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...6a32fd79b70fecfb54ff82.1625801868.git.alistair.francis@wdc.com
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2021-07-14 Alistair Francischar: ibex_uart: Update the register layout
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...a862c8a5092f8a9e3f9928.1625801868.git.alistair.francis@wdc.com
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2021-07-14 Bin Menghw/riscv: sifive_u: Make sure firmware info is 8-byte...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-07-14 Bin Menghw/riscv: sifive_u: Correct the CLINT timebase frequency
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-07-14 Bin Mengdocs/system: riscv: Update Microchip Icicle Kit for...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-07-14 Jose Martinstarget/riscv: hardwire bits in hideleg and hedeleg
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-07-14 Bin Mengdocs/system: riscv: Add documentation for virt machine
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-07-14 Bin Mengdocs/system: riscv: Fix CLINT name in the sifive_u doc
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-07-14 Bin Mengtarget/riscv: csr: Remove redundant check in fp csr...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-07-14 Bin Mengtarget/riscv: pmp: Fix some typos
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-24 Alistair Francishw/riscv: OpenTitan: Connect the mtime and mtimecmp...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...b8db1264b840b56ef2a929.1624001156.git.alistair.francis@wdc.com
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2021-06-24 Alistair Francishw/timer: Initial commit of Ibex Timer
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...a2c46fe69467d013c03147.1624001156.git.alistair.francis@wdc.com
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2021-06-24 Alistair Francishw/char/ibex_uart: Make the register layout private
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...0387a3ba2fad7d116a4986.1624001156.git.alistair.francis@wdc.com
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2021-06-24 Lukas Jüngerhw/char: QOMify sifive_uart
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-24 Lukas Jüngerhw/char: Consistent function names for sifive_uart
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-24 Bin Mengtarget/riscv: gdbstub: Fix dynamic CSR XML generation
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-24 Alistair Francistarget/riscv: Use target_ulong for the DisasContext...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...e3eec320b6a683ab56f705.1622435221.git.alistair.francis@wdc.com
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2021-06-07 Frank Changtarget/riscv: rvb: add b-ext version cpu option
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Kito Chengtarget/riscv: rvb: support and turn on B-extension...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Kito Chengtarget/riscv: rvb: add/shift with prefix zero-extend
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Kito Chengtarget/riscv: rvb: address calculation
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Frank Changtarget/riscv: rvb: generalized or-combine
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Frank Changtarget/riscv: rvb: generalized reverse
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Kito Chengtarget/riscv: rvb: rotate (left/right)
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Kito Chengtarget/riscv: rvb: shift ones
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Frank Changtarget/riscv: rvb: single-bit instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Frank Changtarget/riscv: add gen_shifti() and gen_shiftiw() helper...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Kito Chengtarget/riscv: rvb: sign-extend instructions
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Kito Chengtarget/riscv: rvb: min/max instructions
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2021-06-07 Kito Chengtarget/riscv: rvb: pack two words into one register
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2021-06-07 Kito Chengtarget/riscv: rvb: logic-with-negate
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Frank Changtarget/riscv: rvb: count bits set
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Kito Chengtarget/riscv: rvb: count leading/trailing zeros
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Kito Chengtarget/riscv: reformat @sh format encoding for B-extension
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 LIU Zhiweitarget/riscv: Pass the same value to oprsz and maxsz.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Alistair Francistarget/riscv/pmp: Add assert for ePMP operations
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...8c82fcb1f6805ee61dde82.1621550996.git.alistair.francis@wdc.com
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2021-06-07 Changbin Dutarget/riscv: Dump CSR mscratch/sscratch/satp
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Bin Mengtarget/riscv: Remove unnecessary riscv_*_names[] declaration
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Philippe Mathieu... target/riscv: Do not include 'pmp.h' in user emulation
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Alistair Francisdocs/system: Move the RISC-V -bios information to removed
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...bb8926d85fe1d35e48ea5b.1620081256.git.alistair.francis@wdc.com
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2021-06-07 Jose Martinstarget/riscv: fix wfi exception behavior
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Bin Menghw/riscv: microchip_pfsoc: Support direct kernel boot
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Bin Menghw/riscv: Use macros for BIOS image names
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Bin Mengdocs/system/riscv: sifive_u: Document '-dtb' usage
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Bin Mengdocs/system/riscv: Correct the indentation level of...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Bin Menghw/riscv: Support the official PLIC DT bindings
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Bin Menghw/riscv: Support the official CLINT DT bindings
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Bin Menghw/riscv: virt: Switch to use qemu_fdt_setprop_string_array...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Bin Menghw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_ar...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Fix the RV64H decode comment
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...4b253512428c4baca7e4ba.1619234854.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Consolidate RV32/64 16-bit instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...ebf133c2cde6a7a37224d7.1619234854.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Consolidate RV32/64 32-bit instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...c6483ab973fe4791aefa77.1619234854.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Remove an unused CASE_OP_32_64 macro
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...0120c74ad892f60cec35ff.1619234854.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Remove the unused HSTATUS_WPRI macro
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...822958f04dfc732d7beb7e.1619234854.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Remove the hardcoded SATP_MODE macro
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...1739334198e36a64fe04df.1619234854.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Remove the hardcoded MSTATUS_SD macro
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...817c9dd6068dc36478fc53.1619234854.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Remove the hardcoded HGATP_MODE macro
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...265004b07de7489c77a766.1619234854.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Remove the hardcoded SSTATUS_SD macro
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...172790f5b5fc058b40f2f1.1619234854.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Remove the hardcoded RVXLEN macro
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...4f93cbc5d0acc31ed3344a.1619234854.git.alistair.francis@wdc.com
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2021-05-11 Emmanuel Blottarget/riscv: fix a typo with interrupt names
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Frank Changfpu/softfloat: set invalid excp flag for RISC-V muladd...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alexander Wagnerhw/riscv: Fix OT IBEX reset vector
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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AR7 emulation for QEMU