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target/riscv: Use the RISCVException enum for CSR predicates
2020-12-18
Anup Patel
hw/riscv:
sifive
_
u: Add UART1 DT no
d
e in t
h
e generated DTB
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-11-03
Anup Patel
hw/ri
s
cv
:
virt: Al
l
o
w passing cu
s
t
om DTB
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-11-03
Anu
p
P
atel
hw/
r
is
c
v
:
s
ifive_u: Allow passing
c
ustom DT
B
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Anu
p
Patel
hw/ris
c
v
: virt: Allow creating multiple NU
M
A soc
k
ets
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Anu
p
Patel
hw/riscv: spike
:
Allow cre
a
ting multiple NUMA
s
ockets
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Anup Patel
hw/riscv: Add help
e
r
s
for RISC-V multi-
s
ocket N
U
MA
.
.
.
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Anup
P
atel
hw/riscv: Allow cr
e
a
t
ing mult
i
ple instanc
e
s of PLIC
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Anup
Pate
l
hw/riscv: Allow creatin
g
multiple instances o
f
CLIN
T
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-04-29
Anup Patel
hw
/
r
iscv/sp
i
k
e: Al
l
ow more th
a
n o
n
e
CPU
s
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-04-29
A
n
up Pate
l
h
w
/ri
s
cv/sp
i
ke: Al
l
ow loading
fi
r
m
w
ar
e
separat
e
ly using
.
.
.
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-04-29
Anup Pa
t
el
hw/riscv: Add o
p
tion
a
l symb
o
l
callba
c
k ptr to riscv_l
o
ad_fir
.
.
.
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-04-29
Anup Patel
ris
c
v
:
Fix
St
a
ge2 SV32 p
a
ge tab
l
e walk
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Anup Patel
hw/riscv: Provide rdtime callback fo
r
T
CG in CLI
N
T
.
.
.
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Anup Patel
targ
e
t/riscv: Emulate TIME
C
SRs for priv
i
l
e
ged mode
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-02-10
Anup Patel
MAINTAINERS: Add
m
aintainer
e
ntry fo
r
Gold
f
ish RTC
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-02-10
Anup Patel
risc
v
: virt
:
Use
Goldfis
h
RTC device
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-02-10
Anup Patel
hw: rt
c
: Add Goldfish RTC device
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-02-10
Anu
p
Patel
r
i
scv
/
virt: Add syscon reboot
and poweroff DT nodes
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2018-12-20
A
n
up Patel
tar
g
et/riscv/pmp
.
c: Fix pmp_decod
e
_napo
t
()
Signed-off-by:
Anup Patel
<anup@brainfault.org>
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2018-12-20
Anu
p
Pate
l
s
if
i
ve_u
:
Set '
c
lock-frequen
c
y' DT property for SiFive
.
.
.
Signed-off-by:
Anup Patel
<anup@brainfault.org>
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2018-12-20
Anup Patel
sifive_u: Ad
d
clock DT node fo
r
G
E
M e
t
he
r
net
Signed-off-by:
Anup Patel
<anup@brainfault.org>
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree