| commit | 709044fd2da7797ae9f60088b832af085542eda6 | |
| author | Cédric Le Goater <clg@kaod.org> | |
| Wed, 12 Jun 2019 17:43:44 +0000 (12 19:43 +0200) | ||
| committer | David Gibson <david@gibson.dropbear.id.au> | |
| Mon, 1 Jul 2019 23:43:58 +0000 (2 09:43 +1000) | ||
| tree | 8ad9315b9a78c37c6b83bb8839f697635230bcc0 | treesnapshot (tar.gz zip) |
| parent | e1a9b7d1fcc1f41c917c0306bd1f2adf0d5d8e1e | commitdiff |
ppc/pnv: fix XSCOM MMIO base address for P9 machines with multiple chips
The PNV_XSCOM_BASE and PNV_XSCOM_SIZE macros are specific to POWER8
and they are used when the device tree is populated and the MMIO
region created, even for POWER9 chips. This is not too much of a
problem today because we don't have important devices on the second
chip, but we might have oneday (PHBs).
Fix by using the appropriate macros in case of P9.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20190612174345.9799-2-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
The PNV_XSCOM_BASE and PNV_XSCOM_SIZE macros are specific to POWER8
and they are used when the device tree is populated and the MMIO
region created, even for POWER9 chips. This is not too much of a
problem today because we don't have important devices on the second
chip, but we might have oneday (PHBs).
Fix by using the appropriate macros in case of P9.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20190612174345.9799-2-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| hw/ppc/pnv.c | diffblobblamehistory | |
| hw/ppc/pnv_xscom.c | diffblobblamehistory | |
| include/hw/ppc/pnv.h | diffblobblamehistory | |
| include/hw/ppc/pnv_xscom.h | diffblobblamehistory |