2 * QEMU PowerPC PowerNV various definitions
4 * Copyright (c) 2014-2016 BenH, IBM Corporation.
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
23 #include "hw/boards.h"
24 #include "hw/sysbus.h"
25 #include "hw/ipmi/ipmi.h"
26 #include "hw/ppc/pnv_lpc.h"
27 #include "hw/ppc/pnv_psi.h"
28 #include "hw/ppc/pnv_occ.h"
29 #include "hw/ppc/pnv_xive.h"
30 #include "hw/ppc/pnv_core.h"
32 #define TYPE_PNV_CHIP "pnv-chip"
33 #define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP)
34 #define PNV_CHIP_CLASS(klass) \
35 OBJECT_CLASS_CHECK(PnvChipClass, (klass), TYPE_PNV_CHIP)
36 #define PNV_CHIP_GET_CLASS(obj) \
37 OBJECT_GET_CLASS(PnvChipClass, (obj), TYPE_PNV_CHIP)
39 typedef enum PnvChipType
{
40 PNV_CHIP_POWER8E
, /* AKA Murano (default) */
41 PNV_CHIP_POWER8
, /* AKA Venice */
42 PNV_CHIP_POWER8NVL
, /* AKA Naples */
43 PNV_CHIP_POWER9
, /* AKA Nimbus */
46 typedef struct PnvChip
{
48 SysBusDevice parent_obj
;
60 MemoryRegion xscom_mmio
;
62 AddressSpace xscom_as
;
64 gchar
*dt_isa_nodename
;
67 #define TYPE_PNV8_CHIP "pnv8-chip"
68 #define PNV8_CHIP(obj) OBJECT_CHECK(Pnv8Chip, (obj), TYPE_PNV8_CHIP)
70 typedef struct Pnv8Chip
{
75 MemoryRegion icp_mmio
;
82 #define TYPE_PNV9_CHIP "pnv9-chip"
83 #define PNV9_CHIP(obj) OBJECT_CHECK(Pnv9Chip, (obj), TYPE_PNV9_CHIP)
85 typedef struct Pnv9Chip
{
99 typedef struct PnvChipClass
{
101 SysBusDeviceClass parent_class
;
104 PnvChipType chip_type
;
105 uint64_t chip_cfam_id
;
110 DeviceRealize parent_realize
;
112 uint32_t (*core_pir
)(PnvChip
*chip
, uint32_t core_id
);
113 void (*intc_create
)(PnvChip
*chip
, PowerPCCPU
*cpu
, Error
**errp
);
114 ISABus
*(*isa_create
)(PnvChip
*chip
, Error
**errp
);
115 void (*dt_populate
)(PnvChip
*chip
, void *fdt
);
116 void (*pic_print_info
)(PnvChip
*chip
, Monitor
*mon
);
119 #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP
120 #define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX
122 #define TYPE_PNV_CHIP_POWER8E PNV_CHIP_TYPE_NAME("power8e_v2.1")
123 #define PNV_CHIP_POWER8E(obj) \
124 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8E)
126 #define TYPE_PNV_CHIP_POWER8 PNV_CHIP_TYPE_NAME("power8_v2.0")
127 #define PNV_CHIP_POWER8(obj) \
128 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8)
130 #define TYPE_PNV_CHIP_POWER8NVL PNV_CHIP_TYPE_NAME("power8nvl_v1.0")
131 #define PNV_CHIP_POWER8NVL(obj) \
132 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8NVL)
134 #define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.0")
135 #define PNV_CHIP_POWER9(obj) \
136 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER9)
139 * This generates a HW chip id depending on an index, as found on a
140 * two socket system with dual chip modules :
142 * 0x0, 0x1, 0x10, 0x11
144 * 4 chips should be the maximum
146 * TODO: use a machine property to define the chip ids
148 #define PNV_CHIP_HWID(i) ((((i) & 0x3e) << 3) | ((i) & 0x1))
151 * Converts back a HW chip id to an index. This is useful to calculate
152 * the MMIO addresses of some controllers which depend on the chip id.
154 #define PNV_CHIP_INDEX(chip) \
155 (((chip)->chip_id >> 2) * 2 + ((chip)->chip_id & 0x3))
157 #define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv")
158 #define PNV_MACHINE(obj) \
159 OBJECT_CHECK(PnvMachineState, (obj), TYPE_PNV_MACHINE)
161 typedef struct PnvMachineState
{
163 MachineState parent_obj
;
165 uint32_t initrd_base
;
172 uint32_t cpld_irqstate
;
175 Notifier powerdown_notifier
;
178 static inline bool pnv_chip_is_power9(const PnvChip
*chip
)
180 return PNV_CHIP_GET_CLASS(chip
)->chip_type
== PNV_CHIP_POWER9
;
183 static inline bool pnv_is_power9(PnvMachineState
*pnv
)
185 return pnv_chip_is_power9(pnv
->chips
[0]);
188 #define PNV_FDT_ADDR 0x01000000
189 #define PNV_TIMEBASE_FREQ 512000000ULL
194 void pnv_dt_bmc_sensors(IPMIBmc
*bmc
, void *fdt
);
195 void pnv_bmc_powerdown(IPMIBmc
*bmc
);
198 * POWER8 MMIO base addresses
200 #define PNV_XSCOM_SIZE 0x800000000ull
201 #define PNV_XSCOM_BASE(chip) \
202 (chip->xscom_base + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE)
205 * XSCOM 0x20109CA defines the ICP BAR:
207 * 0:29 : bits 14 to 43 of address to define 1 MB region.
208 * 30 : 1 to enable ICP to receive loads/stores against its BAR region
211 * Usually defined as :
213 * 0xffffe00200000000 -> 0x0003ffff80000000
214 * 0xffffe00600000000 -> 0x0003ffff80100000
215 * 0xffffe02200000000 -> 0x0003ffff80800000
216 * 0xffffe02600000000 -> 0x0003ffff80900000
218 #define PNV_ICP_SIZE 0x0000000000100000ull
219 #define PNV_ICP_BASE(chip) \
220 (0x0003ffff80000000ull + (uint64_t) PNV_CHIP_INDEX(chip) * PNV_ICP_SIZE)
223 #define PNV_PSIHB_SIZE 0x0000000000100000ull
224 #define PNV_PSIHB_BASE(chip) \
225 (0x0003fffe80000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * PNV_PSIHB_SIZE)
227 #define PNV_PSIHB_FSP_SIZE 0x0000000100000000ull
228 #define PNV_PSIHB_FSP_BASE(chip) \
229 (0x0003ffe000000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * \
233 * POWER9 MMIO base addresses
235 #define PNV9_CHIP_BASE(chip, base) \
236 ((base) + ((uint64_t) (chip)->chip_id << 42))
238 #define PNV9_XIVE_VC_SIZE 0x0000008000000000ull
239 #define PNV9_XIVE_VC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006010000000000ull)
241 #define PNV9_XIVE_PC_SIZE 0x0000001000000000ull
242 #define PNV9_XIVE_PC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006018000000000ull)
244 #define PNV9_LPCM_SIZE 0x0000000100000000ull
245 #define PNV9_LPCM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030000000000ull)
247 #define PNV9_PSIHB_SIZE 0x0000000000100000ull
248 #define PNV9_PSIHB_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203000000ull)
250 #define PNV9_XIVE_IC_SIZE 0x0000000000080000ull
251 #define PNV9_XIVE_IC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203100000ull)
253 #define PNV9_XIVE_TM_SIZE 0x0000000000040000ull
254 #define PNV9_XIVE_TM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203180000ull)
256 #define PNV9_PSIHB_ESB_SIZE 0x0000000000010000ull
257 #define PNV9_PSIHB_ESB_BASE(chip) PNV9_CHIP_BASE(chip, 0x00060302031c0000ull)
259 #define PNV9_XSCOM_SIZE 0x0000000400000000ull
260 #define PNV9_XSCOM_BASE(chip) PNV9_CHIP_BASE(chip, 0x00603fc00000000ull)
262 #endif /* PPC_PNV_H */