2 * ARM Generic/Distributed Interrupt Controller
4 * Copyright (c) 2006-2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL.
10 /* This file contains implementation code for the RealView EB interrupt
11 * controller, MPCore distributed interrupt controller and ARMv7-M
12 * Nested Vectored Interrupt Controller.
13 * It is compiled in two ways:
14 * (1) as a standalone file to produce a sysbus device which is a GIC
15 * that can be used on the realview board and as one of the builtin
16 * private peripherals for the ARM MP CPUs (11MPCore, A9, etc)
17 * (2) by being directly #included into armv7m_nvic.c to produce the
21 #include "hw/sysbus.h"
22 #include "gic_internal.h"
28 #define DPRINTF(fmt, ...) \
29 do { fprintf(stderr, "arm_gic: " fmt , ## __VA_ARGS__); } while (0)
31 #define DPRINTF(fmt, ...) do {} while(0)
34 static const uint8_t gic_id
[] = {
35 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1
38 #define NUM_CPU(s) ((s)->num_cpu)
40 static inline int gic_get_current_cpu(GICState
*s
)
43 return current_cpu
->cpu_index
;
48 /* Return true if this GIC config has interrupt groups, which is
49 * true if we're a GICv2, or a GICv1 with the security extensions.
51 static inline bool gic_has_groups(GICState
*s
)
53 return s
->revision
== 2 || s
->security_extn
;
56 /* TODO: Many places that call this routine could be optimized. */
57 /* Update interrupt status after enabled or pending bits have been changed. */
58 void gic_update(GICState
*s
)
63 int irq_level
, fiq_level
;
67 for (cpu
= 0; cpu
< NUM_CPU(s
); cpu
++) {
69 s
->current_pending
[cpu
] = 1023;
70 if (!(s
->ctlr
& (GICD_CTLR_EN_GRP0
| GICD_CTLR_EN_GRP1
))
71 || !(s
->cpu_ctlr
[cpu
] & (GICC_CTLR_EN_GRP0
| GICC_CTLR_EN_GRP1
))) {
72 qemu_irq_lower(s
->parent_irq
[cpu
]);
73 qemu_irq_lower(s
->parent_fiq
[cpu
]);
78 for (irq
= 0; irq
< s
->num_irq
; irq
++) {
79 if (GIC_TEST_ENABLED(irq
, cm
) && gic_test_pending(s
, irq
, cm
) &&
80 (irq
< GIC_INTERNAL
|| GIC_TARGET(irq
) & cm
)) {
81 if (GIC_GET_PRIORITY(irq
, cpu
) < best_prio
) {
82 best_prio
= GIC_GET_PRIORITY(irq
, cpu
);
88 irq_level
= fiq_level
= 0;
90 if (best_prio
< s
->priority_mask
[cpu
]) {
91 s
->current_pending
[cpu
] = best_irq
;
92 if (best_prio
< s
->running_priority
[cpu
]) {
93 int group
= GIC_TEST_GROUP(best_irq
, cm
);
95 if (extract32(s
->ctlr
, group
, 1) &&
96 extract32(s
->cpu_ctlr
[cpu
], group
, 1)) {
97 if (group
== 0 && s
->cpu_ctlr
[cpu
] & GICC_CTLR_FIQ_EN
) {
98 DPRINTF("Raised pending FIQ %d (cpu %d)\n",
102 DPRINTF("Raised pending IRQ %d (cpu %d)\n",
110 qemu_set_irq(s
->parent_irq
[cpu
], irq_level
);
111 qemu_set_irq(s
->parent_fiq
[cpu
], fiq_level
);
115 void gic_set_pending_private(GICState
*s
, int cpu
, int irq
)
119 if (gic_test_pending(s
, irq
, cm
)) {
123 DPRINTF("Set %d pending cpu %d\n", irq
, cpu
);
124 GIC_SET_PENDING(irq
, cm
);
128 static void gic_set_irq_11mpcore(GICState
*s
, int irq
, int level
,
132 GIC_SET_LEVEL(irq
, cm
);
133 if (GIC_TEST_EDGE_TRIGGER(irq
) || GIC_TEST_ENABLED(irq
, cm
)) {
134 DPRINTF("Set %d pending mask %x\n", irq
, target
);
135 GIC_SET_PENDING(irq
, target
);
138 GIC_CLEAR_LEVEL(irq
, cm
);
142 static void gic_set_irq_generic(GICState
*s
, int irq
, int level
,
146 GIC_SET_LEVEL(irq
, cm
);
147 DPRINTF("Set %d pending mask %x\n", irq
, target
);
148 if (GIC_TEST_EDGE_TRIGGER(irq
)) {
149 GIC_SET_PENDING(irq
, target
);
152 GIC_CLEAR_LEVEL(irq
, cm
);
156 /* Process a change in an external IRQ input. */
157 static void gic_set_irq(void *opaque
, int irq
, int level
)
159 /* Meaning of the 'irq' parameter:
160 * [0..N-1] : external interrupts
161 * [N..N+31] : PPI (internal) interrupts for CPU 0
162 * [N+32..N+63] : PPI (internal interrupts for CPU 1
165 GICState
*s
= (GICState
*)opaque
;
167 if (irq
< (s
->num_irq
- GIC_INTERNAL
)) {
168 /* The first external input line is internal interrupt 32. */
171 target
= GIC_TARGET(irq
);
174 irq
-= (s
->num_irq
- GIC_INTERNAL
);
175 cpu
= irq
/ GIC_INTERNAL
;
181 assert(irq
>= GIC_NR_SGIS
);
183 if (level
== GIC_TEST_LEVEL(irq
, cm
)) {
187 if (s
->revision
== REV_11MPCORE
|| s
->revision
== REV_NVIC
) {
188 gic_set_irq_11mpcore(s
, irq
, level
, cm
, target
);
190 gic_set_irq_generic(s
, irq
, level
, cm
, target
);
196 static uint16_t gic_get_current_pending_irq(GICState
*s
, int cpu
,
199 uint16_t pending_irq
= s
->current_pending
[cpu
];
201 if (pending_irq
< GIC_MAXIRQ
&& gic_has_groups(s
)) {
202 int group
= GIC_TEST_GROUP(pending_irq
, (1 << cpu
));
203 /* On a GIC without the security extensions, reading this register
204 * behaves in the same way as a secure access to a GIC with them.
206 bool secure
= !s
->security_extn
|| attrs
.secure
;
208 if (group
== 0 && !secure
) {
209 /* Group0 interrupts hidden from Non-secure access */
212 if (group
== 1 && secure
&& !(s
->cpu_ctlr
[cpu
] & GICC_CTLR_ACK_CTL
)) {
213 /* Group1 interrupts only seen by Secure access if
222 static int gic_get_group_priority(GICState
*s
, int cpu
, int irq
)
224 /* Return the group priority of the specified interrupt
225 * (which is the top bits of its priority, with the number
226 * of bits masked determined by the applicable binary point register).
231 if (gic_has_groups(s
) &&
232 !(s
->cpu_ctlr
[cpu
] & GICC_CTLR_CBPR
) &&
233 GIC_TEST_GROUP(irq
, (1 << cpu
))) {
239 /* a BPR of 0 means the group priority bits are [7:1];
240 * a BPR of 1 means they are [7:2], and so on down to
241 * a BPR of 7 meaning no group priority bits at all.
243 mask
= ~0U << ((bpr
& 7) + 1);
245 return GIC_GET_PRIORITY(irq
, cpu
) & mask
;
248 static void gic_activate_irq(GICState
*s
, int cpu
, int irq
)
250 /* Set the appropriate Active Priority Register bit for this IRQ,
251 * and update the running priority.
253 int prio
= gic_get_group_priority(s
, cpu
, irq
);
254 int preemption_level
= prio
>> (GIC_MIN_BPR
+ 1);
255 int regno
= preemption_level
/ 32;
256 int bitno
= preemption_level
% 32;
258 if (gic_has_groups(s
) && GIC_TEST_GROUP(irq
, (1 << cpu
))) {
259 s
->nsapr
[regno
][cpu
] &= (1 << bitno
);
261 s
->apr
[regno
][cpu
] &= (1 << bitno
);
264 s
->running_priority
[cpu
] = prio
;
265 GIC_SET_ACTIVE(irq
, 1 << cpu
);
268 static int gic_get_prio_from_apr_bits(GICState
*s
, int cpu
)
270 /* Recalculate the current running priority for this CPU based
271 * on the set bits in the Active Priority Registers.
274 for (i
= 0; i
< GIC_NR_APRS
; i
++) {
275 uint32_t apr
= s
->apr
[i
][cpu
] | s
->nsapr
[i
][cpu
];
279 return (i
* 32 + ctz32(apr
)) << (GIC_MIN_BPR
+ 1);
284 static void gic_drop_prio(GICState
*s
, int cpu
, int group
)
286 /* Drop the priority of the currently active interrupt in the
289 * Note that we can guarantee (because of the requirement to nest
290 * GICC_IAR reads [which activate an interrupt and raise priority]
291 * with GICC_EOIR writes [which drop the priority for the interrupt])
292 * that the interrupt we're being called for is the highest priority
293 * active interrupt, meaning that it has the lowest set bit in the
296 * If the guest does not honour the ordering constraints then the
297 * behaviour of the GIC is UNPREDICTABLE, which for us means that
298 * the values of the APR registers might become incorrect and the
299 * running priority will be wrong, so interrupts that should preempt
300 * might not do so, and interrupts that should not preempt might do so.
304 for (i
= 0; i
< GIC_NR_APRS
; i
++) {
305 uint32_t *papr
= group
? &s
->nsapr
[i
][cpu
] : &s
->apr
[i
][cpu
];
309 /* Clear lowest set bit */
314 s
->running_priority
[cpu
] = gic_get_prio_from_apr_bits(s
, cpu
);
317 uint32_t gic_acknowledge_irq(GICState
*s
, int cpu
, MemTxAttrs attrs
)
322 /* gic_get_current_pending_irq() will return 1022 or 1023 appropriately
323 * for the case where this GIC supports grouping and the pending interrupt
324 * is in the wrong group.
326 irq
= gic_get_current_pending_irq(s
, cpu
, attrs
);
328 if (irq
>= GIC_MAXIRQ
) {
329 DPRINTF("ACK, no pending interrupt or it is hidden: %d\n", irq
);
333 if (GIC_GET_PRIORITY(irq
, cpu
) >= s
->running_priority
[cpu
]) {
334 DPRINTF("ACK, pending interrupt (%d) has insufficient priority\n", irq
);
338 if (s
->revision
== REV_11MPCORE
|| s
->revision
== REV_NVIC
) {
339 /* Clear pending flags for both level and edge triggered interrupts.
340 * Level triggered IRQs will be reasserted once they become inactive.
342 GIC_CLEAR_PENDING(irq
, GIC_TEST_MODEL(irq
) ? ALL_CPU_MASK
: cm
);
345 if (irq
< GIC_NR_SGIS
) {
346 /* Lookup the source CPU for the SGI and clear this in the
347 * sgi_pending map. Return the src and clear the overall pending
348 * state on this CPU if the SGI is not pending from any CPUs.
350 assert(s
->sgi_pending
[irq
][cpu
] != 0);
351 src
= ctz32(s
->sgi_pending
[irq
][cpu
]);
352 s
->sgi_pending
[irq
][cpu
] &= ~(1 << src
);
353 if (s
->sgi_pending
[irq
][cpu
] == 0) {
354 GIC_CLEAR_PENDING(irq
, GIC_TEST_MODEL(irq
) ? ALL_CPU_MASK
: cm
);
356 ret
= irq
| ((src
& 0x7) << 10);
358 /* Clear pending state for both level and edge triggered
359 * interrupts. (level triggered interrupts with an active line
360 * remain pending, see gic_test_pending)
362 GIC_CLEAR_PENDING(irq
, GIC_TEST_MODEL(irq
) ? ALL_CPU_MASK
: cm
);
367 gic_activate_irq(s
, cpu
, irq
);
369 DPRINTF("ACK %d\n", irq
);
373 void gic_set_priority(GICState
*s
, int cpu
, int irq
, uint8_t val
,
376 if (s
->security_extn
&& !attrs
.secure
) {
377 if (!GIC_TEST_GROUP(irq
, (1 << cpu
))) {
378 return; /* Ignore Non-secure access of Group0 IRQ */
380 val
= 0x80 | (val
>> 1); /* Non-secure view */
383 if (irq
< GIC_INTERNAL
) {
384 s
->priority1
[irq
][cpu
] = val
;
386 s
->priority2
[(irq
) - GIC_INTERNAL
] = val
;
390 static uint32_t gic_get_priority(GICState
*s
, int cpu
, int irq
,
393 uint32_t prio
= GIC_GET_PRIORITY(irq
, cpu
);
395 if (s
->security_extn
&& !attrs
.secure
) {
396 if (!GIC_TEST_GROUP(irq
, (1 << cpu
))) {
397 return 0; /* Non-secure access cannot read priority of Group0 IRQ */
399 prio
= (prio
<< 1) & 0xff; /* Non-secure view */
404 static void gic_set_priority_mask(GICState
*s
, int cpu
, uint8_t pmask
,
407 if (s
->security_extn
&& !attrs
.secure
) {
408 if (s
->priority_mask
[cpu
] & 0x80) {
409 /* Priority Mask in upper half */
410 pmask
= 0x80 | (pmask
>> 1);
412 /* Non-secure write ignored if priority mask is in lower half */
416 s
->priority_mask
[cpu
] = pmask
;
419 static uint32_t gic_get_priority_mask(GICState
*s
, int cpu
, MemTxAttrs attrs
)
421 uint32_t pmask
= s
->priority_mask
[cpu
];
423 if (s
->security_extn
&& !attrs
.secure
) {
425 /* Priority Mask in upper half, return Non-secure view */
426 pmask
= (pmask
<< 1) & 0xff;
428 /* Priority Mask in lower half, RAZ */
435 static uint32_t gic_get_cpu_control(GICState
*s
, int cpu
, MemTxAttrs attrs
)
437 uint32_t ret
= s
->cpu_ctlr
[cpu
];
439 if (s
->security_extn
&& !attrs
.secure
) {
440 /* Construct the NS banked view of GICC_CTLR from the correct
441 * bits of the S banked view. We don't need to move the bypass
442 * control bits because we don't implement that (IMPDEF) part
443 * of the GIC architecture.
445 ret
= (ret
& (GICC_CTLR_EN_GRP1
| GICC_CTLR_EOIMODE_NS
)) >> 1;
450 static void gic_set_cpu_control(GICState
*s
, int cpu
, uint32_t value
,
455 if (s
->security_extn
&& !attrs
.secure
) {
456 /* The NS view can only write certain bits in the register;
457 * the rest are unchanged
459 mask
= GICC_CTLR_EN_GRP1
;
460 if (s
->revision
== 2) {
461 mask
|= GICC_CTLR_EOIMODE_NS
;
463 s
->cpu_ctlr
[cpu
] &= ~mask
;
464 s
->cpu_ctlr
[cpu
] |= (value
<< 1) & mask
;
466 if (s
->revision
== 2) {
467 mask
= s
->security_extn
? GICC_CTLR_V2_S_MASK
: GICC_CTLR_V2_MASK
;
469 mask
= s
->security_extn
? GICC_CTLR_V1_S_MASK
: GICC_CTLR_V1_MASK
;
471 s
->cpu_ctlr
[cpu
] = value
& mask
;
473 DPRINTF("CPU Interface %d: Group0 Interrupts %sabled, "
474 "Group1 Interrupts %sabled\n", cpu
,
475 (s
->cpu_ctlr
[cpu
] & GICC_CTLR_EN_GRP0
) ? "En" : "Dis",
476 (s
->cpu_ctlr
[cpu
] & GICC_CTLR_EN_GRP1
) ? "En" : "Dis");
479 static uint8_t gic_get_running_priority(GICState
*s
, int cpu
, MemTxAttrs attrs
)
481 if (s
->security_extn
&& !attrs
.secure
) {
482 if (s
->running_priority
[cpu
] & 0x80) {
483 /* Running priority in upper half of range: return the Non-secure
484 * view of the priority.
486 return s
->running_priority
[cpu
] << 1;
488 /* Running priority in lower half of range: RAZ */
492 return s
->running_priority
[cpu
];
496 void gic_complete_irq(GICState
*s
, int cpu
, int irq
, MemTxAttrs attrs
)
501 DPRINTF("EOI %d\n", irq
);
502 if (irq
>= s
->num_irq
) {
503 /* This handles two cases:
504 * 1. If software writes the ID of a spurious interrupt [ie 1023]
505 * to the GICC_EOIR, the GIC ignores that write.
506 * 2. If software writes the number of a non-existent interrupt
507 * this must be a subcase of "value written does not match the last
508 * valid interrupt value read from the Interrupt Acknowledge
509 * register" and so this is UNPREDICTABLE. We choose to ignore it.
513 if (s
->running_priority
[cpu
] == 0x100) {
514 return; /* No active IRQ. */
517 if (s
->revision
== REV_11MPCORE
|| s
->revision
== REV_NVIC
) {
518 /* Mark level triggered interrupts as pending if they are still
520 if (!GIC_TEST_EDGE_TRIGGER(irq
) && GIC_TEST_ENABLED(irq
, cm
)
521 && GIC_TEST_LEVEL(irq
, cm
) && (GIC_TARGET(irq
) & cm
) != 0) {
522 DPRINTF("Set %d pending mask %x\n", irq
, cm
);
523 GIC_SET_PENDING(irq
, cm
);
527 group
= gic_has_groups(s
) && GIC_TEST_GROUP(irq
, cm
);
529 if (s
->security_extn
&& !attrs
.secure
&& !group
) {
530 DPRINTF("Non-secure EOI for Group0 interrupt %d ignored\n", irq
);
534 /* Secure EOI with GICC_CTLR.AckCtl == 0 when the IRQ is a Group 1
535 * interrupt is UNPREDICTABLE. We choose to handle it as if AckCtl == 1,
536 * i.e. go ahead and complete the irq anyway.
539 gic_drop_prio(s
, cpu
, group
);
540 GIC_CLEAR_ACTIVE(irq
, cm
);
544 static uint32_t gic_dist_readb(void *opaque
, hwaddr offset
, MemTxAttrs attrs
)
546 GICState
*s
= (GICState
*)opaque
;
554 cpu
= gic_get_current_cpu(s
);
556 if (offset
< 0x100) {
557 if (offset
== 0) { /* GICD_CTLR */
558 if (s
->security_extn
&& !attrs
.secure
) {
559 /* The NS bank of this register is just an alias of the
560 * EnableGrp1 bit in the S bank version.
562 return extract32(s
->ctlr
, 1, 1);
568 /* Interrupt Controller Type Register */
569 return ((s
->num_irq
/ 32) - 1)
570 | ((NUM_CPU(s
) - 1) << 5)
571 | (s
->security_extn
<< 10);
574 if (offset
>= 0x80) {
575 /* Interrupt Group Registers: these RAZ/WI if this is an NS
576 * access to a GIC with the security extensions, or if the GIC
577 * doesn't have groups at all.
580 if (!(s
->security_extn
&& !attrs
.secure
) && gic_has_groups(s
)) {
581 /* Every byte offset holds 8 group status bits */
582 irq
= (offset
- 0x080) * 8 + GIC_BASE_IRQ
;
583 if (irq
>= s
->num_irq
) {
586 for (i
= 0; i
< 8; i
++) {
587 if (GIC_TEST_GROUP(irq
+ i
, cm
)) {
595 } else if (offset
< 0x200) {
596 /* Interrupt Set/Clear Enable. */
598 irq
= (offset
- 0x100) * 8;
600 irq
= (offset
- 0x180) * 8;
602 if (irq
>= s
->num_irq
)
605 for (i
= 0; i
< 8; i
++) {
606 if (GIC_TEST_ENABLED(irq
+ i
, cm
)) {
610 } else if (offset
< 0x300) {
611 /* Interrupt Set/Clear Pending. */
613 irq
= (offset
- 0x200) * 8;
615 irq
= (offset
- 0x280) * 8;
617 if (irq
>= s
->num_irq
)
620 mask
= (irq
< GIC_INTERNAL
) ? cm
: ALL_CPU_MASK
;
621 for (i
= 0; i
< 8; i
++) {
622 if (gic_test_pending(s
, irq
+ i
, mask
)) {
626 } else if (offset
< 0x400) {
627 /* Interrupt Active. */
628 irq
= (offset
- 0x300) * 8 + GIC_BASE_IRQ
;
629 if (irq
>= s
->num_irq
)
632 mask
= (irq
< GIC_INTERNAL
) ? cm
: ALL_CPU_MASK
;
633 for (i
= 0; i
< 8; i
++) {
634 if (GIC_TEST_ACTIVE(irq
+ i
, mask
)) {
638 } else if (offset
< 0x800) {
639 /* Interrupt Priority. */
640 irq
= (offset
- 0x400) + GIC_BASE_IRQ
;
641 if (irq
>= s
->num_irq
)
643 res
= gic_get_priority(s
, cpu
, irq
, attrs
);
644 } else if (offset
< 0xc00) {
645 /* Interrupt CPU Target. */
646 if (s
->num_cpu
== 1 && s
->revision
!= REV_11MPCORE
) {
647 /* For uniprocessor GICs these RAZ/WI */
650 irq
= (offset
- 0x800) + GIC_BASE_IRQ
;
651 if (irq
>= s
->num_irq
) {
654 if (irq
>= 29 && irq
<= 31) {
657 res
= GIC_TARGET(irq
);
660 } else if (offset
< 0xf00) {
661 /* Interrupt Configuration. */
662 irq
= (offset
- 0xc00) * 4 + GIC_BASE_IRQ
;
663 if (irq
>= s
->num_irq
)
666 for (i
= 0; i
< 4; i
++) {
667 if (GIC_TEST_MODEL(irq
+ i
))
668 res
|= (1 << (i
* 2));
669 if (GIC_TEST_EDGE_TRIGGER(irq
+ i
))
670 res
|= (2 << (i
* 2));
672 } else if (offset
< 0xf10) {
674 } else if (offset
< 0xf30) {
675 if (s
->revision
== REV_11MPCORE
|| s
->revision
== REV_NVIC
) {
679 if (offset
< 0xf20) {
680 /* GICD_CPENDSGIRn */
681 irq
= (offset
- 0xf10);
683 irq
= (offset
- 0xf20);
684 /* GICD_SPENDSGIRn */
687 res
= s
->sgi_pending
[irq
][cpu
];
688 } else if (offset
< 0xfe0) {
690 } else /* offset >= 0xfe0 */ {
694 res
= gic_id
[(offset
- 0xfe0) >> 2];
699 qemu_log_mask(LOG_GUEST_ERROR
,
700 "gic_dist_readb: Bad offset %x\n", (int)offset
);
704 static MemTxResult
gic_dist_read(void *opaque
, hwaddr offset
, uint64_t *data
,
705 unsigned size
, MemTxAttrs attrs
)
709 *data
= gic_dist_readb(opaque
, offset
, attrs
);
712 *data
= gic_dist_readb(opaque
, offset
, attrs
);
713 *data
|= gic_dist_readb(opaque
, offset
+ 1, attrs
) << 8;
716 *data
= gic_dist_readb(opaque
, offset
, attrs
);
717 *data
|= gic_dist_readb(opaque
, offset
+ 1, attrs
) << 8;
718 *data
|= gic_dist_readb(opaque
, offset
+ 2, attrs
) << 16;
719 *data
|= gic_dist_readb(opaque
, offset
+ 3, attrs
) << 24;
726 static void gic_dist_writeb(void *opaque
, hwaddr offset
,
727 uint32_t value
, MemTxAttrs attrs
)
729 GICState
*s
= (GICState
*)opaque
;
734 cpu
= gic_get_current_cpu(s
);
735 if (offset
< 0x100) {
737 if (s
->security_extn
&& !attrs
.secure
) {
738 /* NS version is just an alias of the S version's bit 1 */
739 s
->ctlr
= deposit32(s
->ctlr
, 1, 1, value
);
740 } else if (gic_has_groups(s
)) {
741 s
->ctlr
= value
& (GICD_CTLR_EN_GRP0
| GICD_CTLR_EN_GRP1
);
743 s
->ctlr
= value
& GICD_CTLR_EN_GRP0
;
745 DPRINTF("Distributor: Group0 %sabled; Group 1 %sabled\n",
746 s
->ctlr
& GICD_CTLR_EN_GRP0
? "En" : "Dis",
747 s
->ctlr
& GICD_CTLR_EN_GRP1
? "En" : "Dis");
748 } else if (offset
< 4) {
750 } else if (offset
>= 0x80) {
751 /* Interrupt Group Registers: RAZ/WI for NS access to secure
752 * GIC, or for GICs without groups.
754 if (!(s
->security_extn
&& !attrs
.secure
) && gic_has_groups(s
)) {
755 /* Every byte offset holds 8 group status bits */
756 irq
= (offset
- 0x80) * 8 + GIC_BASE_IRQ
;
757 if (irq
>= s
->num_irq
) {
760 for (i
= 0; i
< 8; i
++) {
761 /* Group bits are banked for private interrupts */
762 int cm
= (irq
< GIC_INTERNAL
) ? (1 << cpu
) : ALL_CPU_MASK
;
763 if (value
& (1 << i
)) {
764 /* Group1 (Non-secure) */
765 GIC_SET_GROUP(irq
+ i
, cm
);
767 /* Group0 (Secure) */
768 GIC_CLEAR_GROUP(irq
+ i
, cm
);
775 } else if (offset
< 0x180) {
776 /* Interrupt Set Enable. */
777 irq
= (offset
- 0x100) * 8 + GIC_BASE_IRQ
;
778 if (irq
>= s
->num_irq
)
780 if (irq
< GIC_NR_SGIS
) {
784 for (i
= 0; i
< 8; i
++) {
785 if (value
& (1 << i
)) {
787 (irq
< GIC_INTERNAL
) ? (1 << cpu
) : GIC_TARGET(irq
+ i
);
788 int cm
= (irq
< GIC_INTERNAL
) ? (1 << cpu
) : ALL_CPU_MASK
;
790 if (!GIC_TEST_ENABLED(irq
+ i
, cm
)) {
791 DPRINTF("Enabled IRQ %d\n", irq
+ i
);
793 GIC_SET_ENABLED(irq
+ i
, cm
);
794 /* If a raised level triggered IRQ enabled then mark
796 if (GIC_TEST_LEVEL(irq
+ i
, mask
)
797 && !GIC_TEST_EDGE_TRIGGER(irq
+ i
)) {
798 DPRINTF("Set %d pending mask %x\n", irq
+ i
, mask
);
799 GIC_SET_PENDING(irq
+ i
, mask
);
803 } else if (offset
< 0x200) {
804 /* Interrupt Clear Enable. */
805 irq
= (offset
- 0x180) * 8 + GIC_BASE_IRQ
;
806 if (irq
>= s
->num_irq
)
808 if (irq
< GIC_NR_SGIS
) {
812 for (i
= 0; i
< 8; i
++) {
813 if (value
& (1 << i
)) {
814 int cm
= (irq
< GIC_INTERNAL
) ? (1 << cpu
) : ALL_CPU_MASK
;
816 if (GIC_TEST_ENABLED(irq
+ i
, cm
)) {
817 DPRINTF("Disabled IRQ %d\n", irq
+ i
);
819 GIC_CLEAR_ENABLED(irq
+ i
, cm
);
822 } else if (offset
< 0x280) {
823 /* Interrupt Set Pending. */
824 irq
= (offset
- 0x200) * 8 + GIC_BASE_IRQ
;
825 if (irq
>= s
->num_irq
)
827 if (irq
< GIC_NR_SGIS
) {
831 for (i
= 0; i
< 8; i
++) {
832 if (value
& (1 << i
)) {
833 GIC_SET_PENDING(irq
+ i
, GIC_TARGET(irq
+ i
));
836 } else if (offset
< 0x300) {
837 /* Interrupt Clear Pending. */
838 irq
= (offset
- 0x280) * 8 + GIC_BASE_IRQ
;
839 if (irq
>= s
->num_irq
)
841 if (irq
< GIC_NR_SGIS
) {
845 for (i
= 0; i
< 8; i
++) {
846 /* ??? This currently clears the pending bit for all CPUs, even
847 for per-CPU interrupts. It's unclear whether this is the
849 if (value
& (1 << i
)) {
850 GIC_CLEAR_PENDING(irq
+ i
, ALL_CPU_MASK
);
853 } else if (offset
< 0x400) {
854 /* Interrupt Active. */
856 } else if (offset
< 0x800) {
857 /* Interrupt Priority. */
858 irq
= (offset
- 0x400) + GIC_BASE_IRQ
;
859 if (irq
>= s
->num_irq
)
861 gic_set_priority(s
, cpu
, irq
, value
, attrs
);
862 } else if (offset
< 0xc00) {
863 /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the
864 * annoying exception of the 11MPCore's GIC.
866 if (s
->num_cpu
!= 1 || s
->revision
== REV_11MPCORE
) {
867 irq
= (offset
- 0x800) + GIC_BASE_IRQ
;
868 if (irq
>= s
->num_irq
) {
873 } else if (irq
< GIC_INTERNAL
) {
874 value
= ALL_CPU_MASK
;
876 s
->irq_target
[irq
] = value
& ALL_CPU_MASK
;
878 } else if (offset
< 0xf00) {
879 /* Interrupt Configuration. */
880 irq
= (offset
- 0xc00) * 4 + GIC_BASE_IRQ
;
881 if (irq
>= s
->num_irq
)
883 if (irq
< GIC_NR_SGIS
)
885 for (i
= 0; i
< 4; i
++) {
886 if (s
->revision
== REV_11MPCORE
|| s
->revision
== REV_NVIC
) {
887 if (value
& (1 << (i
* 2))) {
888 GIC_SET_MODEL(irq
+ i
);
890 GIC_CLEAR_MODEL(irq
+ i
);
893 if (value
& (2 << (i
* 2))) {
894 GIC_SET_EDGE_TRIGGER(irq
+ i
);
896 GIC_CLEAR_EDGE_TRIGGER(irq
+ i
);
899 } else if (offset
< 0xf10) {
900 /* 0xf00 is only handled for 32-bit writes. */
902 } else if (offset
< 0xf20) {
903 /* GICD_CPENDSGIRn */
904 if (s
->revision
== REV_11MPCORE
|| s
->revision
== REV_NVIC
) {
907 irq
= (offset
- 0xf10);
909 s
->sgi_pending
[irq
][cpu
] &= ~value
;
910 if (s
->sgi_pending
[irq
][cpu
] == 0) {
911 GIC_CLEAR_PENDING(irq
, 1 << cpu
);
913 } else if (offset
< 0xf30) {
914 /* GICD_SPENDSGIRn */
915 if (s
->revision
== REV_11MPCORE
|| s
->revision
== REV_NVIC
) {
918 irq
= (offset
- 0xf20);
920 GIC_SET_PENDING(irq
, 1 << cpu
);
921 s
->sgi_pending
[irq
][cpu
] |= value
;
928 qemu_log_mask(LOG_GUEST_ERROR
,
929 "gic_dist_writeb: Bad offset %x\n", (int)offset
);
932 static void gic_dist_writew(void *opaque
, hwaddr offset
,
933 uint32_t value
, MemTxAttrs attrs
)
935 gic_dist_writeb(opaque
, offset
, value
& 0xff, attrs
);
936 gic_dist_writeb(opaque
, offset
+ 1, value
>> 8, attrs
);
939 static void gic_dist_writel(void *opaque
, hwaddr offset
,
940 uint32_t value
, MemTxAttrs attrs
)
942 GICState
*s
= (GICState
*)opaque
;
943 if (offset
== 0xf00) {
949 cpu
= gic_get_current_cpu(s
);
951 switch ((value
>> 24) & 3) {
953 mask
= (value
>> 16) & ALL_CPU_MASK
;
956 mask
= ALL_CPU_MASK
^ (1 << cpu
);
962 DPRINTF("Bad Soft Int target filter\n");
966 GIC_SET_PENDING(irq
, mask
);
967 target_cpu
= ctz32(mask
);
968 while (target_cpu
< GIC_NCPU
) {
969 s
->sgi_pending
[irq
][target_cpu
] |= (1 << cpu
);
970 mask
&= ~(1 << target_cpu
);
971 target_cpu
= ctz32(mask
);
976 gic_dist_writew(opaque
, offset
, value
& 0xffff, attrs
);
977 gic_dist_writew(opaque
, offset
+ 2, value
>> 16, attrs
);
980 static MemTxResult
gic_dist_write(void *opaque
, hwaddr offset
, uint64_t data
,
981 unsigned size
, MemTxAttrs attrs
)
985 gic_dist_writeb(opaque
, offset
, data
, attrs
);
988 gic_dist_writew(opaque
, offset
, data
, attrs
);
991 gic_dist_writel(opaque
, offset
, data
, attrs
);
998 static inline uint32_t gic_apr_ns_view(GICState
*s
, int cpu
, int regno
)
1000 /* Return the Nonsecure view of GICC_APR<regno>. This is the
1001 * second half of GICC_NSAPR.
1003 switch (GIC_MIN_BPR
) {
1006 return s
->nsapr
[regno
+ 2][cpu
];
1011 return s
->nsapr
[regno
+ 1][cpu
];
1016 return extract32(s
->nsapr
[0][cpu
], 16, 16);
1021 return extract32(s
->nsapr
[0][cpu
], 8, 8);
1025 g_assert_not_reached();
1030 static inline void gic_apr_write_ns_view(GICState
*s
, int cpu
, int regno
,
1033 /* Write the Nonsecure view of GICC_APR<regno>. */
1034 switch (GIC_MIN_BPR
) {
1037 s
->nsapr
[regno
+ 2][cpu
] = value
;
1042 s
->nsapr
[regno
+ 1][cpu
] = value
;
1047 s
->nsapr
[0][cpu
] = deposit32(s
->nsapr
[0][cpu
], 16, 16, value
);
1052 s
->nsapr
[0][cpu
] = deposit32(s
->nsapr
[0][cpu
], 8, 8, value
);
1056 g_assert_not_reached();
1060 static MemTxResult
gic_cpu_read(GICState
*s
, int cpu
, int offset
,
1061 uint64_t *data
, MemTxAttrs attrs
)
1064 case 0x00: /* Control */
1065 *data
= gic_get_cpu_control(s
, cpu
, attrs
);
1067 case 0x04: /* Priority mask */
1068 *data
= gic_get_priority_mask(s
, cpu
, attrs
);
1070 case 0x08: /* Binary Point */
1071 if (s
->security_extn
&& !attrs
.secure
) {
1072 /* BPR is banked. Non-secure copy stored in ABPR. */
1073 *data
= s
->abpr
[cpu
];
1075 *data
= s
->bpr
[cpu
];
1078 case 0x0c: /* Acknowledge */
1079 *data
= gic_acknowledge_irq(s
, cpu
, attrs
);
1081 case 0x14: /* Running Priority */
1082 *data
= gic_get_running_priority(s
, cpu
, attrs
);
1084 case 0x18: /* Highest Pending Interrupt */
1085 *data
= gic_get_current_pending_irq(s
, cpu
, attrs
);
1087 case 0x1c: /* Aliased Binary Point */
1088 /* GIC v2, no security: ABPR
1089 * GIC v1, no security: not implemented (RAZ/WI)
1090 * With security extensions, secure access: ABPR (alias of NS BPR)
1091 * With security extensions, nonsecure access: RAZ/WI
1093 if (!gic_has_groups(s
) || (s
->security_extn
&& !attrs
.secure
)) {
1096 *data
= s
->abpr
[cpu
];
1099 case 0xd0: case 0xd4: case 0xd8: case 0xdc:
1101 int regno
= (offset
- 0xd0) / 4;
1103 if (regno
>= GIC_NR_APRS
|| s
->revision
!= 2) {
1105 } else if (s
->security_extn
&& !attrs
.secure
) {
1106 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */
1107 *data
= gic_apr_ns_view(s
, regno
, cpu
);
1109 *data
= s
->apr
[regno
][cpu
];
1113 case 0xe0: case 0xe4: case 0xe8: case 0xec:
1115 int regno
= (offset
- 0xe0) / 4;
1117 if (regno
>= GIC_NR_APRS
|| s
->revision
!= 2 || !gic_has_groups(s
) ||
1118 (s
->security_extn
&& !attrs
.secure
)) {
1121 *data
= s
->nsapr
[regno
][cpu
];
1126 qemu_log_mask(LOG_GUEST_ERROR
,
1127 "gic_cpu_read: Bad offset %x\n", (int)offset
);
1133 static MemTxResult
gic_cpu_write(GICState
*s
, int cpu
, int offset
,
1134 uint32_t value
, MemTxAttrs attrs
)
1137 case 0x00: /* Control */
1138 gic_set_cpu_control(s
, cpu
, value
, attrs
);
1140 case 0x04: /* Priority mask */
1141 gic_set_priority_mask(s
, cpu
, value
, attrs
);
1143 case 0x08: /* Binary Point */
1144 if (s
->security_extn
&& !attrs
.secure
) {
1145 s
->abpr
[cpu
] = MAX(value
& 0x7, GIC_MIN_ABPR
);
1147 s
->bpr
[cpu
] = MAX(value
& 0x7, GIC_MIN_BPR
);
1150 case 0x10: /* End Of Interrupt */
1151 gic_complete_irq(s
, cpu
, value
& 0x3ff, attrs
);
1153 case 0x1c: /* Aliased Binary Point */
1154 if (!gic_has_groups(s
) || (s
->security_extn
&& !attrs
.secure
)) {
1155 /* unimplemented, or NS access: RAZ/WI */
1158 s
->abpr
[cpu
] = MAX(value
& 0x7, GIC_MIN_ABPR
);
1161 case 0xd0: case 0xd4: case 0xd8: case 0xdc:
1163 int regno
= (offset
- 0xd0) / 4;
1165 if (regno
>= GIC_NR_APRS
|| s
->revision
!= 2) {
1168 if (s
->security_extn
&& !attrs
.secure
) {
1169 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */
1170 gic_apr_write_ns_view(s
, regno
, cpu
, value
);
1172 s
->apr
[regno
][cpu
] = value
;
1176 case 0xe0: case 0xe4: case 0xe8: case 0xec:
1178 int regno
= (offset
- 0xe0) / 4;
1180 if (regno
>= GIC_NR_APRS
|| s
->revision
!= 2) {
1183 if (!gic_has_groups(s
) || (s
->security_extn
&& !attrs
.secure
)) {
1186 s
->nsapr
[regno
][cpu
] = value
;
1190 qemu_log_mask(LOG_GUEST_ERROR
,
1191 "gic_cpu_write: Bad offset %x\n", (int)offset
);
1198 /* Wrappers to read/write the GIC CPU interface for the current CPU */
1199 static MemTxResult
gic_thiscpu_read(void *opaque
, hwaddr addr
, uint64_t *data
,
1200 unsigned size
, MemTxAttrs attrs
)
1202 GICState
*s
= (GICState
*)opaque
;
1203 return gic_cpu_read(s
, gic_get_current_cpu(s
), addr
, data
, attrs
);
1206 static MemTxResult
gic_thiscpu_write(void *opaque
, hwaddr addr
,
1207 uint64_t value
, unsigned size
,
1210 GICState
*s
= (GICState
*)opaque
;
1211 return gic_cpu_write(s
, gic_get_current_cpu(s
), addr
, value
, attrs
);
1214 /* Wrappers to read/write the GIC CPU interface for a specific CPU.
1215 * These just decode the opaque pointer into GICState* + cpu id.
1217 static MemTxResult
gic_do_cpu_read(void *opaque
, hwaddr addr
, uint64_t *data
,
1218 unsigned size
, MemTxAttrs attrs
)
1220 GICState
**backref
= (GICState
**)opaque
;
1221 GICState
*s
= *backref
;
1222 int id
= (backref
- s
->backref
);
1223 return gic_cpu_read(s
, id
, addr
, data
, attrs
);
1226 static MemTxResult
gic_do_cpu_write(void *opaque
, hwaddr addr
,
1227 uint64_t value
, unsigned size
,
1230 GICState
**backref
= (GICState
**)opaque
;
1231 GICState
*s
= *backref
;
1232 int id
= (backref
- s
->backref
);
1233 return gic_cpu_write(s
, id
, addr
, value
, attrs
);
1236 static const MemoryRegionOps gic_ops
[2] = {
1238 .read_with_attrs
= gic_dist_read
,
1239 .write_with_attrs
= gic_dist_write
,
1240 .endianness
= DEVICE_NATIVE_ENDIAN
,
1243 .read_with_attrs
= gic_thiscpu_read
,
1244 .write_with_attrs
= gic_thiscpu_write
,
1245 .endianness
= DEVICE_NATIVE_ENDIAN
,
1249 static const MemoryRegionOps gic_cpu_ops
= {
1250 .read_with_attrs
= gic_do_cpu_read
,
1251 .write_with_attrs
= gic_do_cpu_write
,
1252 .endianness
= DEVICE_NATIVE_ENDIAN
,
1255 /* This function is used by nvic model */
1256 void gic_init_irqs_and_distributor(GICState
*s
)
1258 gic_init_irqs_and_mmio(s
, gic_set_irq
, gic_ops
);
1261 static void arm_gic_realize(DeviceState
*dev
, Error
**errp
)
1263 /* Device instance realize function for the GIC sysbus device */
1265 GICState
*s
= ARM_GIC(dev
);
1266 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
1267 ARMGICClass
*agc
= ARM_GIC_GET_CLASS(s
);
1268 Error
*local_err
= NULL
;
1270 agc
->parent_realize(dev
, &local_err
);
1272 error_propagate(errp
, local_err
);
1276 /* This creates distributor and main CPU interface (s->cpuiomem[0]) */
1277 gic_init_irqs_and_mmio(s
, gic_set_irq
, gic_ops
);
1279 /* Extra core-specific regions for the CPU interfaces. This is
1280 * necessary for "franken-GIC" implementations, for example on
1282 * NB that the memory region size of 0x100 applies for the 11MPCore
1283 * and also cores following the GIC v1 spec (ie A9).
1284 * GIC v2 defines a larger memory region (0x1000) so this will need
1285 * to be extended when we implement A15.
1287 for (i
= 0; i
< NUM_CPU(s
); i
++) {
1289 memory_region_init_io(&s
->cpuiomem
[i
+1], OBJECT(s
), &gic_cpu_ops
,
1290 &s
->backref
[i
], "gic_cpu", 0x100);
1291 sysbus_init_mmio(sbd
, &s
->cpuiomem
[i
+1]);
1295 static void arm_gic_class_init(ObjectClass
*klass
, void *data
)
1297 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1298 ARMGICClass
*agc
= ARM_GIC_CLASS(klass
);
1300 agc
->parent_realize
= dc
->realize
;
1301 dc
->realize
= arm_gic_realize
;
1304 static const TypeInfo arm_gic_info
= {
1305 .name
= TYPE_ARM_GIC
,
1306 .parent
= TYPE_ARM_GIC_COMMON
,
1307 .instance_size
= sizeof(GICState
),
1308 .class_init
= arm_gic_class_init
,
1309 .class_size
= sizeof(ARMGICClass
),
1312 static void arm_gic_register_types(void)
1314 type_register_static(&arm_gic_info
);
1317 type_init(arm_gic_register_types
)