2 * QEMU emulation of an Intel IOMMU (VT-d)
3 * (DMA Remapping device)
5 * Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com>
6 * Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
22 #include "qemu/osdep.h"
23 #include "qemu/error-report.h"
24 #include "qapi/error.h"
25 #include "hw/sysbus.h"
26 #include "exec/address-spaces.h"
27 #include "intel_iommu_internal.h"
28 #include "hw/pci/pci.h"
29 #include "hw/pci/pci_bus.h"
30 #include "hw/i386/pc.h"
31 #include "hw/i386/apic-msidef.h"
32 #include "hw/boards.h"
33 #include "hw/i386/x86-iommu.h"
34 #include "hw/pci-host/q35.h"
35 #include "sysemu/kvm.h"
36 #include "hw/i386/apic_internal.h"
40 static void vtd_define_quad(IntelIOMMUState
*s
, hwaddr addr
, uint64_t val
,
41 uint64_t wmask
, uint64_t w1cmask
)
43 stq_le_p(&s
->csr
[addr
], val
);
44 stq_le_p(&s
->wmask
[addr
], wmask
);
45 stq_le_p(&s
->w1cmask
[addr
], w1cmask
);
48 static void vtd_define_quad_wo(IntelIOMMUState
*s
, hwaddr addr
, uint64_t mask
)
50 stq_le_p(&s
->womask
[addr
], mask
);
53 static void vtd_define_long(IntelIOMMUState
*s
, hwaddr addr
, uint32_t val
,
54 uint32_t wmask
, uint32_t w1cmask
)
56 stl_le_p(&s
->csr
[addr
], val
);
57 stl_le_p(&s
->wmask
[addr
], wmask
);
58 stl_le_p(&s
->w1cmask
[addr
], w1cmask
);
61 static void vtd_define_long_wo(IntelIOMMUState
*s
, hwaddr addr
, uint32_t mask
)
63 stl_le_p(&s
->womask
[addr
], mask
);
66 /* "External" get/set operations */
67 static void vtd_set_quad(IntelIOMMUState
*s
, hwaddr addr
, uint64_t val
)
69 uint64_t oldval
= ldq_le_p(&s
->csr
[addr
]);
70 uint64_t wmask
= ldq_le_p(&s
->wmask
[addr
]);
71 uint64_t w1cmask
= ldq_le_p(&s
->w1cmask
[addr
]);
72 stq_le_p(&s
->csr
[addr
],
73 ((oldval
& ~wmask
) | (val
& wmask
)) & ~(w1cmask
& val
));
76 static void vtd_set_long(IntelIOMMUState
*s
, hwaddr addr
, uint32_t val
)
78 uint32_t oldval
= ldl_le_p(&s
->csr
[addr
]);
79 uint32_t wmask
= ldl_le_p(&s
->wmask
[addr
]);
80 uint32_t w1cmask
= ldl_le_p(&s
->w1cmask
[addr
]);
81 stl_le_p(&s
->csr
[addr
],
82 ((oldval
& ~wmask
) | (val
& wmask
)) & ~(w1cmask
& val
));
85 static uint64_t vtd_get_quad(IntelIOMMUState
*s
, hwaddr addr
)
87 uint64_t val
= ldq_le_p(&s
->csr
[addr
]);
88 uint64_t womask
= ldq_le_p(&s
->womask
[addr
]);
92 static uint32_t vtd_get_long(IntelIOMMUState
*s
, hwaddr addr
)
94 uint32_t val
= ldl_le_p(&s
->csr
[addr
]);
95 uint32_t womask
= ldl_le_p(&s
->womask
[addr
]);
99 /* "Internal" get/set operations */
100 static uint64_t vtd_get_quad_raw(IntelIOMMUState
*s
, hwaddr addr
)
102 return ldq_le_p(&s
->csr
[addr
]);
105 static uint32_t vtd_get_long_raw(IntelIOMMUState
*s
, hwaddr addr
)
107 return ldl_le_p(&s
->csr
[addr
]);
110 static void vtd_set_quad_raw(IntelIOMMUState
*s
, hwaddr addr
, uint64_t val
)
112 stq_le_p(&s
->csr
[addr
], val
);
115 static uint32_t vtd_set_clear_mask_long(IntelIOMMUState
*s
, hwaddr addr
,
116 uint32_t clear
, uint32_t mask
)
118 uint32_t new_val
= (ldl_le_p(&s
->csr
[addr
]) & ~clear
) | mask
;
119 stl_le_p(&s
->csr
[addr
], new_val
);
123 static uint64_t vtd_set_clear_mask_quad(IntelIOMMUState
*s
, hwaddr addr
,
124 uint64_t clear
, uint64_t mask
)
126 uint64_t new_val
= (ldq_le_p(&s
->csr
[addr
]) & ~clear
) | mask
;
127 stq_le_p(&s
->csr
[addr
], new_val
);
131 static inline void vtd_iommu_lock(IntelIOMMUState
*s
)
133 qemu_mutex_lock(&s
->iommu_lock
);
136 static inline void vtd_iommu_unlock(IntelIOMMUState
*s
)
138 qemu_mutex_unlock(&s
->iommu_lock
);
141 /* Whether the address space needs to notify new mappings */
142 static inline gboolean
vtd_as_has_map_notifier(VTDAddressSpace
*as
)
144 return as
->notifier_flags
& IOMMU_NOTIFIER_MAP
;
147 /* GHashTable functions */
148 static gboolean
vtd_uint64_equal(gconstpointer v1
, gconstpointer v2
)
150 return *((const uint64_t *)v1
) == *((const uint64_t *)v2
);
153 static guint
vtd_uint64_hash(gconstpointer v
)
155 return (guint
)*(const uint64_t *)v
;
158 static gboolean
vtd_hash_remove_by_domain(gpointer key
, gpointer value
,
161 VTDIOTLBEntry
*entry
= (VTDIOTLBEntry
*)value
;
162 uint16_t domain_id
= *(uint16_t *)user_data
;
163 return entry
->domain_id
== domain_id
;
166 /* The shift of an addr for a certain level of paging structure */
167 static inline uint32_t vtd_slpt_level_shift(uint32_t level
)
170 return VTD_PAGE_SHIFT_4K
+ (level
- 1) * VTD_SL_LEVEL_BITS
;
173 static inline uint64_t vtd_slpt_level_page_mask(uint32_t level
)
175 return ~((1ULL << vtd_slpt_level_shift(level
)) - 1);
178 static gboolean
vtd_hash_remove_by_page(gpointer key
, gpointer value
,
181 VTDIOTLBEntry
*entry
= (VTDIOTLBEntry
*)value
;
182 VTDIOTLBPageInvInfo
*info
= (VTDIOTLBPageInvInfo
*)user_data
;
183 uint64_t gfn
= (info
->addr
>> VTD_PAGE_SHIFT_4K
) & info
->mask
;
184 uint64_t gfn_tlb
= (info
->addr
& entry
->mask
) >> VTD_PAGE_SHIFT_4K
;
185 return (entry
->domain_id
== info
->domain_id
) &&
186 (((entry
->gfn
& info
->mask
) == gfn
) ||
187 (entry
->gfn
== gfn_tlb
));
190 /* Reset all the gen of VTDAddressSpace to zero and set the gen of
191 * IntelIOMMUState to 1. Must be called with IOMMU lock held.
193 static void vtd_reset_context_cache_locked(IntelIOMMUState
*s
)
195 VTDAddressSpace
*vtd_as
;
197 GHashTableIter bus_it
;
200 trace_vtd_context_cache_reset();
202 g_hash_table_iter_init(&bus_it
, s
->vtd_as_by_busptr
);
204 while (g_hash_table_iter_next (&bus_it
, NULL
, (void**)&vtd_bus
)) {
205 for (devfn_it
= 0; devfn_it
< PCI_DEVFN_MAX
; ++devfn_it
) {
206 vtd_as
= vtd_bus
->dev_as
[devfn_it
];
210 vtd_as
->context_cache_entry
.context_cache_gen
= 0;
213 s
->context_cache_gen
= 1;
216 /* Must be called with IOMMU lock held. */
217 static void vtd_reset_iotlb_locked(IntelIOMMUState
*s
)
220 g_hash_table_remove_all(s
->iotlb
);
223 static void vtd_reset_iotlb(IntelIOMMUState
*s
)
226 vtd_reset_iotlb_locked(s
);
230 static uint64_t vtd_get_iotlb_key(uint64_t gfn
, uint16_t source_id
,
233 return gfn
| ((uint64_t)(source_id
) << VTD_IOTLB_SID_SHIFT
) |
234 ((uint64_t)(level
) << VTD_IOTLB_LVL_SHIFT
);
237 static uint64_t vtd_get_iotlb_gfn(hwaddr addr
, uint32_t level
)
239 return (addr
& vtd_slpt_level_page_mask(level
)) >> VTD_PAGE_SHIFT_4K
;
242 /* Must be called with IOMMU lock held */
243 static VTDIOTLBEntry
*vtd_lookup_iotlb(IntelIOMMUState
*s
, uint16_t source_id
,
246 VTDIOTLBEntry
*entry
;
250 for (level
= VTD_SL_PT_LEVEL
; level
< VTD_SL_PML4_LEVEL
; level
++) {
251 key
= vtd_get_iotlb_key(vtd_get_iotlb_gfn(addr
, level
),
253 entry
= g_hash_table_lookup(s
->iotlb
, &key
);
263 /* Must be with IOMMU lock held */
264 static void vtd_update_iotlb(IntelIOMMUState
*s
, uint16_t source_id
,
265 uint16_t domain_id
, hwaddr addr
, uint64_t slpte
,
266 uint8_t access_flags
, uint32_t level
)
268 VTDIOTLBEntry
*entry
= g_malloc(sizeof(*entry
));
269 uint64_t *key
= g_malloc(sizeof(*key
));
270 uint64_t gfn
= vtd_get_iotlb_gfn(addr
, level
);
272 trace_vtd_iotlb_page_update(source_id
, addr
, slpte
, domain_id
);
273 if (g_hash_table_size(s
->iotlb
) >= VTD_IOTLB_MAX_SIZE
) {
274 trace_vtd_iotlb_reset("iotlb exceeds size limit");
275 vtd_reset_iotlb_locked(s
);
279 entry
->domain_id
= domain_id
;
280 entry
->slpte
= slpte
;
281 entry
->access_flags
= access_flags
;
282 entry
->mask
= vtd_slpt_level_page_mask(level
);
283 *key
= vtd_get_iotlb_key(gfn
, source_id
, level
);
284 g_hash_table_replace(s
->iotlb
, key
, entry
);
287 /* Given the reg addr of both the message data and address, generate an
290 static void vtd_generate_interrupt(IntelIOMMUState
*s
, hwaddr mesg_addr_reg
,
291 hwaddr mesg_data_reg
)
295 assert(mesg_data_reg
< DMAR_REG_SIZE
);
296 assert(mesg_addr_reg
< DMAR_REG_SIZE
);
298 msi
.address
= vtd_get_long_raw(s
, mesg_addr_reg
);
299 msi
.data
= vtd_get_long_raw(s
, mesg_data_reg
);
301 trace_vtd_irq_generate(msi
.address
, msi
.data
);
303 apic_get_class()->send_msi(&msi
);
306 /* Generate a fault event to software via MSI if conditions are met.
307 * Notice that the value of FSTS_REG being passed to it should be the one
310 static void vtd_generate_fault_event(IntelIOMMUState
*s
, uint32_t pre_fsts
)
312 if (pre_fsts
& VTD_FSTS_PPF
|| pre_fsts
& VTD_FSTS_PFO
||
313 pre_fsts
& VTD_FSTS_IQE
) {
314 trace_vtd_err("There are previous interrupt conditions "
315 "to be serviced by software, fault event "
316 "is not generated.");
319 vtd_set_clear_mask_long(s
, DMAR_FECTL_REG
, 0, VTD_FECTL_IP
);
320 if (vtd_get_long_raw(s
, DMAR_FECTL_REG
) & VTD_FECTL_IM
) {
321 trace_vtd_err("Interrupt Mask set, irq is not generated.");
323 vtd_generate_interrupt(s
, DMAR_FEADDR_REG
, DMAR_FEDATA_REG
);
324 vtd_set_clear_mask_long(s
, DMAR_FECTL_REG
, VTD_FECTL_IP
, 0);
328 /* Check if the Fault (F) field of the Fault Recording Register referenced by
331 static bool vtd_is_frcd_set(IntelIOMMUState
*s
, uint16_t index
)
333 /* Each reg is 128-bit */
334 hwaddr addr
= DMAR_FRCD_REG_OFFSET
+ (((uint64_t)index
) << 4);
335 addr
+= 8; /* Access the high 64-bit half */
337 assert(index
< DMAR_FRCD_REG_NR
);
339 return vtd_get_quad_raw(s
, addr
) & VTD_FRCD_F
;
342 /* Update the PPF field of Fault Status Register.
343 * Should be called whenever change the F field of any fault recording
346 static void vtd_update_fsts_ppf(IntelIOMMUState
*s
)
349 uint32_t ppf_mask
= 0;
351 for (i
= 0; i
< DMAR_FRCD_REG_NR
; i
++) {
352 if (vtd_is_frcd_set(s
, i
)) {
353 ppf_mask
= VTD_FSTS_PPF
;
357 vtd_set_clear_mask_long(s
, DMAR_FSTS_REG
, VTD_FSTS_PPF
, ppf_mask
);
358 trace_vtd_fsts_ppf(!!ppf_mask
);
361 static void vtd_set_frcd_and_update_ppf(IntelIOMMUState
*s
, uint16_t index
)
363 /* Each reg is 128-bit */
364 hwaddr addr
= DMAR_FRCD_REG_OFFSET
+ (((uint64_t)index
) << 4);
365 addr
+= 8; /* Access the high 64-bit half */
367 assert(index
< DMAR_FRCD_REG_NR
);
369 vtd_set_clear_mask_quad(s
, addr
, 0, VTD_FRCD_F
);
370 vtd_update_fsts_ppf(s
);
373 /* Must not update F field now, should be done later */
374 static void vtd_record_frcd(IntelIOMMUState
*s
, uint16_t index
,
375 uint16_t source_id
, hwaddr addr
,
376 VTDFaultReason fault
, bool is_write
)
379 hwaddr frcd_reg_addr
= DMAR_FRCD_REG_OFFSET
+ (((uint64_t)index
) << 4);
381 assert(index
< DMAR_FRCD_REG_NR
);
383 lo
= VTD_FRCD_FI(addr
);
384 hi
= VTD_FRCD_SID(source_id
) | VTD_FRCD_FR(fault
);
388 vtd_set_quad_raw(s
, frcd_reg_addr
, lo
);
389 vtd_set_quad_raw(s
, frcd_reg_addr
+ 8, hi
);
391 trace_vtd_frr_new(index
, hi
, lo
);
394 /* Try to collapse multiple pending faults from the same requester */
395 static bool vtd_try_collapse_fault(IntelIOMMUState
*s
, uint16_t source_id
)
399 hwaddr addr
= DMAR_FRCD_REG_OFFSET
+ 8; /* The high 64-bit half */
401 for (i
= 0; i
< DMAR_FRCD_REG_NR
; i
++) {
402 frcd_reg
= vtd_get_quad_raw(s
, addr
);
403 if ((frcd_reg
& VTD_FRCD_F
) &&
404 ((frcd_reg
& VTD_FRCD_SID_MASK
) == source_id
)) {
407 addr
+= 16; /* 128-bit for each */
412 /* Log and report an DMAR (address translation) fault to software */
413 static void vtd_report_dmar_fault(IntelIOMMUState
*s
, uint16_t source_id
,
414 hwaddr addr
, VTDFaultReason fault
,
417 uint32_t fsts_reg
= vtd_get_long_raw(s
, DMAR_FSTS_REG
);
419 assert(fault
< VTD_FR_MAX
);
421 if (fault
== VTD_FR_RESERVED_ERR
) {
422 /* This is not a normal fault reason case. Drop it. */
426 trace_vtd_dmar_fault(source_id
, fault
, addr
, is_write
);
428 if (fsts_reg
& VTD_FSTS_PFO
) {
429 trace_vtd_err("New fault is not recorded due to "
430 "Primary Fault Overflow.");
434 if (vtd_try_collapse_fault(s
, source_id
)) {
435 trace_vtd_err("New fault is not recorded due to "
436 "compression of faults.");
440 if (vtd_is_frcd_set(s
, s
->next_frcd_reg
)) {
441 trace_vtd_err("Next Fault Recording Reg is used, "
442 "new fault is not recorded, set PFO field.");
443 vtd_set_clear_mask_long(s
, DMAR_FSTS_REG
, 0, VTD_FSTS_PFO
);
447 vtd_record_frcd(s
, s
->next_frcd_reg
, source_id
, addr
, fault
, is_write
);
449 if (fsts_reg
& VTD_FSTS_PPF
) {
450 trace_vtd_err("There are pending faults already, "
451 "fault event is not generated.");
452 vtd_set_frcd_and_update_ppf(s
, s
->next_frcd_reg
);
454 if (s
->next_frcd_reg
== DMAR_FRCD_REG_NR
) {
455 s
->next_frcd_reg
= 0;
458 vtd_set_clear_mask_long(s
, DMAR_FSTS_REG
, VTD_FSTS_FRI_MASK
,
459 VTD_FSTS_FRI(s
->next_frcd_reg
));
460 vtd_set_frcd_and_update_ppf(s
, s
->next_frcd_reg
); /* Will set PPF */
462 if (s
->next_frcd_reg
== DMAR_FRCD_REG_NR
) {
463 s
->next_frcd_reg
= 0;
465 /* This case actually cause the PPF to be Set.
466 * So generate fault event (interrupt).
468 vtd_generate_fault_event(s
, fsts_reg
);
472 /* Handle Invalidation Queue Errors of queued invalidation interface error
475 static void vtd_handle_inv_queue_error(IntelIOMMUState
*s
)
477 uint32_t fsts_reg
= vtd_get_long_raw(s
, DMAR_FSTS_REG
);
479 vtd_set_clear_mask_long(s
, DMAR_FSTS_REG
, 0, VTD_FSTS_IQE
);
480 vtd_generate_fault_event(s
, fsts_reg
);
483 /* Set the IWC field and try to generate an invalidation completion interrupt */
484 static void vtd_generate_completion_event(IntelIOMMUState
*s
)
486 if (vtd_get_long_raw(s
, DMAR_ICS_REG
) & VTD_ICS_IWC
) {
487 trace_vtd_inv_desc_wait_irq("One pending, skip current");
490 vtd_set_clear_mask_long(s
, DMAR_ICS_REG
, 0, VTD_ICS_IWC
);
491 vtd_set_clear_mask_long(s
, DMAR_IECTL_REG
, 0, VTD_IECTL_IP
);
492 if (vtd_get_long_raw(s
, DMAR_IECTL_REG
) & VTD_IECTL_IM
) {
493 trace_vtd_inv_desc_wait_irq("IM in IECTL_REG is set, "
494 "new event not generated");
497 /* Generate the interrupt event */
498 trace_vtd_inv_desc_wait_irq("Generating complete event");
499 vtd_generate_interrupt(s
, DMAR_IEADDR_REG
, DMAR_IEDATA_REG
);
500 vtd_set_clear_mask_long(s
, DMAR_IECTL_REG
, VTD_IECTL_IP
, 0);
504 static inline bool vtd_root_entry_present(VTDRootEntry
*root
)
506 return root
->val
& VTD_ROOT_ENTRY_P
;
509 static int vtd_get_root_entry(IntelIOMMUState
*s
, uint8_t index
,
514 addr
= s
->root
+ index
* sizeof(*re
);
515 if (dma_memory_read(&address_space_memory
, addr
, re
, sizeof(*re
))) {
516 trace_vtd_re_invalid(re
->rsvd
, re
->val
);
518 return -VTD_FR_ROOT_TABLE_INV
;
520 re
->val
= le64_to_cpu(re
->val
);
524 static inline bool vtd_ce_present(VTDContextEntry
*context
)
526 return context
->lo
& VTD_CONTEXT_ENTRY_P
;
529 static int vtd_get_context_entry_from_root(VTDRootEntry
*root
, uint8_t index
,
534 /* we have checked that root entry is present */
535 addr
= (root
->val
& VTD_ROOT_ENTRY_CTP
) + index
* sizeof(*ce
);
536 if (dma_memory_read(&address_space_memory
, addr
, ce
, sizeof(*ce
))) {
537 trace_vtd_re_invalid(root
->rsvd
, root
->val
);
538 return -VTD_FR_CONTEXT_TABLE_INV
;
540 ce
->lo
= le64_to_cpu(ce
->lo
);
541 ce
->hi
= le64_to_cpu(ce
->hi
);
545 static inline dma_addr_t
vtd_ce_get_slpt_base(VTDContextEntry
*ce
)
547 return ce
->lo
& VTD_CONTEXT_ENTRY_SLPTPTR
;
550 static inline uint64_t vtd_get_slpte_addr(uint64_t slpte
, uint8_t aw
)
552 return slpte
& VTD_SL_PT_BASE_ADDR_MASK(aw
);
555 /* Whether the pte indicates the address of the page frame */
556 static inline bool vtd_is_last_slpte(uint64_t slpte
, uint32_t level
)
558 return level
== VTD_SL_PT_LEVEL
|| (slpte
& VTD_SL_PT_PAGE_SIZE_MASK
);
561 /* Get the content of a spte located in @base_addr[@index] */
562 static uint64_t vtd_get_slpte(dma_addr_t base_addr
, uint32_t index
)
566 assert(index
< VTD_SL_PT_ENTRY_NR
);
568 if (dma_memory_read(&address_space_memory
,
569 base_addr
+ index
* sizeof(slpte
), &slpte
,
571 slpte
= (uint64_t)-1;
574 slpte
= le64_to_cpu(slpte
);
578 /* Given an iova and the level of paging structure, return the offset
581 static inline uint32_t vtd_iova_level_offset(uint64_t iova
, uint32_t level
)
583 return (iova
>> vtd_slpt_level_shift(level
)) &
584 ((1ULL << VTD_SL_LEVEL_BITS
) - 1);
587 /* Check Capability Register to see if the @level of page-table is supported */
588 static inline bool vtd_is_level_supported(IntelIOMMUState
*s
, uint32_t level
)
590 return VTD_CAP_SAGAW_MASK
& s
->cap
&
591 (1ULL << (level
- 2 + VTD_CAP_SAGAW_SHIFT
));
594 /* Get the page-table level that hardware should use for the second-level
595 * page-table walk from the Address Width field of context-entry.
597 static inline uint32_t vtd_ce_get_level(VTDContextEntry
*ce
)
599 return 2 + (ce
->hi
& VTD_CONTEXT_ENTRY_AW
);
602 static inline uint32_t vtd_ce_get_agaw(VTDContextEntry
*ce
)
604 return 30 + (ce
->hi
& VTD_CONTEXT_ENTRY_AW
) * 9;
607 static inline uint32_t vtd_ce_get_type(VTDContextEntry
*ce
)
609 return ce
->lo
& VTD_CONTEXT_ENTRY_TT
;
612 /* Return true if check passed, otherwise false */
613 static inline bool vtd_ce_type_check(X86IOMMUState
*x86_iommu
,
616 switch (vtd_ce_get_type(ce
)) {
617 case VTD_CONTEXT_TT_MULTI_LEVEL
:
618 /* Always supported */
620 case VTD_CONTEXT_TT_DEV_IOTLB
:
621 if (!x86_iommu
->dt_supported
) {
625 case VTD_CONTEXT_TT_PASS_THROUGH
:
626 if (!x86_iommu
->pt_supported
) {
637 static inline uint64_t vtd_iova_limit(VTDContextEntry
*ce
, uint8_t aw
)
639 uint32_t ce_agaw
= vtd_ce_get_agaw(ce
);
640 return 1ULL << MIN(ce_agaw
, aw
);
643 /* Return true if IOVA passes range check, otherwise false. */
644 static inline bool vtd_iova_range_check(uint64_t iova
, VTDContextEntry
*ce
,
648 * Check if @iova is above 2^X-1, where X is the minimum of MGAW
649 * in CAP_REG and AW in context-entry.
651 return !(iova
& ~(vtd_iova_limit(ce
, aw
) - 1));
655 * Rsvd field masks for spte:
656 * Index [1] to [4] 4k pages
657 * Index [5] to [8] large pages
659 static uint64_t vtd_paging_entry_rsvd_field
[9];
661 static bool vtd_slpte_nonzero_rsvd(uint64_t slpte
, uint32_t level
)
663 if (slpte
& VTD_SL_PT_PAGE_SIZE_MASK
) {
664 /* Maybe large page */
665 return slpte
& vtd_paging_entry_rsvd_field
[level
+ 4];
667 return slpte
& vtd_paging_entry_rsvd_field
[level
];
671 /* Find the VTD address space associated with a given bus number */
672 static VTDBus
*vtd_find_as_from_bus_num(IntelIOMMUState
*s
, uint8_t bus_num
)
674 VTDBus
*vtd_bus
= s
->vtd_as_by_bus_num
[bus_num
];
677 * Iterate over the registered buses to find the one which
678 * currently hold this bus number, and update the bus_num
683 g_hash_table_iter_init(&iter
, s
->vtd_as_by_busptr
);
684 while (g_hash_table_iter_next(&iter
, NULL
, (void **)&vtd_bus
)) {
685 if (pci_bus_num(vtd_bus
->bus
) == bus_num
) {
686 s
->vtd_as_by_bus_num
[bus_num
] = vtd_bus
;
694 /* Given the @iova, get relevant @slptep. @slpte_level will be the last level
695 * of the translation, can be used for deciding the size of large page.
697 static int vtd_iova_to_slpte(VTDContextEntry
*ce
, uint64_t iova
, bool is_write
,
698 uint64_t *slptep
, uint32_t *slpte_level
,
699 bool *reads
, bool *writes
, uint8_t aw_bits
)
701 dma_addr_t addr
= vtd_ce_get_slpt_base(ce
);
702 uint32_t level
= vtd_ce_get_level(ce
);
705 uint64_t access_right_check
;
707 if (!vtd_iova_range_check(iova
, ce
, aw_bits
)) {
708 trace_vtd_err_dmar_iova_overflow(iova
);
709 return -VTD_FR_ADDR_BEYOND_MGAW
;
712 /* FIXME: what is the Atomics request here? */
713 access_right_check
= is_write
? VTD_SL_W
: VTD_SL_R
;
716 offset
= vtd_iova_level_offset(iova
, level
);
717 slpte
= vtd_get_slpte(addr
, offset
);
719 if (slpte
== (uint64_t)-1) {
720 trace_vtd_err_dmar_slpte_read_error(iova
, level
);
721 if (level
== vtd_ce_get_level(ce
)) {
722 /* Invalid programming of context-entry */
723 return -VTD_FR_CONTEXT_ENTRY_INV
;
725 return -VTD_FR_PAGING_ENTRY_INV
;
728 *reads
= (*reads
) && (slpte
& VTD_SL_R
);
729 *writes
= (*writes
) && (slpte
& VTD_SL_W
);
730 if (!(slpte
& access_right_check
)) {
731 trace_vtd_err_dmar_slpte_perm_error(iova
, level
, slpte
, is_write
);
732 return is_write
? -VTD_FR_WRITE
: -VTD_FR_READ
;
734 if (vtd_slpte_nonzero_rsvd(slpte
, level
)) {
735 trace_vtd_err_dmar_slpte_resv_error(iova
, level
, slpte
);
736 return -VTD_FR_PAGING_ENTRY_RSVD
;
739 if (vtd_is_last_slpte(slpte
, level
)) {
741 *slpte_level
= level
;
744 addr
= vtd_get_slpte_addr(slpte
, aw_bits
);
749 typedef int (*vtd_page_walk_hook
)(IOMMUTLBEntry
*entry
, void *private);
752 * Constant information used during page walking
754 * @hook_fn: hook func to be called when detected page
755 * @private: private data to be passed into hook func
756 * @notify_unmap: whether we should notify invalid entries
757 * @aw: maximum address width
760 vtd_page_walk_hook hook_fn
;
764 } vtd_page_walk_info
;
766 static int vtd_page_walk_one(IOMMUTLBEntry
*entry
, int level
,
767 vtd_page_walk_info
*info
)
769 vtd_page_walk_hook hook_fn
= info
->hook_fn
;
770 void *private = info
->private;
773 trace_vtd_page_walk_one(level
, entry
->iova
, entry
->translated_addr
,
774 entry
->addr_mask
, entry
->perm
);
775 return hook_fn(entry
, private);
779 * vtd_page_walk_level - walk over specific level for IOVA range
781 * @addr: base GPA addr to start the walk
782 * @start: IOVA range start address
783 * @end: IOVA range end address (start <= addr < end)
784 * @read: whether parent level has read permission
785 * @write: whether parent level has write permission
786 * @info: constant information for the page walk
788 static int vtd_page_walk_level(dma_addr_t addr
, uint64_t start
,
789 uint64_t end
, uint32_t level
, bool read
,
790 bool write
, vtd_page_walk_info
*info
)
792 bool read_cur
, write_cur
, entry_valid
;
795 uint64_t subpage_size
, subpage_mask
;
797 uint64_t iova
= start
;
801 trace_vtd_page_walk_level(addr
, level
, start
, end
);
803 subpage_size
= 1ULL << vtd_slpt_level_shift(level
);
804 subpage_mask
= vtd_slpt_level_page_mask(level
);
807 iova_next
= (iova
& subpage_mask
) + subpage_size
;
809 offset
= vtd_iova_level_offset(iova
, level
);
810 slpte
= vtd_get_slpte(addr
, offset
);
812 if (slpte
== (uint64_t)-1) {
813 trace_vtd_page_walk_skip_read(iova
, iova_next
);
817 if (vtd_slpte_nonzero_rsvd(slpte
, level
)) {
818 trace_vtd_page_walk_skip_reserve(iova
, iova_next
);
822 /* Permissions are stacked with parents' */
823 read_cur
= read
&& (slpte
& VTD_SL_R
);
824 write_cur
= write
&& (slpte
& VTD_SL_W
);
827 * As long as we have either read/write permission, this is a
828 * valid entry. The rule works for both page entries and page
831 entry_valid
= read_cur
| write_cur
;
833 entry
.target_as
= &address_space_memory
;
834 entry
.iova
= iova
& subpage_mask
;
835 entry
.perm
= IOMMU_ACCESS_FLAG(read_cur
, write_cur
);
836 entry
.addr_mask
= ~subpage_mask
;
838 if (vtd_is_last_slpte(slpte
, level
)) {
839 /* NOTE: this is only meaningful if entry_valid == true */
840 entry
.translated_addr
= vtd_get_slpte_addr(slpte
, info
->aw
);
841 if (!entry_valid
&& !info
->notify_unmap
) {
842 trace_vtd_page_walk_skip_perm(iova
, iova_next
);
845 ret
= vtd_page_walk_one(&entry
, level
, info
);
851 if (info
->notify_unmap
) {
853 * The whole entry is invalid; unmap it all.
854 * Translated address is meaningless, zero it.
856 entry
.translated_addr
= 0x0;
857 ret
= vtd_page_walk_one(&entry
, level
, info
);
862 trace_vtd_page_walk_skip_perm(iova
, iova_next
);
866 ret
= vtd_page_walk_level(vtd_get_slpte_addr(slpte
, info
->aw
),
867 iova
, MIN(iova_next
, end
), level
- 1,
868 read_cur
, write_cur
, info
);
882 * vtd_page_walk - walk specific IOVA range, and call the hook
884 * @ce: context entry to walk upon
885 * @start: IOVA address to start the walk
886 * @end: IOVA range end address (start <= addr < end)
887 * @info: page walking information struct
889 static int vtd_page_walk(VTDContextEntry
*ce
, uint64_t start
, uint64_t end
,
890 vtd_page_walk_info
*info
)
892 dma_addr_t addr
= vtd_ce_get_slpt_base(ce
);
893 uint32_t level
= vtd_ce_get_level(ce
);
895 if (!vtd_iova_range_check(start
, ce
, info
->aw
)) {
896 return -VTD_FR_ADDR_BEYOND_MGAW
;
899 if (!vtd_iova_range_check(end
, ce
, info
->aw
)) {
900 /* Fix end so that it reaches the maximum */
901 end
= vtd_iova_limit(ce
, info
->aw
);
904 return vtd_page_walk_level(addr
, start
, end
, level
, true, true, info
);
907 /* Map a device to its corresponding domain (context-entry) */
908 static int vtd_dev_to_context_entry(IntelIOMMUState
*s
, uint8_t bus_num
,
909 uint8_t devfn
, VTDContextEntry
*ce
)
913 X86IOMMUState
*x86_iommu
= X86_IOMMU_DEVICE(s
);
915 ret_fr
= vtd_get_root_entry(s
, bus_num
, &re
);
920 if (!vtd_root_entry_present(&re
)) {
921 /* Not error - it's okay we don't have root entry. */
922 trace_vtd_re_not_present(bus_num
);
923 return -VTD_FR_ROOT_ENTRY_P
;
926 if (re
.rsvd
|| (re
.val
& VTD_ROOT_ENTRY_RSVD(s
->aw_bits
))) {
927 trace_vtd_re_invalid(re
.rsvd
, re
.val
);
928 return -VTD_FR_ROOT_ENTRY_RSVD
;
931 ret_fr
= vtd_get_context_entry_from_root(&re
, devfn
, ce
);
936 if (!vtd_ce_present(ce
)) {
937 /* Not error - it's okay we don't have context entry. */
938 trace_vtd_ce_not_present(bus_num
, devfn
);
939 return -VTD_FR_CONTEXT_ENTRY_P
;
942 if ((ce
->hi
& VTD_CONTEXT_ENTRY_RSVD_HI
) ||
943 (ce
->lo
& VTD_CONTEXT_ENTRY_RSVD_LO(s
->aw_bits
))) {
944 trace_vtd_ce_invalid(ce
->hi
, ce
->lo
);
945 return -VTD_FR_CONTEXT_ENTRY_RSVD
;
948 /* Check if the programming of context-entry is valid */
949 if (!vtd_is_level_supported(s
, vtd_ce_get_level(ce
))) {
950 trace_vtd_ce_invalid(ce
->hi
, ce
->lo
);
951 return -VTD_FR_CONTEXT_ENTRY_INV
;
954 /* Do translation type check */
955 if (!vtd_ce_type_check(x86_iommu
, ce
)) {
956 trace_vtd_ce_invalid(ce
->hi
, ce
->lo
);
957 return -VTD_FR_CONTEXT_ENTRY_INV
;
964 * Fetch translation type for specific device. Returns <0 if error
965 * happens, otherwise return the shifted type to check against
968 static int vtd_dev_get_trans_type(VTDAddressSpace
*as
)
976 ret
= vtd_dev_to_context_entry(s
, pci_bus_num(as
->bus
),
982 return vtd_ce_get_type(&ce
);
985 static bool vtd_dev_pt_enabled(VTDAddressSpace
*as
)
991 ret
= vtd_dev_get_trans_type(as
);
994 * Possibly failed to parse the context entry for some reason
995 * (e.g., during init, or any guest configuration errors on
996 * context entries). We should assume PT not enabled for
1002 return ret
== VTD_CONTEXT_TT_PASS_THROUGH
;
1005 /* Return whether the device is using IOMMU translation. */
1006 static bool vtd_switch_address_space(VTDAddressSpace
*as
)
1009 /* Whether we need to take the BQL on our own */
1010 bool take_bql
= !qemu_mutex_iothread_locked();
1014 use_iommu
= as
->iommu_state
->dmar_enabled
& !vtd_dev_pt_enabled(as
);
1016 trace_vtd_switch_address_space(pci_bus_num(as
->bus
),
1017 VTD_PCI_SLOT(as
->devfn
),
1018 VTD_PCI_FUNC(as
->devfn
),
1022 * It's possible that we reach here without BQL, e.g., when called
1023 * from vtd_pt_enable_fast_path(). However the memory APIs need
1024 * it. We'd better make sure we have had it already, or, take it.
1027 qemu_mutex_lock_iothread();
1030 /* Turn off first then on the other */
1032 memory_region_set_enabled(&as
->sys_alias
, false);
1033 memory_region_set_enabled(MEMORY_REGION(&as
->iommu
), true);
1035 memory_region_set_enabled(MEMORY_REGION(&as
->iommu
), false);
1036 memory_region_set_enabled(&as
->sys_alias
, true);
1040 qemu_mutex_unlock_iothread();
1046 static void vtd_switch_address_space_all(IntelIOMMUState
*s
)
1048 GHashTableIter iter
;
1052 g_hash_table_iter_init(&iter
, s
->vtd_as_by_busptr
);
1053 while (g_hash_table_iter_next(&iter
, NULL
, (void **)&vtd_bus
)) {
1054 for (i
= 0; i
< PCI_DEVFN_MAX
; i
++) {
1055 if (!vtd_bus
->dev_as
[i
]) {
1058 vtd_switch_address_space(vtd_bus
->dev_as
[i
]);
1063 static inline uint16_t vtd_make_source_id(uint8_t bus_num
, uint8_t devfn
)
1065 return ((bus_num
& 0xffUL
) << 8) | (devfn
& 0xffUL
);
1068 static const bool vtd_qualified_faults
[] = {
1069 [VTD_FR_RESERVED
] = false,
1070 [VTD_FR_ROOT_ENTRY_P
] = false,
1071 [VTD_FR_CONTEXT_ENTRY_P
] = true,
1072 [VTD_FR_CONTEXT_ENTRY_INV
] = true,
1073 [VTD_FR_ADDR_BEYOND_MGAW
] = true,
1074 [VTD_FR_WRITE
] = true,
1075 [VTD_FR_READ
] = true,
1076 [VTD_FR_PAGING_ENTRY_INV
] = true,
1077 [VTD_FR_ROOT_TABLE_INV
] = false,
1078 [VTD_FR_CONTEXT_TABLE_INV
] = false,
1079 [VTD_FR_ROOT_ENTRY_RSVD
] = false,
1080 [VTD_FR_PAGING_ENTRY_RSVD
] = true,
1081 [VTD_FR_CONTEXT_ENTRY_TT
] = true,
1082 [VTD_FR_RESERVED_ERR
] = false,
1083 [VTD_FR_MAX
] = false,
1086 /* To see if a fault condition is "qualified", which is reported to software
1087 * only if the FPD field in the context-entry used to process the faulting
1090 static inline bool vtd_is_qualified_fault(VTDFaultReason fault
)
1092 return vtd_qualified_faults
[fault
];
1095 static inline bool vtd_is_interrupt_addr(hwaddr addr
)
1097 return VTD_INTERRUPT_ADDR_FIRST
<= addr
&& addr
<= VTD_INTERRUPT_ADDR_LAST
;
1100 static void vtd_pt_enable_fast_path(IntelIOMMUState
*s
, uint16_t source_id
)
1103 VTDAddressSpace
*vtd_as
;
1104 bool success
= false;
1106 vtd_bus
= vtd_find_as_from_bus_num(s
, VTD_SID_TO_BUS(source_id
));
1111 vtd_as
= vtd_bus
->dev_as
[VTD_SID_TO_DEVFN(source_id
)];
1116 if (vtd_switch_address_space(vtd_as
) == false) {
1117 /* We switched off IOMMU region successfully. */
1122 trace_vtd_pt_enable_fast_path(source_id
, success
);
1125 /* Map dev to context-entry then do a paging-structures walk to do a iommu
1128 * Called from RCU critical section.
1130 * @bus_num: The bus number
1131 * @devfn: The devfn, which is the combined of device and function number
1132 * @is_write: The access is a write operation
1133 * @entry: IOMMUTLBEntry that contain the addr to be translated and result
1135 * Returns true if translation is successful, otherwise false.
1137 static bool vtd_do_iommu_translate(VTDAddressSpace
*vtd_as
, PCIBus
*bus
,
1138 uint8_t devfn
, hwaddr addr
, bool is_write
,
1139 IOMMUTLBEntry
*entry
)
1141 IntelIOMMUState
*s
= vtd_as
->iommu_state
;
1143 uint8_t bus_num
= pci_bus_num(bus
);
1144 VTDContextCacheEntry
*cc_entry
;
1145 uint64_t slpte
, page_mask
;
1147 uint16_t source_id
= vtd_make_source_id(bus_num
, devfn
);
1149 bool is_fpd_set
= false;
1152 uint8_t access_flags
;
1153 VTDIOTLBEntry
*iotlb_entry
;
1156 * We have standalone memory region for interrupt addresses, we
1157 * should never receive translation requests in this region.
1159 assert(!vtd_is_interrupt_addr(addr
));
1163 cc_entry
= &vtd_as
->context_cache_entry
;
1165 /* Try to fetch slpte form IOTLB */
1166 iotlb_entry
= vtd_lookup_iotlb(s
, source_id
, addr
);
1168 trace_vtd_iotlb_page_hit(source_id
, addr
, iotlb_entry
->slpte
,
1169 iotlb_entry
->domain_id
);
1170 slpte
= iotlb_entry
->slpte
;
1171 access_flags
= iotlb_entry
->access_flags
;
1172 page_mask
= iotlb_entry
->mask
;
1176 /* Try to fetch context-entry from cache first */
1177 if (cc_entry
->context_cache_gen
== s
->context_cache_gen
) {
1178 trace_vtd_iotlb_cc_hit(bus_num
, devfn
, cc_entry
->context_entry
.hi
,
1179 cc_entry
->context_entry
.lo
,
1180 cc_entry
->context_cache_gen
);
1181 ce
= cc_entry
->context_entry
;
1182 is_fpd_set
= ce
.lo
& VTD_CONTEXT_ENTRY_FPD
;
1184 ret_fr
= vtd_dev_to_context_entry(s
, bus_num
, devfn
, &ce
);
1185 is_fpd_set
= ce
.lo
& VTD_CONTEXT_ENTRY_FPD
;
1188 if (is_fpd_set
&& vtd_is_qualified_fault(ret_fr
)) {
1189 trace_vtd_fault_disabled();
1191 vtd_report_dmar_fault(s
, source_id
, addr
, ret_fr
, is_write
);
1195 /* Update context-cache */
1196 trace_vtd_iotlb_cc_update(bus_num
, devfn
, ce
.hi
, ce
.lo
,
1197 cc_entry
->context_cache_gen
,
1198 s
->context_cache_gen
);
1199 cc_entry
->context_entry
= ce
;
1200 cc_entry
->context_cache_gen
= s
->context_cache_gen
;
1204 * We don't need to translate for pass-through context entries.
1205 * Also, let's ignore IOTLB caching as well for PT devices.
1207 if (vtd_ce_get_type(&ce
) == VTD_CONTEXT_TT_PASS_THROUGH
) {
1208 entry
->iova
= addr
& VTD_PAGE_MASK_4K
;
1209 entry
->translated_addr
= entry
->iova
;
1210 entry
->addr_mask
= ~VTD_PAGE_MASK_4K
;
1211 entry
->perm
= IOMMU_RW
;
1212 trace_vtd_translate_pt(source_id
, entry
->iova
);
1215 * When this happens, it means firstly caching-mode is not
1216 * enabled, and this is the first passthrough translation for
1217 * the device. Let's enable the fast path for passthrough.
1219 * When passthrough is disabled again for the device, we can
1220 * capture it via the context entry invalidation, then the
1221 * IOMMU region can be swapped back.
1223 vtd_pt_enable_fast_path(s
, source_id
);
1224 vtd_iommu_unlock(s
);
1228 ret_fr
= vtd_iova_to_slpte(&ce
, addr
, is_write
, &slpte
, &level
,
1229 &reads
, &writes
, s
->aw_bits
);
1232 if (is_fpd_set
&& vtd_is_qualified_fault(ret_fr
)) {
1233 trace_vtd_fault_disabled();
1235 vtd_report_dmar_fault(s
, source_id
, addr
, ret_fr
, is_write
);
1240 page_mask
= vtd_slpt_level_page_mask(level
);
1241 access_flags
= IOMMU_ACCESS_FLAG(reads
, writes
);
1242 vtd_update_iotlb(s
, source_id
, VTD_CONTEXT_ENTRY_DID(ce
.hi
), addr
, slpte
,
1243 access_flags
, level
);
1245 vtd_iommu_unlock(s
);
1246 entry
->iova
= addr
& page_mask
;
1247 entry
->translated_addr
= vtd_get_slpte_addr(slpte
, s
->aw_bits
) & page_mask
;
1248 entry
->addr_mask
= ~page_mask
;
1249 entry
->perm
= access_flags
;
1253 vtd_iommu_unlock(s
);
1255 entry
->translated_addr
= 0;
1256 entry
->addr_mask
= 0;
1257 entry
->perm
= IOMMU_NONE
;
1261 static void vtd_root_table_setup(IntelIOMMUState
*s
)
1263 s
->root
= vtd_get_quad_raw(s
, DMAR_RTADDR_REG
);
1264 s
->root_extended
= s
->root
& VTD_RTADDR_RTT
;
1265 s
->root
&= VTD_RTADDR_ADDR_MASK(s
->aw_bits
);
1267 trace_vtd_reg_dmar_root(s
->root
, s
->root_extended
);
1270 static void vtd_iec_notify_all(IntelIOMMUState
*s
, bool global
,
1271 uint32_t index
, uint32_t mask
)
1273 x86_iommu_iec_notify_all(X86_IOMMU_DEVICE(s
), global
, index
, mask
);
1276 static void vtd_interrupt_remap_table_setup(IntelIOMMUState
*s
)
1279 value
= vtd_get_quad_raw(s
, DMAR_IRTA_REG
);
1280 s
->intr_size
= 1UL << ((value
& VTD_IRTA_SIZE_MASK
) + 1);
1281 s
->intr_root
= value
& VTD_IRTA_ADDR_MASK(s
->aw_bits
);
1282 s
->intr_eime
= value
& VTD_IRTA_EIME
;
1284 /* Notify global invalidation */
1285 vtd_iec_notify_all(s
, true, 0, 0);
1287 trace_vtd_reg_ir_root(s
->intr_root
, s
->intr_size
);
1290 static void vtd_iommu_replay_all(IntelIOMMUState
*s
)
1292 VTDAddressSpace
*vtd_as
;
1294 QLIST_FOREACH(vtd_as
, &s
->vtd_as_with_notifiers
, next
) {
1295 memory_region_iommu_replay_all(&vtd_as
->iommu
);
1299 static void vtd_context_global_invalidate(IntelIOMMUState
*s
)
1301 trace_vtd_inv_desc_cc_global();
1302 /* Protects context cache */
1304 s
->context_cache_gen
++;
1305 if (s
->context_cache_gen
== VTD_CONTEXT_CACHE_GEN_MAX
) {
1306 vtd_reset_context_cache_locked(s
);
1308 vtd_iommu_unlock(s
);
1309 vtd_switch_address_space_all(s
);
1311 * From VT-d spec 6.5.2.1, a global context entry invalidation
1312 * should be followed by a IOTLB global invalidation, so we should
1313 * be safe even without this. Hoewever, let's replay the region as
1314 * well to be safer, and go back here when we need finer tunes for
1315 * VT-d emulation codes.
1317 vtd_iommu_replay_all(s
);
1320 /* Do a context-cache device-selective invalidation.
1321 * @func_mask: FM field after shifting
1323 static void vtd_context_device_invalidate(IntelIOMMUState
*s
,
1329 VTDAddressSpace
*vtd_as
;
1330 uint8_t bus_n
, devfn
;
1333 trace_vtd_inv_desc_cc_devices(source_id
, func_mask
);
1335 switch (func_mask
& 3) {
1337 mask
= 0; /* No bits in the SID field masked */
1340 mask
= 4; /* Mask bit 2 in the SID field */
1343 mask
= 6; /* Mask bit 2:1 in the SID field */
1346 mask
= 7; /* Mask bit 2:0 in the SID field */
1351 bus_n
= VTD_SID_TO_BUS(source_id
);
1352 vtd_bus
= vtd_find_as_from_bus_num(s
, bus_n
);
1354 devfn
= VTD_SID_TO_DEVFN(source_id
);
1355 for (devfn_it
= 0; devfn_it
< PCI_DEVFN_MAX
; ++devfn_it
) {
1356 vtd_as
= vtd_bus
->dev_as
[devfn_it
];
1357 if (vtd_as
&& ((devfn_it
& mask
) == (devfn
& mask
))) {
1358 trace_vtd_inv_desc_cc_device(bus_n
, VTD_PCI_SLOT(devfn_it
),
1359 VTD_PCI_FUNC(devfn_it
));
1361 vtd_as
->context_cache_entry
.context_cache_gen
= 0;
1362 vtd_iommu_unlock(s
);
1364 * Do switch address space when needed, in case if the
1365 * device passthrough bit is switched.
1367 vtd_switch_address_space(vtd_as
);
1369 * So a device is moving out of (or moving into) a
1370 * domain, a replay() suites here to notify all the
1371 * IOMMU_NOTIFIER_MAP registers about this change.
1372 * This won't bring bad even if we have no such
1373 * notifier registered - the IOMMU notification
1374 * framework will skip MAP notifications if that
1377 memory_region_iommu_replay_all(&vtd_as
->iommu
);
1383 /* Context-cache invalidation
1384 * Returns the Context Actual Invalidation Granularity.
1385 * @val: the content of the CCMD_REG
1387 static uint64_t vtd_context_cache_invalidate(IntelIOMMUState
*s
, uint64_t val
)
1390 uint64_t type
= val
& VTD_CCMD_CIRG_MASK
;
1393 case VTD_CCMD_DOMAIN_INVL
:
1395 case VTD_CCMD_GLOBAL_INVL
:
1396 caig
= VTD_CCMD_GLOBAL_INVL_A
;
1397 vtd_context_global_invalidate(s
);
1400 case VTD_CCMD_DEVICE_INVL
:
1401 caig
= VTD_CCMD_DEVICE_INVL_A
;
1402 vtd_context_device_invalidate(s
, VTD_CCMD_SID(val
), VTD_CCMD_FM(val
));
1406 trace_vtd_err("Context cache invalidate type error.");
1412 static void vtd_iotlb_global_invalidate(IntelIOMMUState
*s
)
1414 trace_vtd_inv_desc_iotlb_global();
1416 vtd_iommu_replay_all(s
);
1419 static void vtd_iotlb_domain_invalidate(IntelIOMMUState
*s
, uint16_t domain_id
)
1422 VTDAddressSpace
*vtd_as
;
1424 trace_vtd_inv_desc_iotlb_domain(domain_id
);
1427 g_hash_table_foreach_remove(s
->iotlb
, vtd_hash_remove_by_domain
,
1429 vtd_iommu_unlock(s
);
1431 QLIST_FOREACH(vtd_as
, &s
->vtd_as_with_notifiers
, next
) {
1432 if (!vtd_dev_to_context_entry(s
, pci_bus_num(vtd_as
->bus
),
1433 vtd_as
->devfn
, &ce
) &&
1434 domain_id
== VTD_CONTEXT_ENTRY_DID(ce
.hi
)) {
1435 memory_region_iommu_replay_all(&vtd_as
->iommu
);
1440 static int vtd_page_invalidate_notify_hook(IOMMUTLBEntry
*entry
,
1443 memory_region_notify_iommu((IOMMUMemoryRegion
*)private, *entry
);
1447 static void vtd_iotlb_page_invalidate_notify(IntelIOMMUState
*s
,
1448 uint16_t domain_id
, hwaddr addr
,
1451 VTDAddressSpace
*vtd_as
;
1454 hwaddr size
= (1 << am
) * VTD_PAGE_SIZE
;
1456 QLIST_FOREACH(vtd_as
, &(s
->vtd_as_with_notifiers
), next
) {
1457 ret
= vtd_dev_to_context_entry(s
, pci_bus_num(vtd_as
->bus
),
1458 vtd_as
->devfn
, &ce
);
1459 if (!ret
&& domain_id
== VTD_CONTEXT_ENTRY_DID(ce
.hi
)) {
1460 if (vtd_as_has_map_notifier(vtd_as
)) {
1461 vtd_page_walk_info info
= {
1462 .hook_fn
= vtd_page_invalidate_notify_hook
,
1463 .private = (void *)&vtd_as
->iommu
,
1464 .notify_unmap
= true,
1469 * As long as we have MAP notifications registered in
1470 * any of our IOMMU notifiers, we need to sync the
1471 * shadow page table.
1473 vtd_page_walk(&ce
, addr
, addr
+ size
, &info
);
1476 * For UNMAP-only notifiers, we don't need to walk the
1477 * page tables. We just deliver the PSI down to
1478 * invalidate caches.
1480 IOMMUTLBEntry entry
= {
1481 .target_as
= &address_space_memory
,
1483 .translated_addr
= 0,
1484 .addr_mask
= size
- 1,
1487 memory_region_notify_iommu(&vtd_as
->iommu
, entry
);
1493 static void vtd_iotlb_page_invalidate(IntelIOMMUState
*s
, uint16_t domain_id
,
1494 hwaddr addr
, uint8_t am
)
1496 VTDIOTLBPageInvInfo info
;
1498 trace_vtd_inv_desc_iotlb_pages(domain_id
, addr
, am
);
1500 assert(am
<= VTD_MAMV
);
1501 info
.domain_id
= domain_id
;
1503 info
.mask
= ~((1 << am
) - 1);
1505 g_hash_table_foreach_remove(s
->iotlb
, vtd_hash_remove_by_page
, &info
);
1506 vtd_iommu_unlock(s
);
1507 vtd_iotlb_page_invalidate_notify(s
, domain_id
, addr
, am
);
1511 * Returns the IOTLB Actual Invalidation Granularity.
1512 * @val: the content of the IOTLB_REG
1514 static uint64_t vtd_iotlb_flush(IntelIOMMUState
*s
, uint64_t val
)
1517 uint64_t type
= val
& VTD_TLB_FLUSH_GRANU_MASK
;
1523 case VTD_TLB_GLOBAL_FLUSH
:
1524 iaig
= VTD_TLB_GLOBAL_FLUSH_A
;
1525 vtd_iotlb_global_invalidate(s
);
1528 case VTD_TLB_DSI_FLUSH
:
1529 domain_id
= VTD_TLB_DID(val
);
1530 iaig
= VTD_TLB_DSI_FLUSH_A
;
1531 vtd_iotlb_domain_invalidate(s
, domain_id
);
1534 case VTD_TLB_PSI_FLUSH
:
1535 domain_id
= VTD_TLB_DID(val
);
1536 addr
= vtd_get_quad_raw(s
, DMAR_IVA_REG
);
1537 am
= VTD_IVA_AM(addr
);
1538 addr
= VTD_IVA_ADDR(addr
);
1539 if (am
> VTD_MAMV
) {
1540 trace_vtd_err("IOTLB PSI flush: address mask overflow.");
1544 iaig
= VTD_TLB_PSI_FLUSH_A
;
1545 vtd_iotlb_page_invalidate(s
, domain_id
, addr
, am
);
1549 trace_vtd_err("IOTLB flush: invalid granularity.");
1555 static void vtd_fetch_inv_desc(IntelIOMMUState
*s
);
1557 static inline bool vtd_queued_inv_disable_check(IntelIOMMUState
*s
)
1559 return s
->qi_enabled
&& (s
->iq_tail
== s
->iq_head
) &&
1560 (s
->iq_last_desc_type
== VTD_INV_DESC_WAIT
);
1563 static void vtd_handle_gcmd_qie(IntelIOMMUState
*s
, bool en
)
1565 uint64_t iqa_val
= vtd_get_quad_raw(s
, DMAR_IQA_REG
);
1567 trace_vtd_inv_qi_enable(en
);
1570 s
->iq
= iqa_val
& VTD_IQA_IQA_MASK(s
->aw_bits
);
1571 /* 2^(x+8) entries */
1572 s
->iq_size
= 1UL << ((iqa_val
& VTD_IQA_QS
) + 8);
1573 s
->qi_enabled
= true;
1574 trace_vtd_inv_qi_setup(s
->iq
, s
->iq_size
);
1575 /* Ok - report back to driver */
1576 vtd_set_clear_mask_long(s
, DMAR_GSTS_REG
, 0, VTD_GSTS_QIES
);
1578 if (s
->iq_tail
!= 0) {
1580 * This is a spec violation but Windows guests are known to set up
1581 * Queued Invalidation this way so we allow the write and process
1582 * Invalidation Descriptors right away.
1584 trace_vtd_warn_invalid_qi_tail(s
->iq_tail
);
1585 if (!(vtd_get_long_raw(s
, DMAR_FSTS_REG
) & VTD_FSTS_IQE
)) {
1586 vtd_fetch_inv_desc(s
);
1590 if (vtd_queued_inv_disable_check(s
)) {
1591 /* disable Queued Invalidation */
1592 vtd_set_quad_raw(s
, DMAR_IQH_REG
, 0);
1594 s
->qi_enabled
= false;
1595 /* Ok - report back to driver */
1596 vtd_set_clear_mask_long(s
, DMAR_GSTS_REG
, VTD_GSTS_QIES
, 0);
1598 trace_vtd_err_qi_disable(s
->iq_head
, s
->iq_tail
, s
->iq_last_desc_type
);
1603 /* Set Root Table Pointer */
1604 static void vtd_handle_gcmd_srtp(IntelIOMMUState
*s
)
1606 vtd_root_table_setup(s
);
1607 /* Ok - report back to driver */
1608 vtd_set_clear_mask_long(s
, DMAR_GSTS_REG
, 0, VTD_GSTS_RTPS
);
1611 /* Set Interrupt Remap Table Pointer */
1612 static void vtd_handle_gcmd_sirtp(IntelIOMMUState
*s
)
1614 vtd_interrupt_remap_table_setup(s
);
1615 /* Ok - report back to driver */
1616 vtd_set_clear_mask_long(s
, DMAR_GSTS_REG
, 0, VTD_GSTS_IRTPS
);
1619 /* Handle Translation Enable/Disable */
1620 static void vtd_handle_gcmd_te(IntelIOMMUState
*s
, bool en
)
1622 if (s
->dmar_enabled
== en
) {
1626 trace_vtd_dmar_enable(en
);
1629 s
->dmar_enabled
= true;
1630 /* Ok - report back to driver */
1631 vtd_set_clear_mask_long(s
, DMAR_GSTS_REG
, 0, VTD_GSTS_TES
);
1633 s
->dmar_enabled
= false;
1635 /* Clear the index of Fault Recording Register */
1636 s
->next_frcd_reg
= 0;
1637 /* Ok - report back to driver */
1638 vtd_set_clear_mask_long(s
, DMAR_GSTS_REG
, VTD_GSTS_TES
, 0);
1641 vtd_switch_address_space_all(s
);
1644 /* Handle Interrupt Remap Enable/Disable */
1645 static void vtd_handle_gcmd_ire(IntelIOMMUState
*s
, bool en
)
1647 trace_vtd_ir_enable(en
);
1650 s
->intr_enabled
= true;
1651 /* Ok - report back to driver */
1652 vtd_set_clear_mask_long(s
, DMAR_GSTS_REG
, 0, VTD_GSTS_IRES
);
1654 s
->intr_enabled
= false;
1655 /* Ok - report back to driver */
1656 vtd_set_clear_mask_long(s
, DMAR_GSTS_REG
, VTD_GSTS_IRES
, 0);
1660 /* Handle write to Global Command Register */
1661 static void vtd_handle_gcmd_write(IntelIOMMUState
*s
)
1663 uint32_t status
= vtd_get_long_raw(s
, DMAR_GSTS_REG
);
1664 uint32_t val
= vtd_get_long_raw(s
, DMAR_GCMD_REG
);
1665 uint32_t changed
= status
^ val
;
1667 trace_vtd_reg_write_gcmd(status
, val
);
1668 if (changed
& VTD_GCMD_TE
) {
1669 /* Translation enable/disable */
1670 vtd_handle_gcmd_te(s
, val
& VTD_GCMD_TE
);
1672 if (val
& VTD_GCMD_SRTP
) {
1673 /* Set/update the root-table pointer */
1674 vtd_handle_gcmd_srtp(s
);
1676 if (changed
& VTD_GCMD_QIE
) {
1677 /* Queued Invalidation Enable */
1678 vtd_handle_gcmd_qie(s
, val
& VTD_GCMD_QIE
);
1680 if (val
& VTD_GCMD_SIRTP
) {
1681 /* Set/update the interrupt remapping root-table pointer */
1682 vtd_handle_gcmd_sirtp(s
);
1684 if (changed
& VTD_GCMD_IRE
) {
1685 /* Interrupt remap enable/disable */
1686 vtd_handle_gcmd_ire(s
, val
& VTD_GCMD_IRE
);
1690 /* Handle write to Context Command Register */
1691 static void vtd_handle_ccmd_write(IntelIOMMUState
*s
)
1694 uint64_t val
= vtd_get_quad_raw(s
, DMAR_CCMD_REG
);
1696 /* Context-cache invalidation request */
1697 if (val
& VTD_CCMD_ICC
) {
1698 if (s
->qi_enabled
) {
1699 trace_vtd_err("Queued Invalidation enabled, "
1700 "should not use register-based invalidation");
1703 ret
= vtd_context_cache_invalidate(s
, val
);
1704 /* Invalidation completed. Change something to show */
1705 vtd_set_clear_mask_quad(s
, DMAR_CCMD_REG
, VTD_CCMD_ICC
, 0ULL);
1706 ret
= vtd_set_clear_mask_quad(s
, DMAR_CCMD_REG
, VTD_CCMD_CAIG_MASK
,
1711 /* Handle write to IOTLB Invalidation Register */
1712 static void vtd_handle_iotlb_write(IntelIOMMUState
*s
)
1715 uint64_t val
= vtd_get_quad_raw(s
, DMAR_IOTLB_REG
);
1717 /* IOTLB invalidation request */
1718 if (val
& VTD_TLB_IVT
) {
1719 if (s
->qi_enabled
) {
1720 trace_vtd_err("Queued Invalidation enabled, "
1721 "should not use register-based invalidation.");
1724 ret
= vtd_iotlb_flush(s
, val
);
1725 /* Invalidation completed. Change something to show */
1726 vtd_set_clear_mask_quad(s
, DMAR_IOTLB_REG
, VTD_TLB_IVT
, 0ULL);
1727 ret
= vtd_set_clear_mask_quad(s
, DMAR_IOTLB_REG
,
1728 VTD_TLB_FLUSH_GRANU_MASK_A
, ret
);
1732 /* Fetch an Invalidation Descriptor from the Invalidation Queue */
1733 static bool vtd_get_inv_desc(dma_addr_t base_addr
, uint32_t offset
,
1734 VTDInvDesc
*inv_desc
)
1736 dma_addr_t addr
= base_addr
+ offset
* sizeof(*inv_desc
);
1737 if (dma_memory_read(&address_space_memory
, addr
, inv_desc
,
1738 sizeof(*inv_desc
))) {
1739 trace_vtd_err("Read INV DESC failed.");
1744 inv_desc
->lo
= le64_to_cpu(inv_desc
->lo
);
1745 inv_desc
->hi
= le64_to_cpu(inv_desc
->hi
);
1749 static bool vtd_process_wait_desc(IntelIOMMUState
*s
, VTDInvDesc
*inv_desc
)
1751 if ((inv_desc
->hi
& VTD_INV_DESC_WAIT_RSVD_HI
) ||
1752 (inv_desc
->lo
& VTD_INV_DESC_WAIT_RSVD_LO
)) {
1753 trace_vtd_inv_desc_wait_invalid(inv_desc
->hi
, inv_desc
->lo
);
1756 if (inv_desc
->lo
& VTD_INV_DESC_WAIT_SW
) {
1758 uint32_t status_data
= (uint32_t)(inv_desc
->lo
>>
1759 VTD_INV_DESC_WAIT_DATA_SHIFT
);
1761 assert(!(inv_desc
->lo
& VTD_INV_DESC_WAIT_IF
));
1763 /* FIXME: need to be masked with HAW? */
1764 dma_addr_t status_addr
= inv_desc
->hi
;
1765 trace_vtd_inv_desc_wait_sw(status_addr
, status_data
);
1766 status_data
= cpu_to_le32(status_data
);
1767 if (dma_memory_write(&address_space_memory
, status_addr
, &status_data
,
1768 sizeof(status_data
))) {
1769 trace_vtd_inv_desc_wait_write_fail(inv_desc
->hi
, inv_desc
->lo
);
1772 } else if (inv_desc
->lo
& VTD_INV_DESC_WAIT_IF
) {
1773 /* Interrupt flag */
1774 vtd_generate_completion_event(s
);
1776 trace_vtd_inv_desc_wait_invalid(inv_desc
->hi
, inv_desc
->lo
);
1782 static bool vtd_process_context_cache_desc(IntelIOMMUState
*s
,
1783 VTDInvDesc
*inv_desc
)
1785 uint16_t sid
, fmask
;
1787 if ((inv_desc
->lo
& VTD_INV_DESC_CC_RSVD
) || inv_desc
->hi
) {
1788 trace_vtd_inv_desc_cc_invalid(inv_desc
->hi
, inv_desc
->lo
);
1791 switch (inv_desc
->lo
& VTD_INV_DESC_CC_G
) {
1792 case VTD_INV_DESC_CC_DOMAIN
:
1793 trace_vtd_inv_desc_cc_domain(
1794 (uint16_t)VTD_INV_DESC_CC_DID(inv_desc
->lo
));
1796 case VTD_INV_DESC_CC_GLOBAL
:
1797 vtd_context_global_invalidate(s
);
1800 case VTD_INV_DESC_CC_DEVICE
:
1801 sid
= VTD_INV_DESC_CC_SID(inv_desc
->lo
);
1802 fmask
= VTD_INV_DESC_CC_FM(inv_desc
->lo
);
1803 vtd_context_device_invalidate(s
, sid
, fmask
);
1807 trace_vtd_inv_desc_cc_invalid(inv_desc
->hi
, inv_desc
->lo
);
1813 static bool vtd_process_iotlb_desc(IntelIOMMUState
*s
, VTDInvDesc
*inv_desc
)
1819 if ((inv_desc
->lo
& VTD_INV_DESC_IOTLB_RSVD_LO
) ||
1820 (inv_desc
->hi
& VTD_INV_DESC_IOTLB_RSVD_HI
)) {
1821 trace_vtd_inv_desc_iotlb_invalid(inv_desc
->hi
, inv_desc
->lo
);
1825 switch (inv_desc
->lo
& VTD_INV_DESC_IOTLB_G
) {
1826 case VTD_INV_DESC_IOTLB_GLOBAL
:
1827 vtd_iotlb_global_invalidate(s
);
1830 case VTD_INV_DESC_IOTLB_DOMAIN
:
1831 domain_id
= VTD_INV_DESC_IOTLB_DID(inv_desc
->lo
);
1832 vtd_iotlb_domain_invalidate(s
, domain_id
);
1835 case VTD_INV_DESC_IOTLB_PAGE
:
1836 domain_id
= VTD_INV_DESC_IOTLB_DID(inv_desc
->lo
);
1837 addr
= VTD_INV_DESC_IOTLB_ADDR(inv_desc
->hi
);
1838 am
= VTD_INV_DESC_IOTLB_AM(inv_desc
->hi
);
1839 if (am
> VTD_MAMV
) {
1840 trace_vtd_inv_desc_iotlb_invalid(inv_desc
->hi
, inv_desc
->lo
);
1843 vtd_iotlb_page_invalidate(s
, domain_id
, addr
, am
);
1847 trace_vtd_inv_desc_iotlb_invalid(inv_desc
->hi
, inv_desc
->lo
);
1853 static bool vtd_process_inv_iec_desc(IntelIOMMUState
*s
,
1854 VTDInvDesc
*inv_desc
)
1856 trace_vtd_inv_desc_iec(inv_desc
->iec
.granularity
,
1857 inv_desc
->iec
.index
,
1858 inv_desc
->iec
.index_mask
);
1860 vtd_iec_notify_all(s
, !inv_desc
->iec
.granularity
,
1861 inv_desc
->iec
.index
,
1862 inv_desc
->iec
.index_mask
);
1866 static bool vtd_process_device_iotlb_desc(IntelIOMMUState
*s
,
1867 VTDInvDesc
*inv_desc
)
1869 VTDAddressSpace
*vtd_dev_as
;
1870 IOMMUTLBEntry entry
;
1871 struct VTDBus
*vtd_bus
;
1879 addr
= VTD_INV_DESC_DEVICE_IOTLB_ADDR(inv_desc
->hi
);
1880 sid
= VTD_INV_DESC_DEVICE_IOTLB_SID(inv_desc
->lo
);
1883 size
= VTD_INV_DESC_DEVICE_IOTLB_SIZE(inv_desc
->hi
);
1885 if ((inv_desc
->lo
& VTD_INV_DESC_DEVICE_IOTLB_RSVD_LO
) ||
1886 (inv_desc
->hi
& VTD_INV_DESC_DEVICE_IOTLB_RSVD_HI
)) {
1887 trace_vtd_inv_desc_iotlb_invalid(inv_desc
->hi
, inv_desc
->lo
);
1891 vtd_bus
= vtd_find_as_from_bus_num(s
, bus_num
);
1896 vtd_dev_as
= vtd_bus
->dev_as
[devfn
];
1901 /* According to ATS spec table 2.4:
1902 * S = 0, bits 15:12 = xxxx range size: 4K
1903 * S = 1, bits 15:12 = xxx0 range size: 8K
1904 * S = 1, bits 15:12 = xx01 range size: 16K
1905 * S = 1, bits 15:12 = x011 range size: 32K
1906 * S = 1, bits 15:12 = 0111 range size: 64K
1910 sz
= (VTD_PAGE_SIZE
* 2) << cto64(addr
>> VTD_PAGE_SHIFT
);
1916 entry
.target_as
= &vtd_dev_as
->as
;
1917 entry
.addr_mask
= sz
- 1;
1919 entry
.perm
= IOMMU_NONE
;
1920 entry
.translated_addr
= 0;
1921 memory_region_notify_iommu(&vtd_dev_as
->iommu
, entry
);
1927 static bool vtd_process_inv_desc(IntelIOMMUState
*s
)
1929 VTDInvDesc inv_desc
;
1932 trace_vtd_inv_qi_head(s
->iq_head
);
1933 if (!vtd_get_inv_desc(s
->iq
, s
->iq_head
, &inv_desc
)) {
1934 s
->iq_last_desc_type
= VTD_INV_DESC_NONE
;
1937 desc_type
= inv_desc
.lo
& VTD_INV_DESC_TYPE
;
1938 /* FIXME: should update at first or at last? */
1939 s
->iq_last_desc_type
= desc_type
;
1941 switch (desc_type
) {
1942 case VTD_INV_DESC_CC
:
1943 trace_vtd_inv_desc("context-cache", inv_desc
.hi
, inv_desc
.lo
);
1944 if (!vtd_process_context_cache_desc(s
, &inv_desc
)) {
1949 case VTD_INV_DESC_IOTLB
:
1950 trace_vtd_inv_desc("iotlb", inv_desc
.hi
, inv_desc
.lo
);
1951 if (!vtd_process_iotlb_desc(s
, &inv_desc
)) {
1956 case VTD_INV_DESC_WAIT
:
1957 trace_vtd_inv_desc("wait", inv_desc
.hi
, inv_desc
.lo
);
1958 if (!vtd_process_wait_desc(s
, &inv_desc
)) {
1963 case VTD_INV_DESC_IEC
:
1964 trace_vtd_inv_desc("iec", inv_desc
.hi
, inv_desc
.lo
);
1965 if (!vtd_process_inv_iec_desc(s
, &inv_desc
)) {
1970 case VTD_INV_DESC_DEVICE
:
1971 trace_vtd_inv_desc("device", inv_desc
.hi
, inv_desc
.lo
);
1972 if (!vtd_process_device_iotlb_desc(s
, &inv_desc
)) {
1978 trace_vtd_inv_desc_invalid(inv_desc
.hi
, inv_desc
.lo
);
1982 if (s
->iq_head
== s
->iq_size
) {
1988 /* Try to fetch and process more Invalidation Descriptors */
1989 static void vtd_fetch_inv_desc(IntelIOMMUState
*s
)
1991 trace_vtd_inv_qi_fetch();
1993 if (s
->iq_tail
>= s
->iq_size
) {
1994 /* Detects an invalid Tail pointer */
1995 trace_vtd_err_qi_tail(s
->iq_tail
, s
->iq_size
);
1996 vtd_handle_inv_queue_error(s
);
1999 while (s
->iq_head
!= s
->iq_tail
) {
2000 if (!vtd_process_inv_desc(s
)) {
2001 /* Invalidation Queue Errors */
2002 vtd_handle_inv_queue_error(s
);
2005 /* Must update the IQH_REG in time */
2006 vtd_set_quad_raw(s
, DMAR_IQH_REG
,
2007 (((uint64_t)(s
->iq_head
)) << VTD_IQH_QH_SHIFT
) &
2012 /* Handle write to Invalidation Queue Tail Register */
2013 static void vtd_handle_iqt_write(IntelIOMMUState
*s
)
2015 uint64_t val
= vtd_get_quad_raw(s
, DMAR_IQT_REG
);
2017 s
->iq_tail
= VTD_IQT_QT(val
);
2018 trace_vtd_inv_qi_tail(s
->iq_tail
);
2020 if (s
->qi_enabled
&& !(vtd_get_long_raw(s
, DMAR_FSTS_REG
) & VTD_FSTS_IQE
)) {
2021 /* Process Invalidation Queue here */
2022 vtd_fetch_inv_desc(s
);
2026 static void vtd_handle_fsts_write(IntelIOMMUState
*s
)
2028 uint32_t fsts_reg
= vtd_get_long_raw(s
, DMAR_FSTS_REG
);
2029 uint32_t fectl_reg
= vtd_get_long_raw(s
, DMAR_FECTL_REG
);
2030 uint32_t status_fields
= VTD_FSTS_PFO
| VTD_FSTS_PPF
| VTD_FSTS_IQE
;
2032 if ((fectl_reg
& VTD_FECTL_IP
) && !(fsts_reg
& status_fields
)) {
2033 vtd_set_clear_mask_long(s
, DMAR_FECTL_REG
, VTD_FECTL_IP
, 0);
2034 trace_vtd_fsts_clear_ip();
2036 /* FIXME: when IQE is Clear, should we try to fetch some Invalidation
2037 * Descriptors if there are any when Queued Invalidation is enabled?
2041 static void vtd_handle_fectl_write(IntelIOMMUState
*s
)
2044 /* FIXME: when software clears the IM field, check the IP field. But do we
2045 * need to compare the old value and the new value to conclude that
2046 * software clears the IM field? Or just check if the IM field is zero?
2048 fectl_reg
= vtd_get_long_raw(s
, DMAR_FECTL_REG
);
2050 trace_vtd_reg_write_fectl(fectl_reg
);
2052 if ((fectl_reg
& VTD_FECTL_IP
) && !(fectl_reg
& VTD_FECTL_IM
)) {
2053 vtd_generate_interrupt(s
, DMAR_FEADDR_REG
, DMAR_FEDATA_REG
);
2054 vtd_set_clear_mask_long(s
, DMAR_FECTL_REG
, VTD_FECTL_IP
, 0);
2058 static void vtd_handle_ics_write(IntelIOMMUState
*s
)
2060 uint32_t ics_reg
= vtd_get_long_raw(s
, DMAR_ICS_REG
);
2061 uint32_t iectl_reg
= vtd_get_long_raw(s
, DMAR_IECTL_REG
);
2063 if ((iectl_reg
& VTD_IECTL_IP
) && !(ics_reg
& VTD_ICS_IWC
)) {
2064 trace_vtd_reg_ics_clear_ip();
2065 vtd_set_clear_mask_long(s
, DMAR_IECTL_REG
, VTD_IECTL_IP
, 0);
2069 static void vtd_handle_iectl_write(IntelIOMMUState
*s
)
2072 /* FIXME: when software clears the IM field, check the IP field. But do we
2073 * need to compare the old value and the new value to conclude that
2074 * software clears the IM field? Or just check if the IM field is zero?
2076 iectl_reg
= vtd_get_long_raw(s
, DMAR_IECTL_REG
);
2078 trace_vtd_reg_write_iectl(iectl_reg
);
2080 if ((iectl_reg
& VTD_IECTL_IP
) && !(iectl_reg
& VTD_IECTL_IM
)) {
2081 vtd_generate_interrupt(s
, DMAR_IEADDR_REG
, DMAR_IEDATA_REG
);
2082 vtd_set_clear_mask_long(s
, DMAR_IECTL_REG
, VTD_IECTL_IP
, 0);
2086 static uint64_t vtd_mem_read(void *opaque
, hwaddr addr
, unsigned size
)
2088 IntelIOMMUState
*s
= opaque
;
2091 trace_vtd_reg_read(addr
, size
);
2093 if (addr
+ size
> DMAR_REG_SIZE
) {
2094 trace_vtd_err("Read MMIO over range.");
2095 return (uint64_t)-1;
2099 /* Root Table Address Register, 64-bit */
2100 case DMAR_RTADDR_REG
:
2102 val
= s
->root
& ((1ULL << 32) - 1);
2108 case DMAR_RTADDR_REG_HI
:
2110 val
= s
->root
>> 32;
2113 /* Invalidation Queue Address Register, 64-bit */
2115 val
= s
->iq
| (vtd_get_quad(s
, DMAR_IQA_REG
) & VTD_IQA_QS
);
2117 val
= val
& ((1ULL << 32) - 1);
2121 case DMAR_IQA_REG_HI
:
2128 val
= vtd_get_long(s
, addr
);
2130 val
= vtd_get_quad(s
, addr
);
2137 static void vtd_mem_write(void *opaque
, hwaddr addr
,
2138 uint64_t val
, unsigned size
)
2140 IntelIOMMUState
*s
= opaque
;
2142 trace_vtd_reg_write(addr
, size
, val
);
2144 if (addr
+ size
> DMAR_REG_SIZE
) {
2145 trace_vtd_err("Write MMIO over range.");
2150 /* Global Command Register, 32-bit */
2152 vtd_set_long(s
, addr
, val
);
2153 vtd_handle_gcmd_write(s
);
2156 /* Context Command Register, 64-bit */
2159 vtd_set_long(s
, addr
, val
);
2161 vtd_set_quad(s
, addr
, val
);
2162 vtd_handle_ccmd_write(s
);
2166 case DMAR_CCMD_REG_HI
:
2168 vtd_set_long(s
, addr
, val
);
2169 vtd_handle_ccmd_write(s
);
2172 /* IOTLB Invalidation Register, 64-bit */
2173 case DMAR_IOTLB_REG
:
2175 vtd_set_long(s
, addr
, val
);
2177 vtd_set_quad(s
, addr
, val
);
2178 vtd_handle_iotlb_write(s
);
2182 case DMAR_IOTLB_REG_HI
:
2184 vtd_set_long(s
, addr
, val
);
2185 vtd_handle_iotlb_write(s
);
2188 /* Invalidate Address Register, 64-bit */
2191 vtd_set_long(s
, addr
, val
);
2193 vtd_set_quad(s
, addr
, val
);
2197 case DMAR_IVA_REG_HI
:
2199 vtd_set_long(s
, addr
, val
);
2202 /* Fault Status Register, 32-bit */
2205 vtd_set_long(s
, addr
, val
);
2206 vtd_handle_fsts_write(s
);
2209 /* Fault Event Control Register, 32-bit */
2210 case DMAR_FECTL_REG
:
2212 vtd_set_long(s
, addr
, val
);
2213 vtd_handle_fectl_write(s
);
2216 /* Fault Event Data Register, 32-bit */
2217 case DMAR_FEDATA_REG
:
2219 vtd_set_long(s
, addr
, val
);
2222 /* Fault Event Address Register, 32-bit */
2223 case DMAR_FEADDR_REG
:
2225 vtd_set_long(s
, addr
, val
);
2228 * While the register is 32-bit only, some guests (Xen...) write to
2231 vtd_set_quad(s
, addr
, val
);
2235 /* Fault Event Upper Address Register, 32-bit */
2236 case DMAR_FEUADDR_REG
:
2238 vtd_set_long(s
, addr
, val
);
2241 /* Protected Memory Enable Register, 32-bit */
2244 vtd_set_long(s
, addr
, val
);
2247 /* Root Table Address Register, 64-bit */
2248 case DMAR_RTADDR_REG
:
2250 vtd_set_long(s
, addr
, val
);
2252 vtd_set_quad(s
, addr
, val
);
2256 case DMAR_RTADDR_REG_HI
:
2258 vtd_set_long(s
, addr
, val
);
2261 /* Invalidation Queue Tail Register, 64-bit */
2264 vtd_set_long(s
, addr
, val
);
2266 vtd_set_quad(s
, addr
, val
);
2268 vtd_handle_iqt_write(s
);
2271 case DMAR_IQT_REG_HI
:
2273 vtd_set_long(s
, addr
, val
);
2274 /* 19:63 of IQT_REG is RsvdZ, do nothing here */
2277 /* Invalidation Queue Address Register, 64-bit */
2280 vtd_set_long(s
, addr
, val
);
2282 vtd_set_quad(s
, addr
, val
);
2286 case DMAR_IQA_REG_HI
:
2288 vtd_set_long(s
, addr
, val
);
2291 /* Invalidation Completion Status Register, 32-bit */
2294 vtd_set_long(s
, addr
, val
);
2295 vtd_handle_ics_write(s
);
2298 /* Invalidation Event Control Register, 32-bit */
2299 case DMAR_IECTL_REG
:
2301 vtd_set_long(s
, addr
, val
);
2302 vtd_handle_iectl_write(s
);
2305 /* Invalidation Event Data Register, 32-bit */
2306 case DMAR_IEDATA_REG
:
2308 vtd_set_long(s
, addr
, val
);
2311 /* Invalidation Event Address Register, 32-bit */
2312 case DMAR_IEADDR_REG
:
2314 vtd_set_long(s
, addr
, val
);
2317 /* Invalidation Event Upper Address Register, 32-bit */
2318 case DMAR_IEUADDR_REG
:
2320 vtd_set_long(s
, addr
, val
);
2323 /* Fault Recording Registers, 128-bit */
2324 case DMAR_FRCD_REG_0_0
:
2326 vtd_set_long(s
, addr
, val
);
2328 vtd_set_quad(s
, addr
, val
);
2332 case DMAR_FRCD_REG_0_1
:
2334 vtd_set_long(s
, addr
, val
);
2337 case DMAR_FRCD_REG_0_2
:
2339 vtd_set_long(s
, addr
, val
);
2341 vtd_set_quad(s
, addr
, val
);
2342 /* May clear bit 127 (Fault), update PPF */
2343 vtd_update_fsts_ppf(s
);
2347 case DMAR_FRCD_REG_0_3
:
2349 vtd_set_long(s
, addr
, val
);
2350 /* May clear bit 127 (Fault), update PPF */
2351 vtd_update_fsts_ppf(s
);
2356 vtd_set_long(s
, addr
, val
);
2358 vtd_set_quad(s
, addr
, val
);
2362 case DMAR_IRTA_REG_HI
:
2364 vtd_set_long(s
, addr
, val
);
2369 vtd_set_long(s
, addr
, val
);
2371 vtd_set_quad(s
, addr
, val
);
2376 static IOMMUTLBEntry
vtd_iommu_translate(IOMMUMemoryRegion
*iommu
, hwaddr addr
,
2377 IOMMUAccessFlags flag
)
2379 VTDAddressSpace
*vtd_as
= container_of(iommu
, VTDAddressSpace
, iommu
);
2380 IntelIOMMUState
*s
= vtd_as
->iommu_state
;
2381 IOMMUTLBEntry iotlb
= {
2382 /* We'll fill in the rest later. */
2383 .target_as
= &address_space_memory
,
2387 if (likely(s
->dmar_enabled
)) {
2388 success
= vtd_do_iommu_translate(vtd_as
, vtd_as
->bus
, vtd_as
->devfn
,
2389 addr
, flag
& IOMMU_WO
, &iotlb
);
2391 /* DMAR disabled, passthrough, use 4k-page*/
2392 iotlb
.iova
= addr
& VTD_PAGE_MASK_4K
;
2393 iotlb
.translated_addr
= addr
& VTD_PAGE_MASK_4K
;
2394 iotlb
.addr_mask
= ~VTD_PAGE_MASK_4K
;
2395 iotlb
.perm
= IOMMU_RW
;
2399 if (likely(success
)) {
2400 trace_vtd_dmar_translate(pci_bus_num(vtd_as
->bus
),
2401 VTD_PCI_SLOT(vtd_as
->devfn
),
2402 VTD_PCI_FUNC(vtd_as
->devfn
),
2403 iotlb
.iova
, iotlb
.translated_addr
,
2406 trace_vtd_err_dmar_translate(pci_bus_num(vtd_as
->bus
),
2407 VTD_PCI_SLOT(vtd_as
->devfn
),
2408 VTD_PCI_FUNC(vtd_as
->devfn
),
2415 static void vtd_iommu_notify_flag_changed(IOMMUMemoryRegion
*iommu
,
2416 IOMMUNotifierFlag old
,
2417 IOMMUNotifierFlag
new)
2419 VTDAddressSpace
*vtd_as
= container_of(iommu
, VTDAddressSpace
, iommu
);
2420 IntelIOMMUState
*s
= vtd_as
->iommu_state
;
2422 if (!s
->caching_mode
&& new & IOMMU_NOTIFIER_MAP
) {
2423 error_report("We need to set caching-mode=1 for intel-iommu to enable "
2424 "device assignment with IOMMU protection.");
2428 /* Update per-address-space notifier flags */
2429 vtd_as
->notifier_flags
= new;
2431 if (old
== IOMMU_NOTIFIER_NONE
) {
2432 QLIST_INSERT_HEAD(&s
->vtd_as_with_notifiers
, vtd_as
, next
);
2433 } else if (new == IOMMU_NOTIFIER_NONE
) {
2434 QLIST_REMOVE(vtd_as
, next
);
2438 static int vtd_post_load(void *opaque
, int version_id
)
2440 IntelIOMMUState
*iommu
= opaque
;
2443 * Memory regions are dynamically turned on/off depending on
2444 * context entry configurations from the guest. After migration,
2445 * we need to make sure the memory regions are still correct.
2447 vtd_switch_address_space_all(iommu
);
2452 static const VMStateDescription vtd_vmstate
= {
2453 .name
= "iommu-intel",
2455 .minimum_version_id
= 1,
2456 .priority
= MIG_PRI_IOMMU
,
2457 .post_load
= vtd_post_load
,
2458 .fields
= (VMStateField
[]) {
2459 VMSTATE_UINT64(root
, IntelIOMMUState
),
2460 VMSTATE_UINT64(intr_root
, IntelIOMMUState
),
2461 VMSTATE_UINT64(iq
, IntelIOMMUState
),
2462 VMSTATE_UINT32(intr_size
, IntelIOMMUState
),
2463 VMSTATE_UINT16(iq_head
, IntelIOMMUState
),
2464 VMSTATE_UINT16(iq_tail
, IntelIOMMUState
),
2465 VMSTATE_UINT16(iq_size
, IntelIOMMUState
),
2466 VMSTATE_UINT16(next_frcd_reg
, IntelIOMMUState
),
2467 VMSTATE_UINT8_ARRAY(csr
, IntelIOMMUState
, DMAR_REG_SIZE
),
2468 VMSTATE_UINT8(iq_last_desc_type
, IntelIOMMUState
),
2469 VMSTATE_BOOL(root_extended
, IntelIOMMUState
),
2470 VMSTATE_BOOL(dmar_enabled
, IntelIOMMUState
),
2471 VMSTATE_BOOL(qi_enabled
, IntelIOMMUState
),
2472 VMSTATE_BOOL(intr_enabled
, IntelIOMMUState
),
2473 VMSTATE_BOOL(intr_eime
, IntelIOMMUState
),
2474 VMSTATE_END_OF_LIST()
2478 static const MemoryRegionOps vtd_mem_ops
= {
2479 .read
= vtd_mem_read
,
2480 .write
= vtd_mem_write
,
2481 .endianness
= DEVICE_LITTLE_ENDIAN
,
2483 .min_access_size
= 4,
2484 .max_access_size
= 8,
2487 .min_access_size
= 4,
2488 .max_access_size
= 8,
2492 static Property vtd_properties
[] = {
2493 DEFINE_PROP_UINT32("version", IntelIOMMUState
, version
, 0),
2494 DEFINE_PROP_ON_OFF_AUTO("eim", IntelIOMMUState
, intr_eim
,
2496 DEFINE_PROP_BOOL("x-buggy-eim", IntelIOMMUState
, buggy_eim
, false),
2497 DEFINE_PROP_UINT8("x-aw-bits", IntelIOMMUState
, aw_bits
,
2498 VTD_HOST_ADDRESS_WIDTH
),
2499 DEFINE_PROP_BOOL("caching-mode", IntelIOMMUState
, caching_mode
, FALSE
),
2500 DEFINE_PROP_END_OF_LIST(),
2503 /* Read IRTE entry with specific index */
2504 static int vtd_irte_get(IntelIOMMUState
*iommu
, uint16_t index
,
2505 VTD_IR_TableEntry
*entry
, uint16_t sid
)
2507 static const uint16_t vtd_svt_mask
[VTD_SQ_MAX
] = \
2508 {0xffff, 0xfffb, 0xfff9, 0xfff8};
2509 dma_addr_t addr
= 0x00;
2510 uint16_t mask
, source_id
;
2511 uint8_t bus
, bus_max
, bus_min
;
2513 addr
= iommu
->intr_root
+ index
* sizeof(*entry
);
2514 if (dma_memory_read(&address_space_memory
, addr
, entry
,
2516 trace_vtd_err("Memory read failed for IRTE.");
2517 return -VTD_FR_IR_ROOT_INVAL
;
2520 trace_vtd_ir_irte_get(index
, le64_to_cpu(entry
->data
[1]),
2521 le64_to_cpu(entry
->data
[0]));
2523 if (!entry
->irte
.present
) {
2524 trace_vtd_err_irte(index
, le64_to_cpu(entry
->data
[1]),
2525 le64_to_cpu(entry
->data
[0]));
2526 return -VTD_FR_IR_ENTRY_P
;
2529 if (entry
->irte
.__reserved_0
|| entry
->irte
.__reserved_1
||
2530 entry
->irte
.__reserved_2
) {
2531 trace_vtd_err_irte(index
, le64_to_cpu(entry
->data
[1]),
2532 le64_to_cpu(entry
->data
[0]));
2533 return -VTD_FR_IR_IRTE_RSVD
;
2536 if (sid
!= X86_IOMMU_SID_INVALID
) {
2537 /* Validate IRTE SID */
2538 source_id
= le32_to_cpu(entry
->irte
.source_id
);
2539 switch (entry
->irte
.sid_vtype
) {
2544 mask
= vtd_svt_mask
[entry
->irte
.sid_q
];
2545 if ((source_id
& mask
) != (sid
& mask
)) {
2546 trace_vtd_err_irte_sid(index
, sid
, source_id
);
2547 return -VTD_FR_IR_SID_ERR
;
2552 bus_max
= source_id
>> 8;
2553 bus_min
= source_id
& 0xff;
2555 if (bus
> bus_max
|| bus
< bus_min
) {
2556 trace_vtd_err_irte_sid_bus(index
, bus
, bus_min
, bus_max
);
2557 return -VTD_FR_IR_SID_ERR
;
2562 trace_vtd_err_irte_svt(index
, entry
->irte
.sid_vtype
);
2563 /* Take this as verification failure. */
2564 return -VTD_FR_IR_SID_ERR
;
2572 /* Fetch IRQ information of specific IR index */
2573 static int vtd_remap_irq_get(IntelIOMMUState
*iommu
, uint16_t index
,
2574 VTDIrq
*irq
, uint16_t sid
)
2576 VTD_IR_TableEntry irte
= {};
2579 ret
= vtd_irte_get(iommu
, index
, &irte
, sid
);
2584 irq
->trigger_mode
= irte
.irte
.trigger_mode
;
2585 irq
->vector
= irte
.irte
.vector
;
2586 irq
->delivery_mode
= irte
.irte
.delivery_mode
;
2587 irq
->dest
= le32_to_cpu(irte
.irte
.dest_id
);
2588 if (!iommu
->intr_eime
) {
2589 #define VTD_IR_APIC_DEST_MASK (0xff00ULL)
2590 #define VTD_IR_APIC_DEST_SHIFT (8)
2591 irq
->dest
= (irq
->dest
& VTD_IR_APIC_DEST_MASK
) >>
2592 VTD_IR_APIC_DEST_SHIFT
;
2594 irq
->dest_mode
= irte
.irte
.dest_mode
;
2595 irq
->redir_hint
= irte
.irte
.redir_hint
;
2597 trace_vtd_ir_remap(index
, irq
->trigger_mode
, irq
->vector
,
2598 irq
->delivery_mode
, irq
->dest
, irq
->dest_mode
);
2603 /* Generate one MSI message from VTDIrq info */
2604 static void vtd_generate_msi_message(VTDIrq
*irq
, MSIMessage
*msg_out
)
2606 VTD_MSIMessage msg
= {};
2608 /* Generate address bits */
2609 msg
.dest_mode
= irq
->dest_mode
;
2610 msg
.redir_hint
= irq
->redir_hint
;
2611 msg
.dest
= irq
->dest
;
2612 msg
.__addr_hi
= irq
->dest
& 0xffffff00;
2613 msg
.__addr_head
= cpu_to_le32(0xfee);
2614 /* Keep this from original MSI address bits */
2615 msg
.__not_used
= irq
->msi_addr_last_bits
;
2617 /* Generate data bits */
2618 msg
.vector
= irq
->vector
;
2619 msg
.delivery_mode
= irq
->delivery_mode
;
2621 msg
.trigger_mode
= irq
->trigger_mode
;
2623 msg_out
->address
= msg
.msi_addr
;
2624 msg_out
->data
= msg
.msi_data
;
2627 /* Interrupt remapping for MSI/MSI-X entry */
2628 static int vtd_interrupt_remap_msi(IntelIOMMUState
*iommu
,
2630 MSIMessage
*translated
,
2634 VTD_IR_MSIAddress addr
;
2638 assert(origin
&& translated
);
2640 trace_vtd_ir_remap_msi_req(origin
->address
, origin
->data
);
2642 if (!iommu
|| !iommu
->intr_enabled
) {
2643 memcpy(translated
, origin
, sizeof(*origin
));
2647 if (origin
->address
& VTD_MSI_ADDR_HI_MASK
) {
2648 trace_vtd_err("MSI address high 32 bits non-zero when "
2649 "Interrupt Remapping enabled.");
2650 return -VTD_FR_IR_REQ_RSVD
;
2653 addr
.data
= origin
->address
& VTD_MSI_ADDR_LO_MASK
;
2654 if (addr
.addr
.__head
!= 0xfee) {
2655 trace_vtd_err("MSI addr low 32 bit invalid.");
2656 return -VTD_FR_IR_REQ_RSVD
;
2659 /* This is compatible mode. */
2660 if (addr
.addr
.int_mode
!= VTD_IR_INT_FORMAT_REMAP
) {
2661 memcpy(translated
, origin
, sizeof(*origin
));
2665 index
= addr
.addr
.index_h
<< 15 | le16_to_cpu(addr
.addr
.index_l
);
2667 #define VTD_IR_MSI_DATA_SUBHANDLE (0x0000ffff)
2668 #define VTD_IR_MSI_DATA_RESERVED (0xffff0000)
2670 if (addr
.addr
.sub_valid
) {
2671 /* See VT-d spec 5.1.2.2 and 5.1.3 on subhandle */
2672 index
+= origin
->data
& VTD_IR_MSI_DATA_SUBHANDLE
;
2675 ret
= vtd_remap_irq_get(iommu
, index
, &irq
, sid
);
2680 if (addr
.addr
.sub_valid
) {
2681 trace_vtd_ir_remap_type("MSI");
2682 if (origin
->data
& VTD_IR_MSI_DATA_RESERVED
) {
2683 trace_vtd_err_ir_msi_invalid(sid
, origin
->address
, origin
->data
);
2684 return -VTD_FR_IR_REQ_RSVD
;
2687 uint8_t vector
= origin
->data
& 0xff;
2688 uint8_t trigger_mode
= (origin
->data
>> MSI_DATA_TRIGGER_SHIFT
) & 0x1;
2690 trace_vtd_ir_remap_type("IOAPIC");
2691 /* IOAPIC entry vector should be aligned with IRTE vector
2692 * (see vt-d spec 5.1.5.1). */
2693 if (vector
!= irq
.vector
) {
2694 trace_vtd_warn_ir_vector(sid
, index
, vector
, irq
.vector
);
2697 /* The Trigger Mode field must match the Trigger Mode in the IRTE.
2698 * (see vt-d spec 5.1.5.1). */
2699 if (trigger_mode
!= irq
.trigger_mode
) {
2700 trace_vtd_warn_ir_trigger(sid
, index
, trigger_mode
,
2706 * We'd better keep the last two bits, assuming that guest OS
2707 * might modify it. Keep it does not hurt after all.
2709 irq
.msi_addr_last_bits
= addr
.addr
.__not_care
;
2711 /* Translate VTDIrq to MSI message */
2712 vtd_generate_msi_message(&irq
, translated
);
2715 trace_vtd_ir_remap_msi(origin
->address
, origin
->data
,
2716 translated
->address
, translated
->data
);
2720 static int vtd_int_remap(X86IOMMUState
*iommu
, MSIMessage
*src
,
2721 MSIMessage
*dst
, uint16_t sid
)
2723 return vtd_interrupt_remap_msi(INTEL_IOMMU_DEVICE(iommu
),
2727 static MemTxResult
vtd_mem_ir_read(void *opaque
, hwaddr addr
,
2728 uint64_t *data
, unsigned size
,
2734 static MemTxResult
vtd_mem_ir_write(void *opaque
, hwaddr addr
,
2735 uint64_t value
, unsigned size
,
2739 MSIMessage from
= {}, to
= {};
2740 uint16_t sid
= X86_IOMMU_SID_INVALID
;
2742 from
.address
= (uint64_t) addr
+ VTD_INTERRUPT_ADDR_FIRST
;
2743 from
.data
= (uint32_t) value
;
2745 if (!attrs
.unspecified
) {
2746 /* We have explicit Source ID */
2747 sid
= attrs
.requester_id
;
2750 ret
= vtd_interrupt_remap_msi(opaque
, &from
, &to
, sid
);
2752 /* TODO: report error */
2753 /* Drop this interrupt */
2757 apic_get_class()->send_msi(&to
);
2762 static const MemoryRegionOps vtd_mem_ir_ops
= {
2763 .read_with_attrs
= vtd_mem_ir_read
,
2764 .write_with_attrs
= vtd_mem_ir_write
,
2765 .endianness
= DEVICE_LITTLE_ENDIAN
,
2767 .min_access_size
= 4,
2768 .max_access_size
= 4,
2771 .min_access_size
= 4,
2772 .max_access_size
= 4,
2776 VTDAddressSpace
*vtd_find_add_as(IntelIOMMUState
*s
, PCIBus
*bus
, int devfn
)
2778 uintptr_t key
= (uintptr_t)bus
;
2779 VTDBus
*vtd_bus
= g_hash_table_lookup(s
->vtd_as_by_busptr
, &key
);
2780 VTDAddressSpace
*vtd_dev_as
;
2784 uintptr_t *new_key
= g_malloc(sizeof(*new_key
));
2785 *new_key
= (uintptr_t)bus
;
2786 /* No corresponding free() */
2787 vtd_bus
= g_malloc0(sizeof(VTDBus
) + sizeof(VTDAddressSpace
*) * \
2790 g_hash_table_insert(s
->vtd_as_by_busptr
, new_key
, vtd_bus
);
2793 vtd_dev_as
= vtd_bus
->dev_as
[devfn
];
2796 snprintf(name
, sizeof(name
), "intel_iommu_devfn_%d", devfn
);
2797 vtd_bus
->dev_as
[devfn
] = vtd_dev_as
= g_malloc0(sizeof(VTDAddressSpace
));
2799 vtd_dev_as
->bus
= bus
;
2800 vtd_dev_as
->devfn
= (uint8_t)devfn
;
2801 vtd_dev_as
->iommu_state
= s
;
2802 vtd_dev_as
->context_cache_entry
.context_cache_gen
= 0;
2805 * Memory region relationships looks like (Address range shows
2806 * only lower 32 bits to make it short in length...):
2808 * |-----------------+-------------------+----------|
2809 * | Name | Address range | Priority |
2810 * |-----------------+-------------------+----------+
2811 * | vtd_root | 00000000-ffffffff | 0 |
2812 * | intel_iommu | 00000000-ffffffff | 1 |
2813 * | vtd_sys_alias | 00000000-ffffffff | 1 |
2814 * | intel_iommu_ir | fee00000-feefffff | 64 |
2815 * |-----------------+-------------------+----------|
2817 * We enable/disable DMAR by switching enablement for
2818 * vtd_sys_alias and intel_iommu regions. IR region is always
2821 memory_region_init_iommu(&vtd_dev_as
->iommu
, sizeof(vtd_dev_as
->iommu
),
2822 TYPE_INTEL_IOMMU_MEMORY_REGION
, OBJECT(s
),
2825 memory_region_init_alias(&vtd_dev_as
->sys_alias
, OBJECT(s
),
2826 "vtd_sys_alias", get_system_memory(),
2827 0, memory_region_size(get_system_memory()));
2828 memory_region_init_io(&vtd_dev_as
->iommu_ir
, OBJECT(s
),
2829 &vtd_mem_ir_ops
, s
, "intel_iommu_ir",
2830 VTD_INTERRUPT_ADDR_SIZE
);
2831 memory_region_init(&vtd_dev_as
->root
, OBJECT(s
),
2832 "vtd_root", UINT64_MAX
);
2833 memory_region_add_subregion_overlap(&vtd_dev_as
->root
,
2834 VTD_INTERRUPT_ADDR_FIRST
,
2835 &vtd_dev_as
->iommu_ir
, 64);
2836 address_space_init(&vtd_dev_as
->as
, &vtd_dev_as
->root
, name
);
2837 memory_region_add_subregion_overlap(&vtd_dev_as
->root
, 0,
2838 &vtd_dev_as
->sys_alias
, 1);
2839 memory_region_add_subregion_overlap(&vtd_dev_as
->root
, 0,
2840 MEMORY_REGION(&vtd_dev_as
->iommu
),
2842 vtd_switch_address_space(vtd_dev_as
);
2847 /* Unmap the whole range in the notifier's scope. */
2848 static void vtd_address_space_unmap(VTDAddressSpace
*as
, IOMMUNotifier
*n
)
2850 IOMMUTLBEntry entry
;
2852 hwaddr start
= n
->start
;
2853 hwaddr end
= n
->end
;
2854 IntelIOMMUState
*s
= as
->iommu_state
;
2857 * Note: all the codes in this function has a assumption that IOVA
2858 * bits are no more than VTD_MGAW bits (which is restricted by
2859 * VT-d spec), otherwise we need to consider overflow of 64 bits.
2862 if (end
> VTD_ADDRESS_SIZE(s
->aw_bits
)) {
2864 * Don't need to unmap regions that is bigger than the whole
2865 * VT-d supported address space size
2867 end
= VTD_ADDRESS_SIZE(s
->aw_bits
);
2870 assert(start
<= end
);
2873 if (ctpop64(size
) != 1) {
2875 * This size cannot format a correct mask. Let's enlarge it to
2876 * suite the minimum available mask.
2878 int n
= 64 - clz64(size
);
2879 if (n
> s
->aw_bits
) {
2880 /* should not happen, but in case it happens, limit it */
2886 entry
.target_as
= &address_space_memory
;
2887 /* Adjust iova for the size */
2888 entry
.iova
= n
->start
& ~(size
- 1);
2889 /* This field is meaningless for unmap */
2890 entry
.translated_addr
= 0;
2891 entry
.perm
= IOMMU_NONE
;
2892 entry
.addr_mask
= size
- 1;
2894 trace_vtd_as_unmap_whole(pci_bus_num(as
->bus
),
2895 VTD_PCI_SLOT(as
->devfn
),
2896 VTD_PCI_FUNC(as
->devfn
),
2899 memory_region_notify_one(n
, &entry
);
2902 static void vtd_address_space_unmap_all(IntelIOMMUState
*s
)
2904 VTDAddressSpace
*vtd_as
;
2907 QLIST_FOREACH(vtd_as
, &s
->vtd_as_with_notifiers
, next
) {
2908 IOMMU_NOTIFIER_FOREACH(n
, &vtd_as
->iommu
) {
2909 vtd_address_space_unmap(vtd_as
, n
);
2914 static int vtd_replay_hook(IOMMUTLBEntry
*entry
, void *private)
2916 memory_region_notify_one((IOMMUNotifier
*)private, entry
);
2920 static void vtd_iommu_replay(IOMMUMemoryRegion
*iommu_mr
, IOMMUNotifier
*n
)
2922 VTDAddressSpace
*vtd_as
= container_of(iommu_mr
, VTDAddressSpace
, iommu
);
2923 IntelIOMMUState
*s
= vtd_as
->iommu_state
;
2924 uint8_t bus_n
= pci_bus_num(vtd_as
->bus
);
2928 * The replay can be triggered by either a invalidation or a newly
2929 * created entry. No matter what, we release existing mappings
2930 * (it means flushing caches for UNMAP-only registers).
2932 vtd_address_space_unmap(vtd_as
, n
);
2934 if (vtd_dev_to_context_entry(s
, bus_n
, vtd_as
->devfn
, &ce
) == 0) {
2935 trace_vtd_replay_ce_valid(bus_n
, PCI_SLOT(vtd_as
->devfn
),
2936 PCI_FUNC(vtd_as
->devfn
),
2937 VTD_CONTEXT_ENTRY_DID(ce
.hi
),
2939 if (vtd_as_has_map_notifier(vtd_as
)) {
2940 /* This is required only for MAP typed notifiers */
2941 vtd_page_walk_info info
= {
2942 .hook_fn
= vtd_replay_hook
,
2943 .private = (void *)n
,
2944 .notify_unmap
= false,
2948 vtd_page_walk(&ce
, 0, ~0ULL, &info
);
2951 trace_vtd_replay_ce_invalid(bus_n
, PCI_SLOT(vtd_as
->devfn
),
2952 PCI_FUNC(vtd_as
->devfn
));
2958 /* Do the initialization. It will also be called when reset, so pay
2959 * attention when adding new initialization stuff.
2961 static void vtd_init(IntelIOMMUState
*s
)
2963 X86IOMMUState
*x86_iommu
= X86_IOMMU_DEVICE(s
);
2965 memset(s
->csr
, 0, DMAR_REG_SIZE
);
2966 memset(s
->wmask
, 0, DMAR_REG_SIZE
);
2967 memset(s
->w1cmask
, 0, DMAR_REG_SIZE
);
2968 memset(s
->womask
, 0, DMAR_REG_SIZE
);
2971 s
->root_extended
= false;
2972 s
->dmar_enabled
= false;
2977 s
->qi_enabled
= false;
2978 s
->iq_last_desc_type
= VTD_INV_DESC_NONE
;
2979 s
->next_frcd_reg
= 0;
2980 s
->cap
= VTD_CAP_FRO
| VTD_CAP_NFR
| VTD_CAP_ND
|
2981 VTD_CAP_MAMV
| VTD_CAP_PSI
| VTD_CAP_SLLPS
|
2982 VTD_CAP_SAGAW_39bit
| VTD_CAP_MGAW(s
->aw_bits
);
2983 if (s
->aw_bits
== VTD_HOST_AW_48BIT
) {
2984 s
->cap
|= VTD_CAP_SAGAW_48bit
;
2986 s
->ecap
= VTD_ECAP_QI
| VTD_ECAP_IRO
;
2989 * Rsvd field masks for spte
2991 vtd_paging_entry_rsvd_field
[0] = ~0ULL;
2992 vtd_paging_entry_rsvd_field
[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s
->aw_bits
);
2993 vtd_paging_entry_rsvd_field
[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s
->aw_bits
);
2994 vtd_paging_entry_rsvd_field
[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s
->aw_bits
);
2995 vtd_paging_entry_rsvd_field
[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s
->aw_bits
);
2996 vtd_paging_entry_rsvd_field
[5] = VTD_SPTE_LPAGE_L1_RSVD_MASK(s
->aw_bits
);
2997 vtd_paging_entry_rsvd_field
[6] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s
->aw_bits
);
2998 vtd_paging_entry_rsvd_field
[7] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s
->aw_bits
);
2999 vtd_paging_entry_rsvd_field
[8] = VTD_SPTE_LPAGE_L4_RSVD_MASK(s
->aw_bits
);
3001 if (x86_iommu
->intr_supported
) {
3002 s
->ecap
|= VTD_ECAP_IR
| VTD_ECAP_MHMV
;
3003 if (s
->intr_eim
== ON_OFF_AUTO_ON
) {
3004 s
->ecap
|= VTD_ECAP_EIM
;
3006 assert(s
->intr_eim
!= ON_OFF_AUTO_AUTO
);
3009 if (x86_iommu
->dt_supported
) {
3010 s
->ecap
|= VTD_ECAP_DT
;
3013 if (x86_iommu
->pt_supported
) {
3014 s
->ecap
|= VTD_ECAP_PT
;
3017 if (s
->caching_mode
) {
3018 s
->cap
|= VTD_CAP_CM
;
3022 vtd_reset_context_cache_locked(s
);
3023 vtd_reset_iotlb_locked(s
);
3024 vtd_iommu_unlock(s
);
3026 /* Define registers with default values and bit semantics */
3027 vtd_define_long(s
, DMAR_VER_REG
, 0x10UL
, 0, 0);
3028 vtd_define_quad(s
, DMAR_CAP_REG
, s
->cap
, 0, 0);
3029 vtd_define_quad(s
, DMAR_ECAP_REG
, s
->ecap
, 0, 0);
3030 vtd_define_long(s
, DMAR_GCMD_REG
, 0, 0xff800000UL
, 0);
3031 vtd_define_long_wo(s
, DMAR_GCMD_REG
, 0xff800000UL
);
3032 vtd_define_long(s
, DMAR_GSTS_REG
, 0, 0, 0);
3033 vtd_define_quad(s
, DMAR_RTADDR_REG
, 0, 0xfffffffffffff000ULL
, 0);
3034 vtd_define_quad(s
, DMAR_CCMD_REG
, 0, 0xe0000003ffffffffULL
, 0);
3035 vtd_define_quad_wo(s
, DMAR_CCMD_REG
, 0x3ffff0000ULL
);
3037 /* Advanced Fault Logging not supported */
3038 vtd_define_long(s
, DMAR_FSTS_REG
, 0, 0, 0x11UL
);
3039 vtd_define_long(s
, DMAR_FECTL_REG
, 0x80000000UL
, 0x80000000UL
, 0);
3040 vtd_define_long(s
, DMAR_FEDATA_REG
, 0, 0x0000ffffUL
, 0);
3041 vtd_define_long(s
, DMAR_FEADDR_REG
, 0, 0xfffffffcUL
, 0);
3043 /* Treated as RsvdZ when EIM in ECAP_REG is not supported
3044 * vtd_define_long(s, DMAR_FEUADDR_REG, 0, 0xffffffffUL, 0);
3046 vtd_define_long(s
, DMAR_FEUADDR_REG
, 0, 0, 0);
3048 /* Treated as RO for implementations that PLMR and PHMR fields reported
3049 * as Clear in the CAP_REG.
3050 * vtd_define_long(s, DMAR_PMEN_REG, 0, 0x80000000UL, 0);
3052 vtd_define_long(s
, DMAR_PMEN_REG
, 0, 0, 0);
3054 vtd_define_quad(s
, DMAR_IQH_REG
, 0, 0, 0);
3055 vtd_define_quad(s
, DMAR_IQT_REG
, 0, 0x7fff0ULL
, 0);
3056 vtd_define_quad(s
, DMAR_IQA_REG
, 0, 0xfffffffffffff007ULL
, 0);
3057 vtd_define_long(s
, DMAR_ICS_REG
, 0, 0, 0x1UL
);
3058 vtd_define_long(s
, DMAR_IECTL_REG
, 0x80000000UL
, 0x80000000UL
, 0);
3059 vtd_define_long(s
, DMAR_IEDATA_REG
, 0, 0xffffffffUL
, 0);
3060 vtd_define_long(s
, DMAR_IEADDR_REG
, 0, 0xfffffffcUL
, 0);
3061 /* Treadted as RsvdZ when EIM in ECAP_REG is not supported */
3062 vtd_define_long(s
, DMAR_IEUADDR_REG
, 0, 0, 0);
3064 /* IOTLB registers */
3065 vtd_define_quad(s
, DMAR_IOTLB_REG
, 0, 0Xb003ffff00000000ULL
, 0);
3066 vtd_define_quad(s
, DMAR_IVA_REG
, 0, 0xfffffffffffff07fULL
, 0);
3067 vtd_define_quad_wo(s
, DMAR_IVA_REG
, 0xfffffffffffff07fULL
);
3069 /* Fault Recording Registers, 128-bit */
3070 vtd_define_quad(s
, DMAR_FRCD_REG_0_0
, 0, 0, 0);
3071 vtd_define_quad(s
, DMAR_FRCD_REG_0_2
, 0, 0, 0x8000000000000000ULL
);
3074 * Interrupt remapping registers.
3076 vtd_define_quad(s
, DMAR_IRTA_REG
, 0, 0xfffffffffffff80fULL
, 0);
3079 /* Should not reset address_spaces when reset because devices will still use
3080 * the address space they got at first (won't ask the bus again).
3082 static void vtd_reset(DeviceState
*dev
)
3084 IntelIOMMUState
*s
= INTEL_IOMMU_DEVICE(dev
);
3089 * When device reset, throw away all mappings and external caches
3091 vtd_address_space_unmap_all(s
);
3094 static AddressSpace
*vtd_host_dma_iommu(PCIBus
*bus
, void *opaque
, int devfn
)
3096 IntelIOMMUState
*s
= opaque
;
3097 VTDAddressSpace
*vtd_as
;
3099 assert(0 <= devfn
&& devfn
< PCI_DEVFN_MAX
);
3101 vtd_as
= vtd_find_add_as(s
, bus
, devfn
);
3105 static bool vtd_decide_config(IntelIOMMUState
*s
, Error
**errp
)
3107 X86IOMMUState
*x86_iommu
= X86_IOMMU_DEVICE(s
);
3109 /* Currently Intel IOMMU IR only support "kernel-irqchip={off|split}" */
3110 if (x86_iommu
->intr_supported
&& kvm_irqchip_in_kernel() &&
3111 !kvm_irqchip_is_split()) {
3112 error_setg(errp
, "Intel Interrupt Remapping cannot work with "
3113 "kernel-irqchip=on, please use 'split|off'.");
3116 if (s
->intr_eim
== ON_OFF_AUTO_ON
&& !x86_iommu
->intr_supported
) {
3117 error_setg(errp
, "eim=on cannot be selected without intremap=on");
3121 if (s
->intr_eim
== ON_OFF_AUTO_AUTO
) {
3122 s
->intr_eim
= (kvm_irqchip_in_kernel() || s
->buggy_eim
)
3123 && x86_iommu
->intr_supported
?
3124 ON_OFF_AUTO_ON
: ON_OFF_AUTO_OFF
;
3126 if (s
->intr_eim
== ON_OFF_AUTO_ON
&& !s
->buggy_eim
) {
3127 if (!kvm_irqchip_in_kernel()) {
3128 error_setg(errp
, "eim=on requires accel=kvm,kernel-irqchip=split");
3131 if (!kvm_enable_x2apic()) {
3132 error_setg(errp
, "eim=on requires support on the KVM side"
3133 "(X2APIC_API, first shipped in v4.7)");
3138 /* Currently only address widths supported are 39 and 48 bits */
3139 if ((s
->aw_bits
!= VTD_HOST_AW_39BIT
) &&
3140 (s
->aw_bits
!= VTD_HOST_AW_48BIT
)) {
3141 error_setg(errp
, "Supported values for x-aw-bits are: %d, %d",
3142 VTD_HOST_AW_39BIT
, VTD_HOST_AW_48BIT
);
3149 static void vtd_realize(DeviceState
*dev
, Error
**errp
)
3151 MachineState
*ms
= MACHINE(qdev_get_machine());
3152 PCMachineState
*pcms
= PC_MACHINE(ms
);
3153 PCIBus
*bus
= pcms
->bus
;
3154 IntelIOMMUState
*s
= INTEL_IOMMU_DEVICE(dev
);
3155 X86IOMMUState
*x86_iommu
= X86_IOMMU_DEVICE(dev
);
3157 x86_iommu
->type
= TYPE_INTEL
;
3159 if (!vtd_decide_config(s
, errp
)) {
3163 QLIST_INIT(&s
->vtd_as_with_notifiers
);
3164 qemu_mutex_init(&s
->iommu_lock
);
3165 memset(s
->vtd_as_by_bus_num
, 0, sizeof(s
->vtd_as_by_bus_num
));
3166 memory_region_init_io(&s
->csrmem
, OBJECT(s
), &vtd_mem_ops
, s
,
3167 "intel_iommu", DMAR_REG_SIZE
);
3168 sysbus_init_mmio(SYS_BUS_DEVICE(s
), &s
->csrmem
);
3169 /* No corresponding destroy */
3170 s
->iotlb
= g_hash_table_new_full(vtd_uint64_hash
, vtd_uint64_equal
,
3172 s
->vtd_as_by_busptr
= g_hash_table_new_full(vtd_uint64_hash
, vtd_uint64_equal
,
3175 sysbus_mmio_map(SYS_BUS_DEVICE(s
), 0, Q35_HOST_BRIDGE_IOMMU_ADDR
);
3176 pci_setup_iommu(bus
, vtd_host_dma_iommu
, dev
);
3177 /* Pseudo address space under root PCI bus. */
3178 pcms
->ioapic_as
= vtd_host_dma_iommu(bus
, s
, Q35_PSEUDO_DEVFN_IOAPIC
);
3181 static void vtd_class_init(ObjectClass
*klass
, void *data
)
3183 DeviceClass
*dc
= DEVICE_CLASS(klass
);
3184 X86IOMMUClass
*x86_class
= X86_IOMMU_CLASS(klass
);
3186 dc
->reset
= vtd_reset
;
3187 dc
->vmsd
= &vtd_vmstate
;
3188 dc
->props
= vtd_properties
;
3189 dc
->hotpluggable
= false;
3190 x86_class
->realize
= vtd_realize
;
3191 x86_class
->int_remap
= vtd_int_remap
;
3192 /* Supported by the pc-q35-* machine types */
3193 dc
->user_creatable
= true;
3196 static const TypeInfo vtd_info
= {
3197 .name
= TYPE_INTEL_IOMMU_DEVICE
,
3198 .parent
= TYPE_X86_IOMMU_DEVICE
,
3199 .instance_size
= sizeof(IntelIOMMUState
),
3200 .class_init
= vtd_class_init
,
3203 static void vtd_iommu_memory_region_class_init(ObjectClass
*klass
,
3206 IOMMUMemoryRegionClass
*imrc
= IOMMU_MEMORY_REGION_CLASS(klass
);
3208 imrc
->translate
= vtd_iommu_translate
;
3209 imrc
->notify_flag_changed
= vtd_iommu_notify_flag_changed
;
3210 imrc
->replay
= vtd_iommu_replay
;
3213 static const TypeInfo vtd_iommu_memory_region_info
= {
3214 .parent
= TYPE_IOMMU_MEMORY_REGION
,
3215 .name
= TYPE_INTEL_IOMMU_MEMORY_REGION
,
3216 .class_init
= vtd_iommu_memory_region_class_init
,
3219 static void vtd_register_types(void)
3221 type_register_static(&vtd_info
);
3222 type_register_static(&vtd_iommu_memory_region_info
);
3225 type_init(vtd_register_types
)