2 * Xilinx Zynq MPSoC emulation
4 * Copyright (C) 2015 Xilinx Inc
5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 #include "qemu/osdep.h"
19 #include "qapi/error.h"
20 #include "qemu-common.h"
22 #include "hw/arm/xlnx-zynqmp.h"
23 #include "hw/intc/arm_gic_common.h"
24 #include "exec/address-spaces.h"
25 #include "sysemu/kvm.h"
28 #define GIC_NUM_SPI_INTR 160
30 #define ARM_PHYS_TIMER_PPI 30
31 #define ARM_VIRT_TIMER_PPI 27
33 #define GEM_REVISION 0x40070106
35 #define GIC_BASE_ADDR 0xf9000000
36 #define GIC_DIST_ADDR 0xf9010000
37 #define GIC_CPU_ADDR 0xf9020000
40 #define SATA_ADDR 0xFD0C0000
41 #define SATA_NUM_PORTS 2
43 #define QSPI_ADDR 0xff0f0000
44 #define LQSPI_ADDR 0xc0000000
47 #define DP_ADDR 0xfd4a0000
50 #define DPDMA_ADDR 0xfd4c0000
53 static const uint64_t gem_addr
[XLNX_ZYNQMP_NUM_GEMS
] = {
54 0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
57 static const int gem_intr
[XLNX_ZYNQMP_NUM_GEMS
] = {
61 static const uint64_t uart_addr
[XLNX_ZYNQMP_NUM_UARTS
] = {
62 0xFF000000, 0xFF010000,
65 static const int uart_intr
[XLNX_ZYNQMP_NUM_UARTS
] = {
69 static const uint64_t sdhci_addr
[XLNX_ZYNQMP_NUM_SDHCI
] = {
70 0xFF160000, 0xFF170000,
73 static const int sdhci_intr
[XLNX_ZYNQMP_NUM_SDHCI
] = {
77 static const uint64_t spi_addr
[XLNX_ZYNQMP_NUM_SPIS
] = {
78 0xFF040000, 0xFF050000,
81 static const int spi_intr
[XLNX_ZYNQMP_NUM_SPIS
] = {
85 typedef struct XlnxZynqMPGICRegion
{
88 } XlnxZynqMPGICRegion
;
90 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions
[] = {
91 { .region_index
= 0, .address
= GIC_DIST_ADDR
, },
92 { .region_index
= 1, .address
= GIC_CPU_ADDR
, },
95 static inline int arm_gic_ppi_index(int cpu_nr
, int ppi_index
)
97 return GIC_NUM_SPI_INTR
+ cpu_nr
* GIC_INTERNAL
+ ppi_index
;
100 static void xlnx_zynqmp_create_rpu(XlnxZynqMPState
*s
, const char *boot_cpu
,
105 int num_rpus
= MIN(smp_cpus
- XLNX_ZYNQMP_NUM_APU_CPUS
, XLNX_ZYNQMP_NUM_RPU_CPUS
);
107 for (i
= 0; i
< num_rpus
; i
++) {
110 object_initialize(&s
->rpu_cpu
[i
], sizeof(s
->rpu_cpu
[i
]),
111 "cortex-r5-" TYPE_ARM_CPU
);
112 object_property_add_child(OBJECT(s
), "rpu-cpu[*]",
113 OBJECT(&s
->rpu_cpu
[i
]), &error_abort
);
115 name
= object_get_canonical_path_component(OBJECT(&s
->rpu_cpu
[i
]));
116 if (strcmp(name
, boot_cpu
)) {
117 /* Secondary CPUs start in PSCI powered-down state */
118 object_property_set_bool(OBJECT(&s
->rpu_cpu
[i
]), true,
119 "start-powered-off", &error_abort
);
121 s
->boot_cpu_ptr
= &s
->rpu_cpu
[i
];
125 object_property_set_bool(OBJECT(&s
->rpu_cpu
[i
]), true, "reset-hivecs",
127 object_property_set_bool(OBJECT(&s
->rpu_cpu
[i
]), true, "realized",
130 error_propagate(errp
, err
);
136 static void xlnx_zynqmp_init(Object
*obj
)
138 XlnxZynqMPState
*s
= XLNX_ZYNQMP(obj
);
140 int num_apus
= MIN(smp_cpus
, XLNX_ZYNQMP_NUM_APU_CPUS
);
142 for (i
= 0; i
< num_apus
; i
++) {
143 object_initialize(&s
->apu_cpu
[i
], sizeof(s
->apu_cpu
[i
]),
144 "cortex-a53-" TYPE_ARM_CPU
);
145 object_property_add_child(obj
, "apu-cpu[*]", OBJECT(&s
->apu_cpu
[i
]),
149 object_initialize(&s
->gic
, sizeof(s
->gic
), gic_class_name());
150 qdev_set_parent_bus(DEVICE(&s
->gic
), sysbus_get_default());
152 for (i
= 0; i
< XLNX_ZYNQMP_NUM_GEMS
; i
++) {
153 object_initialize(&s
->gem
[i
], sizeof(s
->gem
[i
]), TYPE_CADENCE_GEM
);
154 qdev_set_parent_bus(DEVICE(&s
->gem
[i
]), sysbus_get_default());
157 for (i
= 0; i
< XLNX_ZYNQMP_NUM_UARTS
; i
++) {
158 object_initialize(&s
->uart
[i
], sizeof(s
->uart
[i
]), TYPE_CADENCE_UART
);
159 qdev_set_parent_bus(DEVICE(&s
->uart
[i
]), sysbus_get_default());
162 object_initialize(&s
->sata
, sizeof(s
->sata
), TYPE_SYSBUS_AHCI
);
163 qdev_set_parent_bus(DEVICE(&s
->sata
), sysbus_get_default());
165 for (i
= 0; i
< XLNX_ZYNQMP_NUM_SDHCI
; i
++) {
166 object_initialize(&s
->sdhci
[i
], sizeof(s
->sdhci
[i
]),
168 qdev_set_parent_bus(DEVICE(&s
->sdhci
[i
]),
169 sysbus_get_default());
172 for (i
= 0; i
< XLNX_ZYNQMP_NUM_SPIS
; i
++) {
173 object_initialize(&s
->spi
[i
], sizeof(s
->spi
[i
]),
175 qdev_set_parent_bus(DEVICE(&s
->spi
[i
]), sysbus_get_default());
178 object_initialize(&s
->qspi
, sizeof(s
->qspi
), TYPE_XLNX_ZYNQMP_QSPIPS
);
179 qdev_set_parent_bus(DEVICE(&s
->qspi
), sysbus_get_default());
181 object_initialize(&s
->dp
, sizeof(s
->dp
), TYPE_XLNX_DP
);
182 qdev_set_parent_bus(DEVICE(&s
->dp
), sysbus_get_default());
184 object_initialize(&s
->dpdma
, sizeof(s
->dpdma
), TYPE_XLNX_DPDMA
);
185 qdev_set_parent_bus(DEVICE(&s
->dpdma
), sysbus_get_default());
188 static void xlnx_zynqmp_realize(DeviceState
*dev
, Error
**errp
)
190 XlnxZynqMPState
*s
= XLNX_ZYNQMP(dev
);
191 MemoryRegion
*system_memory
= get_system_memory();
194 int num_apus
= MIN(smp_cpus
, XLNX_ZYNQMP_NUM_APU_CPUS
);
195 const char *boot_cpu
= s
->boot_cpu
? s
->boot_cpu
: "apu-cpu[0]";
196 ram_addr_t ddr_low_size
, ddr_high_size
;
197 qemu_irq gic_spi
[GIC_NUM_SPI_INTR
];
200 ram_size
= memory_region_size(s
->ddr_ram
);
202 /* Create the DDR Memory Regions. User friendly checks should happen at
205 if (ram_size
> XLNX_ZYNQMP_MAX_LOW_RAM_SIZE
) {
206 /* The RAM size is above the maximum available for the low DDR.
207 * Create the high DDR memory region as well.
209 assert(ram_size
<= XLNX_ZYNQMP_MAX_RAM_SIZE
);
210 ddr_low_size
= XLNX_ZYNQMP_MAX_LOW_RAM_SIZE
;
211 ddr_high_size
= ram_size
- XLNX_ZYNQMP_MAX_LOW_RAM_SIZE
;
213 memory_region_init_alias(&s
->ddr_ram_high
, NULL
,
214 "ddr-ram-high", s
->ddr_ram
,
215 ddr_low_size
, ddr_high_size
);
216 memory_region_add_subregion(get_system_memory(),
217 XLNX_ZYNQMP_HIGH_RAM_START
,
220 /* RAM must be non-zero */
222 ddr_low_size
= ram_size
;
225 memory_region_init_alias(&s
->ddr_ram_low
, NULL
,
226 "ddr-ram-low", s
->ddr_ram
,
228 memory_region_add_subregion(get_system_memory(), 0, &s
->ddr_ram_low
);
230 /* Create the four OCM banks */
231 for (i
= 0; i
< XLNX_ZYNQMP_NUM_OCM_BANKS
; i
++) {
232 char *ocm_name
= g_strdup_printf("zynqmp.ocm_ram_bank_%d", i
);
234 memory_region_init_ram(&s
->ocm_ram
[i
], NULL
, ocm_name
,
235 XLNX_ZYNQMP_OCM_RAM_SIZE
, &error_fatal
);
236 memory_region_add_subregion(get_system_memory(),
237 XLNX_ZYNQMP_OCM_RAM_0_ADDRESS
+
238 i
* XLNX_ZYNQMP_OCM_RAM_SIZE
,
244 qdev_prop_set_uint32(DEVICE(&s
->gic
), "num-irq", GIC_NUM_SPI_INTR
+ 32);
245 qdev_prop_set_uint32(DEVICE(&s
->gic
), "revision", 2);
246 qdev_prop_set_uint32(DEVICE(&s
->gic
), "num-cpu", num_apus
);
248 /* Realize APUs before realizing the GIC. KVM requires this. */
249 for (i
= 0; i
< num_apus
; i
++) {
252 object_property_set_int(OBJECT(&s
->apu_cpu
[i
]), QEMU_PSCI_CONDUIT_SMC
,
253 "psci-conduit", &error_abort
);
255 name
= object_get_canonical_path_component(OBJECT(&s
->apu_cpu
[i
]));
256 if (strcmp(name
, boot_cpu
)) {
257 /* Secondary CPUs start in PSCI powered-down state */
258 object_property_set_bool(OBJECT(&s
->apu_cpu
[i
]), true,
259 "start-powered-off", &error_abort
);
261 s
->boot_cpu_ptr
= &s
->apu_cpu
[i
];
265 object_property_set_bool(OBJECT(&s
->apu_cpu
[i
]),
266 s
->secure
, "has_el3", NULL
);
267 object_property_set_bool(OBJECT(&s
->apu_cpu
[i
]),
268 s
->virt
, "has_el2", NULL
);
269 object_property_set_int(OBJECT(&s
->apu_cpu
[i
]), GIC_BASE_ADDR
,
270 "reset-cbar", &error_abort
);
271 object_property_set_bool(OBJECT(&s
->apu_cpu
[i
]), true, "realized",
274 error_propagate(errp
, err
);
279 object_property_set_bool(OBJECT(&s
->gic
), true, "realized", &err
);
281 error_propagate(errp
, err
);
285 assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions
) == XLNX_ZYNQMP_GIC_REGIONS
);
286 for (i
= 0; i
< XLNX_ZYNQMP_GIC_REGIONS
; i
++) {
287 SysBusDevice
*gic
= SYS_BUS_DEVICE(&s
->gic
);
288 const XlnxZynqMPGICRegion
*r
= &xlnx_zynqmp_gic_regions
[i
];
289 MemoryRegion
*mr
= sysbus_mmio_get_region(gic
, r
->region_index
);
290 uint32_t addr
= r
->address
;
293 sysbus_mmio_map(gic
, r
->region_index
, addr
);
295 for (j
= 0; j
< XLNX_ZYNQMP_GIC_ALIASES
; j
++) {
296 MemoryRegion
*alias
= &s
->gic_mr
[i
][j
];
298 addr
+= XLNX_ZYNQMP_GIC_REGION_SIZE
;
299 memory_region_init_alias(alias
, OBJECT(s
), "zynqmp-gic-alias", mr
,
300 0, XLNX_ZYNQMP_GIC_REGION_SIZE
);
301 memory_region_add_subregion(system_memory
, addr
, alias
);
305 for (i
= 0; i
< num_apus
; i
++) {
308 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gic
), i
,
309 qdev_get_gpio_in(DEVICE(&s
->apu_cpu
[i
]),
311 irq
= qdev_get_gpio_in(DEVICE(&s
->gic
),
312 arm_gic_ppi_index(i
, ARM_PHYS_TIMER_PPI
));
313 qdev_connect_gpio_out(DEVICE(&s
->apu_cpu
[i
]), 0, irq
);
314 irq
= qdev_get_gpio_in(DEVICE(&s
->gic
),
315 arm_gic_ppi_index(i
, ARM_VIRT_TIMER_PPI
));
316 qdev_connect_gpio_out(DEVICE(&s
->apu_cpu
[i
]), 1, irq
);
320 info_report("The 'has_rpu' property is no longer required, to use the "
321 "RPUs just use -smp 6.");
324 xlnx_zynqmp_create_rpu(s
, boot_cpu
, &err
);
326 error_propagate(errp
, err
);
330 if (!s
->boot_cpu_ptr
) {
331 error_setg(errp
, "ZynqMP Boot cpu %s not found", boot_cpu
);
335 for (i
= 0; i
< GIC_NUM_SPI_INTR
; i
++) {
336 gic_spi
[i
] = qdev_get_gpio_in(DEVICE(&s
->gic
), i
);
339 for (i
= 0; i
< XLNX_ZYNQMP_NUM_GEMS
; i
++) {
340 NICInfo
*nd
= &nd_table
[i
];
343 qemu_check_nic_model(nd
, TYPE_CADENCE_GEM
);
344 qdev_set_nic_properties(DEVICE(&s
->gem
[i
]), nd
);
346 object_property_set_int(OBJECT(&s
->gem
[i
]), GEM_REVISION
, "revision",
348 object_property_set_int(OBJECT(&s
->gem
[i
]), 2, "num-priority-queues",
350 object_property_set_bool(OBJECT(&s
->gem
[i
]), true, "realized", &err
);
352 error_propagate(errp
, err
);
355 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->gem
[i
]), 0, gem_addr
[i
]);
356 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gem
[i
]), 0,
357 gic_spi
[gem_intr
[i
]]);
360 for (i
= 0; i
< XLNX_ZYNQMP_NUM_UARTS
; i
++) {
361 qdev_prop_set_chr(DEVICE(&s
->uart
[i
]), "chardev", serial_hds
[i
]);
362 object_property_set_bool(OBJECT(&s
->uart
[i
]), true, "realized", &err
);
364 error_propagate(errp
, err
);
367 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->uart
[i
]), 0, uart_addr
[i
]);
368 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->uart
[i
]), 0,
369 gic_spi
[uart_intr
[i
]]);
372 object_property_set_int(OBJECT(&s
->sata
), SATA_NUM_PORTS
, "num-ports",
374 object_property_set_bool(OBJECT(&s
->sata
), true, "realized", &err
);
376 error_propagate(errp
, err
);
380 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->sata
), 0, SATA_ADDR
);
381 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->sata
), 0, gic_spi
[SATA_INTR
]);
383 for (i
= 0; i
< XLNX_ZYNQMP_NUM_SDHCI
; i
++) {
386 object_property_set_bool(OBJECT(&s
->sdhci
[i
]), true,
389 error_propagate(errp
, err
);
392 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->sdhci
[i
]), 0,
394 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->sdhci
[i
]), 0,
395 gic_spi
[sdhci_intr
[i
]]);
396 /* Alias controller SD bus to the SoC itself */
397 bus_name
= g_strdup_printf("sd-bus%d", i
);
398 object_property_add_alias(OBJECT(s
), bus_name
,
399 OBJECT(&s
->sdhci
[i
]), "sd-bus",
404 for (i
= 0; i
< XLNX_ZYNQMP_NUM_SPIS
; i
++) {
407 object_property_set_bool(OBJECT(&s
->spi
[i
]), true, "realized", &err
);
409 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->spi
[i
]), 0, spi_addr
[i
]);
410 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->spi
[i
]), 0,
411 gic_spi
[spi_intr
[i
]]);
413 /* Alias controller SPI bus to the SoC itself */
414 bus_name
= g_strdup_printf("spi%d", i
);
415 object_property_add_alias(OBJECT(s
), bus_name
,
416 OBJECT(&s
->spi
[i
]), "spi0",
421 object_property_set_bool(OBJECT(&s
->qspi
), true, "realized", &err
);
422 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->qspi
), 0, QSPI_ADDR
);
423 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->qspi
), 1, LQSPI_ADDR
);
424 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->qspi
), 0, gic_spi
[QSPI_IRQ
]);
426 for (i
= 0; i
< XLNX_ZYNQMP_NUM_QSPI_BUS
; i
++) {
430 /* Alias controller SPI bus to the SoC itself */
431 bus_name
= g_strdup_printf("qspi%d", i
);
432 target_bus
= g_strdup_printf("spi%d", i
);
433 object_property_add_alias(OBJECT(s
), bus_name
,
434 OBJECT(&s
->qspi
), target_bus
,
440 object_property_set_bool(OBJECT(&s
->dp
), true, "realized", &err
);
442 error_propagate(errp
, err
);
445 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->dp
), 0, DP_ADDR
);
446 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->dp
), 0, gic_spi
[DP_IRQ
]);
448 object_property_set_bool(OBJECT(&s
->dpdma
), true, "realized", &err
);
450 error_propagate(errp
, err
);
453 object_property_set_link(OBJECT(&s
->dp
), OBJECT(&s
->dpdma
), "dpdma",
455 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->dpdma
), 0, DPDMA_ADDR
);
456 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->dpdma
), 0, gic_spi
[DPDMA_IRQ
]);
459 static Property xlnx_zynqmp_props
[] = {
460 DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState
, boot_cpu
),
461 DEFINE_PROP_BOOL("secure", XlnxZynqMPState
, secure
, false),
462 DEFINE_PROP_BOOL("virtualization", XlnxZynqMPState
, virt
, false),
463 DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState
, has_rpu
, false),
464 DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState
, ddr_ram
, TYPE_MEMORY_REGION
,
466 DEFINE_PROP_END_OF_LIST()
469 static void xlnx_zynqmp_class_init(ObjectClass
*oc
, void *data
)
471 DeviceClass
*dc
= DEVICE_CLASS(oc
);
473 dc
->props
= xlnx_zynqmp_props
;
474 dc
->realize
= xlnx_zynqmp_realize
;
475 /* Reason: Uses serial_hds in realize function, thus can't be used twice */
476 dc
->user_creatable
= false;
479 static const TypeInfo xlnx_zynqmp_type_info
= {
480 .name
= TYPE_XLNX_ZYNQMP
,
481 .parent
= TYPE_DEVICE
,
482 .instance_size
= sizeof(XlnxZynqMPState
),
483 .instance_init
= xlnx_zynqmp_init
,
484 .class_init
= xlnx_zynqmp_class_init
,
487 static void xlnx_zynqmp_register_types(void)
489 type_register_static(&xlnx_zynqmp_type_info
);
492 type_init(xlnx_zynqmp_register_types
)