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Merge tag 'v9.0.0-rc3'
[qemu/ar7.git] / hw / arm / xlnx-zynqmp.c
blob587c17146087c0a6a5617cc86b02a0ffdb8b5136
1 /*
2 * Xilinx Zynq MPSoC emulation
3 *
4 * Copyright (C) 2015 Xilinx Inc
5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
16 */
17
18 #include "qemu/osdep.h"
19 #include "qapi/error.h"
20 #include "qemu/module.h"
21 #include "hw/arm/xlnx-zynqmp.h"
22 #include "hw/intc/arm_gic_common.h"
23 #include "hw/misc/unimp.h"
24 #include "hw/boards.h"
25 #include "sysemu/kvm.h"
26 #include "sysemu/sysemu.h"
27 #include "kvm_arm.h"
28 #include "target/arm/cpu-qom.h"
29 #include "target/arm/gtimer.h"
30
31 #define GIC_NUM_SPI_INTR 160
32
33 #define ARM_PHYS_TIMER_PPI 30
34 #define ARM_VIRT_TIMER_PPI 27
35 #define ARM_HYP_TIMER_PPI 26
36 #define ARM_SEC_TIMER_PPI 29
37 #define GIC_MAINTENANCE_PPI 25
38
39 #define GEM_REVISION 0x40070106
40
41 #define GIC_BASE_ADDR 0xf9000000
42 #define GIC_DIST_ADDR 0xf9010000
43 #define GIC_CPU_ADDR 0xf9020000
44 #define GIC_VIFACE_ADDR 0xf9040000
45 #define GIC_VCPU_ADDR 0xf9060000
46
47 #define SATA_INTR 133
48 #define SATA_ADDR 0xFD0C0000
49 #define SATA_NUM_PORTS 2
50
51 #define QSPI_ADDR 0xff0f0000
52 #define LQSPI_ADDR 0xc0000000
53 #define QSPI_IRQ 15
54 #define QSPI_DMA_ADDR 0xff0f0800
55 #define NUM_QSPI_IRQ_LINES 2
56
57 #define CRF_ADDR 0xfd1a0000
58 #define CRF_IRQ 120
59
60 /* Serializer/Deserializer. */
61 #define SERDES_ADDR 0xfd400000
62 #define SERDES_SIZE 0x20000
63
64 #define DP_ADDR 0xfd4a0000
65 #define DP_IRQ 0x77
66
67 #define DPDMA_ADDR 0xfd4c0000
68 #define DPDMA_IRQ 0x7a
69
70 #define APU_ADDR 0xfd5c0000
71 #define APU_IRQ 153
72
73 #define TTC0_ADDR 0xFF110000
74 #define TTC0_IRQ 36
75
76 #define IPI_ADDR 0xFF300000
77 #define IPI_IRQ 64
78
79 #define RTC_ADDR 0xffa60000
80 #define RTC_IRQ 26
81
82 #define BBRAM_ADDR 0xffcd0000
83 #define BBRAM_IRQ 11
84
85 #define EFUSE_ADDR 0xffcc0000
86 #define EFUSE_IRQ 87
87
88 #define SDHCI_CAPABILITIES 0x280737ec6481 /* Datasheet: UG1085 (v1.7) */
89
90 static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
91 0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
92 };
93
94 static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = {
95 57, 59, 61, 63,
96 };
97
98 static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = {
99 0xFF000000, 0xFF010000,
100 };
101
102 static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
103 21, 22,
104 };
105
106 static const uint64_t can_addr[XLNX_ZYNQMP_NUM_CAN] = {
107 0xFF060000, 0xFF070000,
108 };
109
110 static const int can_intr[XLNX_ZYNQMP_NUM_CAN] = {
111 23, 24,
112 };
113
114 static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = {
115 0xFF160000, 0xFF170000,
116 };
117
118 static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = {
119 48, 49,
120 };
121
122 static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = {
123 0xFF040000, 0xFF050000,
124 };
125
126 static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = {
127 19, 20,
128 };
129
130 static const uint64_t gdma_ch_addr[XLNX_ZYNQMP_NUM_GDMA_CH] = {
131 0xFD500000, 0xFD510000, 0xFD520000, 0xFD530000,
132 0xFD540000, 0xFD550000, 0xFD560000, 0xFD570000
133 };
134
135 static const int gdma_ch_intr[XLNX_ZYNQMP_NUM_GDMA_CH] = {
136 124, 125, 126, 127, 128, 129, 130, 131
137 };
138
139 static const uint64_t adma_ch_addr[XLNX_ZYNQMP_NUM_ADMA_CH] = {
140 0xFFA80000, 0xFFA90000, 0xFFAA0000, 0xFFAB0000,
141 0xFFAC0000, 0xFFAD0000, 0xFFAE0000, 0xFFAF0000
142 };
143
144 static const int adma_ch_intr[XLNX_ZYNQMP_NUM_ADMA_CH] = {
145 77, 78, 79, 80, 81, 82, 83, 84
146 };
147
148 static const uint64_t usb_addr[XLNX_ZYNQMP_NUM_USB] = {
149 0xFE200000, 0xFE300000
150 };
151
152 static const int usb_intr[XLNX_ZYNQMP_NUM_USB] = {
153 65, 70
154 };
155
156 typedef struct XlnxZynqMPGICRegion {
157 int region_index;
158 uint32_t address;
159 uint32_t offset;
160 bool virt;
161 } XlnxZynqMPGICRegion;
162
163 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = {
164 /* Distributor */
165 {
166 .region_index = 0,
167 .address = GIC_DIST_ADDR,
168 .offset = 0,
169 .virt = false
170 },
171
172 /* CPU interface */
173 {
174 .region_index = 1,
175 .address = GIC_CPU_ADDR,
176 .offset = 0,
177 .virt = false
178 },
179 {
180 .region_index = 1,
181 .address = GIC_CPU_ADDR + 0x10000,
182 .offset = 0x1000,
183 .virt = false
184 },
185
186 /* Virtual interface */
187 {
188 .region_index = 2,
189 .address = GIC_VIFACE_ADDR,
190 .offset = 0,
191 .virt = true
192 },
193
194 /* Virtual CPU interface */
195 {
196 .region_index = 3,
197 .address = GIC_VCPU_ADDR,
198 .offset = 0,
199 .virt = true
200 },
201 {
202 .region_index = 3,
203 .address = GIC_VCPU_ADDR + 0x10000,
204 .offset = 0x1000,
205 .virt = true
206 },
207 };
208
209 static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
210 {
211 return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index;
212 }
213
214 static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s,
215 const char *boot_cpu, Error **errp)
216 {
217 int i;
218 int num_rpus = MIN((int)(ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS),
219 XLNX_ZYNQMP_NUM_RPU_CPUS);
220
221 if (num_rpus <= 0) {
222 /* Don't create rpu-cluster object if there's nothing to put in it */
223 return;
224 }
225
226 object_initialize_child(OBJECT(s), "rpu-cluster", &s->rpu_cluster,
227 TYPE_CPU_CLUSTER);
228 qdev_prop_set_uint32(DEVICE(&s->rpu_cluster), "cluster-id", 1);
229
230 for (i = 0; i < num_rpus; i++) {
231 const char *name;
232
233 object_initialize_child(OBJECT(&s->rpu_cluster), "rpu-cpu[*]",
234 &s->rpu_cpu[i],
235 ARM_CPU_TYPE_NAME("cortex-r5f"));
236
237 name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i]));
238 if (strcmp(name, boot_cpu)) {
239 /*
240 * Secondary CPUs start in powered-down state.
241 */
242 object_property_set_bool(OBJECT(&s->rpu_cpu[i]),
243 "start-powered-off", true, &error_abort);
244 } else {
245 s->boot_cpu_ptr = &s->rpu_cpu[i];
246 }
247
248 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), "reset-hivecs", true,
249 &error_abort);
250 if (!qdev_realize(DEVICE(&s->rpu_cpu[i]), NULL, errp)) {
251 return;
252 }
253 }
254
255 qdev_realize(DEVICE(&s->rpu_cluster), NULL, &error_fatal);
256 }
257
258 static void xlnx_zynqmp_create_bbram(XlnxZynqMPState *s, qemu_irq *gic)
259 {
260 SysBusDevice *sbd;
261
262 object_initialize_child_with_props(OBJECT(s), "bbram", &s->bbram,
263 sizeof(s->bbram), TYPE_XLNX_BBRAM,
264 &error_fatal,
265 "crc-zpads", "1",
266 NULL);
267 sbd = SYS_BUS_DEVICE(&s->bbram);
268
269 sysbus_realize(sbd, &error_fatal);
270 sysbus_mmio_map(sbd, 0, BBRAM_ADDR);
271 sysbus_connect_irq(sbd, 0, gic[BBRAM_IRQ]);
272 }
273
274 static void xlnx_zynqmp_create_efuse(XlnxZynqMPState *s, qemu_irq *gic)
275 {
276 Object *bits = OBJECT(&s->efuse);
277 Object *ctrl = OBJECT(&s->efuse_ctrl);
278 SysBusDevice *sbd;
279
280 object_initialize_child(OBJECT(s), "efuse-ctrl", &s->efuse_ctrl,
281 TYPE_XLNX_ZYNQMP_EFUSE);
282
283 object_initialize_child_with_props(ctrl, "xlnx-efuse@0", bits,
284 sizeof(s->efuse),
285 TYPE_XLNX_EFUSE, &error_abort,
286 "efuse-nr", "3",
287 "efuse-size", "2048",
288 NULL);
289
290 qdev_realize(DEVICE(bits), NULL, &error_abort);
291 object_property_set_link(ctrl, "efuse", bits, &error_abort);
292
293 sbd = SYS_BUS_DEVICE(ctrl);
294 sysbus_realize(sbd, &error_abort);
295 sysbus_mmio_map(sbd, 0, EFUSE_ADDR);
296 sysbus_connect_irq(sbd, 0, gic[EFUSE_IRQ]);
297 }
298
299 static void xlnx_zynqmp_create_apu_ctrl(XlnxZynqMPState *s, qemu_irq *gic)
300 {
301 SysBusDevice *sbd;
302 int i;
303
304 object_initialize_child(OBJECT(s), "apu-ctrl", &s->apu_ctrl,
305 TYPE_XLNX_ZYNQMP_APU_CTRL);
306 sbd = SYS_BUS_DEVICE(&s->apu_ctrl);
307
308 for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
309 g_autofree gchar *name = g_strdup_printf("cpu%d", i);
310
311 object_property_set_link(OBJECT(&s->apu_ctrl), name,
312 OBJECT(&s->apu_cpu[i]), &error_abort);
313 }
314
315 sysbus_realize(sbd, &error_fatal);
316 sysbus_mmio_map(sbd, 0, APU_ADDR);
317 sysbus_connect_irq(sbd, 0, gic[APU_IRQ]);
318 }
319
320 static void xlnx_zynqmp_create_crf(XlnxZynqMPState *s, qemu_irq *gic)
321 {
322 SysBusDevice *sbd;
323
324 object_initialize_child(OBJECT(s), "crf", &s->crf, TYPE_XLNX_ZYNQMP_CRF);
325 sbd = SYS_BUS_DEVICE(&s->crf);
326
327 sysbus_realize(sbd, &error_fatal);
328 sysbus_mmio_map(sbd, 0, CRF_ADDR);
329 sysbus_connect_irq(sbd, 0, gic[CRF_IRQ]);
330 }
331
332 static void xlnx_zynqmp_create_ttc(XlnxZynqMPState *s, qemu_irq *gic)
333 {
334 SysBusDevice *sbd;
335 int i, irq;
336
337 for (i = 0; i < XLNX_ZYNQMP_NUM_TTC; i++) {
338 object_initialize_child(OBJECT(s), "ttc[*]", &s->ttc[i],
339 TYPE_CADENCE_TTC);
340 sbd = SYS_BUS_DEVICE(&s->ttc[i]);
341
342 sysbus_realize(sbd, &error_fatal);
343 sysbus_mmio_map(sbd, 0, TTC0_ADDR + i * 0x10000);
344 for (irq = 0; irq < 3; irq++) {
345 sysbus_connect_irq(sbd, irq, gic[TTC0_IRQ + i * 3 + irq]);
346 }
347 }
348 }
349
350 static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s)
351 {
352 static const struct UnimpInfo {
353 const char *name;
354 hwaddr base;
355 hwaddr size;
356 } unimp_areas[ARRAY_SIZE(s->mr_unimp)] = {
357 { .name = "serdes", SERDES_ADDR, SERDES_SIZE },
358 };
359 unsigned int nr;
360
361 for (nr = 0; nr < ARRAY_SIZE(unimp_areas); nr++) {
362 const struct UnimpInfo *info = &unimp_areas[nr];
363 DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE);
364 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
365
366 assert(info->name && info->base && info->size > 0);
367 qdev_prop_set_string(dev, "name", info->name);
368 qdev_prop_set_uint64(dev, "size", info->size);
369 object_property_add_child(OBJECT(s), info->name, OBJECT(dev));
370
371 sysbus_realize_and_unref(sbd, &error_fatal);
372 sysbus_mmio_map(sbd, 0, info->base);
373 }
374 }
375
376 static void xlnx_zynqmp_init(Object *obj)
377 {
378 MachineState *ms = MACHINE(qdev_get_machine());
379 XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
380 int i;
381 int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
382
383 object_initialize_child(obj, "apu-cluster", &s->apu_cluster,
384 TYPE_CPU_CLUSTER);
385 qdev_prop_set_uint32(DEVICE(&s->apu_cluster), "cluster-id", 0);
386
387 for (i = 0; i < num_apus; i++) {
388 object_initialize_child(OBJECT(&s->apu_cluster), "apu-cpu[*]",
389 &s->apu_cpu[i],
390 ARM_CPU_TYPE_NAME("cortex-a53"));
391 }
392
393 object_initialize_child(obj, "gic", &s->gic, gic_class_name());
394
395 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
396 object_initialize_child(obj, "gem[*]", &s->gem[i], TYPE_CADENCE_GEM);
397 }
398
399 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
400 object_initialize_child(obj, "uart[*]", &s->uart[i],
401 TYPE_CADENCE_UART);
402 }
403
404 for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) {
405 object_initialize_child(obj, "can[*]", &s->can[i],
406 TYPE_XLNX_ZYNQMP_CAN);
407 }
408
409 object_initialize_child(obj, "sata", &s->sata, TYPE_SYSBUS_AHCI);
410
411 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
412 object_initialize_child(obj, "sdhci[*]", &s->sdhci[i],
413 TYPE_SYSBUS_SDHCI);
414 }
415
416 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
417 object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_XILINX_SPIPS);
418 }
419
420 object_initialize_child(obj, "qspi", &s->qspi, TYPE_XLNX_ZYNQMP_QSPIPS);
421
422 object_initialize_child(obj, "xxxdp", &s->dp, TYPE_XLNX_DP);
423
424 object_initialize_child(obj, "dp-dma", &s->dpdma, TYPE_XLNX_DPDMA);
425
426 object_initialize_child(obj, "ipi", &s->ipi, TYPE_XLNX_ZYNQMP_IPI);
427
428 object_initialize_child(obj, "rtc", &s->rtc, TYPE_XLNX_ZYNQMP_RTC);
429
430 for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
431 object_initialize_child(obj, "gdma[*]", &s->gdma[i], TYPE_XLNX_ZDMA);
432 }
433
434 for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) {
435 object_initialize_child(obj, "adma[*]", &s->adma[i], TYPE_XLNX_ZDMA);
436 }
437
438 object_initialize_child(obj, "qspi-dma", &s->qspi_dma, TYPE_XLNX_CSU_DMA);
439 object_initialize_child(obj, "qspi-irq-orgate",
440 &s->qspi_irq_orgate, TYPE_OR_IRQ);
441
442 for (i = 0; i < XLNX_ZYNQMP_NUM_USB; i++) {
443 object_initialize_child(obj, "usb[*]", &s->usb[i], TYPE_USB_DWC3);
444 }
445 }
446
447 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
448 {
449 MachineState *ms = MACHINE(qdev_get_machine());
450 XlnxZynqMPState *s = XLNX_ZYNQMP(dev);
451 MemoryRegion *system_memory = get_system_memory();
452 uint8_t i;
453 uint64_t ram_size;
454 int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
455 const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]";
456 ram_addr_t ddr_low_size, ddr_high_size;
457 qemu_irq gic_spi[GIC_NUM_SPI_INTR];
458 Error *err = NULL;
459
460 ram_size = memory_region_size(s->ddr_ram);
461
462 /*
463 * Create the DDR Memory Regions. User friendly checks should happen at
464 * the board level
465 */
466 if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) {
467 /*
468 * The RAM size is above the maximum available for the low DDR.
469 * Create the high DDR memory region as well.
470 */
471 assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE);
472 ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
473 ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
474
475 memory_region_init_alias(&s->ddr_ram_high, OBJECT(dev),
476 "ddr-ram-high", s->ddr_ram, ddr_low_size,
477 ddr_high_size);
478 memory_region_add_subregion(get_system_memory(),
479 XLNX_ZYNQMP_HIGH_RAM_START,
480 &s->ddr_ram_high);
481 } else {
482 /* RAM must be non-zero */
483 assert(ram_size);
484 ddr_low_size = ram_size;
485 }
486
487 memory_region_init_alias(&s->ddr_ram_low, OBJECT(dev), "ddr-ram-low",
488 s->ddr_ram, 0, ddr_low_size);
489 memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low);
490
491 /* Create the four OCM banks */
492 for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) {
493 char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i);
494
495 memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name,
496 XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal);
497 memory_region_add_subregion(get_system_memory(),
498 XLNX_ZYNQMP_OCM_RAM_0_ADDRESS +
499 i * XLNX_ZYNQMP_OCM_RAM_SIZE,
500 &s->ocm_ram[i]);
501
502 g_free(ocm_name);
503 }
504
505 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
506 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
507 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", num_apus);
508 qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", s->secure);
509 qdev_prop_set_bit(DEVICE(&s->gic),
510 "has-virtualization-extensions", s->virt);
511
512 qdev_realize(DEVICE(&s->apu_cluster), NULL, &error_fatal);
513
514 /* Realize APUs before realizing the GIC. KVM requires this. */
515 for (i = 0; i < num_apus; i++) {
516 const char *name;
517
518 name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i]));
519 if (strcmp(name, boot_cpu)) {
520 /*
521 * Secondary CPUs start in powered-down state.
522 */
523 object_property_set_bool(OBJECT(&s->apu_cpu[i]),
524 "start-powered-off", true, &error_abort);
525 } else {
526 s->boot_cpu_ptr = &s->apu_cpu[i];
527 }
528
529 object_property_set_bool(OBJECT(&s->apu_cpu[i]), "has_el3", s->secure,
530 NULL);
531 object_property_set_bool(OBJECT(&s->apu_cpu[i]), "has_el2", s->virt,
532 NULL);
533 object_property_set_int(OBJECT(&s->apu_cpu[i]), "reset-cbar",
534 GIC_BASE_ADDR, &error_abort);
535 object_property_set_int(OBJECT(&s->apu_cpu[i]), "core-count",
536 num_apus, &error_abort);
537 if (!qdev_realize(DEVICE(&s->apu_cpu[i]), NULL, errp)) {
538 return;
539 }
540 }
541
542 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) {
543 return;
544 }
545
546 assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS);
547 for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) {
548 SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic);
549 const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i];
550 MemoryRegion *mr;
551 uint32_t addr = r->address;
552 int j;
553
554 if (r->virt && !s->virt) {
555 continue;
556 }
557
558 mr = sysbus_mmio_get_region(gic, r->region_index);
559 for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) {
560 MemoryRegion *alias = &s->gic_mr[i][j];
561
562 memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr,
563 r->offset, XLNX_ZYNQMP_GIC_REGION_SIZE);
564 memory_region_add_subregion(system_memory, addr, alias);
565
566 addr += XLNX_ZYNQMP_GIC_REGION_SIZE;
567 }
568 }
569
570 for (i = 0; i < num_apus; i++) {
571 qemu_irq irq;
572
573 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
574 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
575 ARM_CPU_IRQ));
576 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus,
577 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
578 ARM_CPU_FIQ));
579 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 2,
580 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
581 ARM_CPU_VIRQ));
582 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 3,
583 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
584 ARM_CPU_VFIQ));
585 irq = qdev_get_gpio_in(DEVICE(&s->gic),
586 arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI));
587 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_PHYS, irq);
588 irq = qdev_get_gpio_in(DEVICE(&s->gic),
589 arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI));
590 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_VIRT, irq);
591 irq = qdev_get_gpio_in(DEVICE(&s->gic),
592 arm_gic_ppi_index(i, ARM_HYP_TIMER_PPI));
593 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_HYP, irq);
594 irq = qdev_get_gpio_in(DEVICE(&s->gic),
595 arm_gic_ppi_index(i, ARM_SEC_TIMER_PPI));
596 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_SEC, irq);
597
598 if (s->virt) {
599 irq = qdev_get_gpio_in(DEVICE(&s->gic),
600 arm_gic_ppi_index(i, GIC_MAINTENANCE_PPI));
601 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 4, irq);
602 }
603 }
604
605 xlnx_zynqmp_create_rpu(ms, s, boot_cpu, &err);
606 if (err) {
607 error_propagate(errp, err);
608 return;
609 }
610
611 if (!s->boot_cpu_ptr) {
612 error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu);
613 return;
614 }
615
616 for (i = 0; i < GIC_NUM_SPI_INTR; i++) {
617 gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i);
618 }
619
620 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
621 qemu_configure_nic_device(DEVICE(&s->gem[i]), true, NULL);
622 object_property_set_int(OBJECT(&s->gem[i]), "revision", GEM_REVISION,
623 &error_abort);
624 object_property_set_int(OBJECT(&s->gem[i]), "phy-addr", 23,
625 &error_abort);
626 object_property_set_int(OBJECT(&s->gem[i]), "num-priority-queues", 2,
627 &error_abort);
628 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem[i]), errp)) {
629 return;
630 }
631 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]);
632 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0,
633 gic_spi[gem_intr[i]]);
634 }
635
636 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
637 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
638 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), errp)) {
639 return;
640 }
641 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]);
642 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
643 gic_spi[uart_intr[i]]);
644 }
645
646 for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) {
647 object_property_set_int(OBJECT(&s->can[i]), "ext_clk_freq",
648 XLNX_ZYNQMP_CAN_REF_CLK, &error_abort);
649
650 object_property_set_link(OBJECT(&s->can[i]), "canbus",
651 OBJECT(s->canbus[i]), &error_fatal);
652
653 sysbus_realize(SYS_BUS_DEVICE(&s->can[i]), &err);
654 if (err) {
655 error_propagate(errp, err);
656 return;
657 }
658 sysbus_mmio_map(SYS_BUS_DEVICE(&s->can[i]), 0, can_addr[i]);
659 sysbus_connect_irq(SYS_BUS_DEVICE(&s->can[i]), 0,
660 gic_spi[can_intr[i]]);
661 }
662
663 object_property_set_int(OBJECT(&s->sata), "num-ports", SATA_NUM_PORTS,
664 &error_abort);
665 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sata), errp)) {
666 return;
667 }
668
669 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR);
670 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]);
671
672 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
673 char *bus_name;
674 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->sdhci[i]);
675 Object *sdhci = OBJECT(&s->sdhci[i]);
676
677 /*
678 * Compatible with:
679 * - SD Host Controller Specification Version 3.00
680 * - SDIO Specification Version 3.0
681 * - eMMC Specification Version 4.51
682 */
683 if (!object_property_set_uint(sdhci, "sd-spec-version", 3, errp)) {
684 return;
685 }
686 if (!object_property_set_uint(sdhci, "capareg", SDHCI_CAPABILITIES,
687 errp)) {
688 return;
689 }
690 if (!object_property_set_uint(sdhci, "uhs", UHS_I, errp)) {
691 return;
692 }
693 if (!sysbus_realize(SYS_BUS_DEVICE(sdhci), errp)) {
694 return;
695 }
696 sysbus_mmio_map(sbd, 0, sdhci_addr[i]);
697 sysbus_connect_irq(sbd, 0, gic_spi[sdhci_intr[i]]);
698
699 /* Alias controller SD bus to the SoC itself */
700 bus_name = g_strdup_printf("sd-bus%d", i);
701 object_property_add_alias(OBJECT(s), bus_name, sdhci, "sd-bus");
702 g_free(bus_name);
703 }
704
705 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
706 gchar *bus_name;
707
708 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
709 return;
710 }
711
712 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
713 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
714 gic_spi[spi_intr[i]]);
715
716 /* Alias controller SPI bus to the SoC itself */
717 bus_name = g_strdup_printf("spi%d", i);
718 object_property_add_alias(OBJECT(s), bus_name,
719 OBJECT(&s->spi[i]), "spi0");
720 g_free(bus_name);
721 }
722
723 if (!sysbus_realize(SYS_BUS_DEVICE(&s->dp), errp)) {
724 return;
725 }
726 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dp), 0, DP_ADDR);
727 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dp), 0, gic_spi[DP_IRQ]);
728
729 if (!sysbus_realize(SYS_BUS_DEVICE(&s->dpdma), errp)) {
730 return;
731 }
732 object_property_set_link(OBJECT(&s->dp), "dpdma", OBJECT(&s->dpdma),
733 &error_abort);
734 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR);
735 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]);
736
737 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ipi), errp)) {
738 return;
739 }
740 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi), 0, IPI_ADDR);
741 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi), 0, gic_spi[IPI_IRQ]);
742
743 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) {
744 return;
745 }
746 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, RTC_ADDR);
747 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]);
748
749 xlnx_zynqmp_create_bbram(s, gic_spi);
750 xlnx_zynqmp_create_efuse(s, gic_spi);
751 xlnx_zynqmp_create_apu_ctrl(s, gic_spi);
752 xlnx_zynqmp_create_crf(s, gic_spi);
753 xlnx_zynqmp_create_ttc(s, gic_spi);
754 xlnx_zynqmp_create_unimp_mmio(s);
755
756 for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
757 if (!object_property_set_uint(OBJECT(&s->gdma[i]), "bus-width", 128,
758 errp)) {
759 return;
760 }
761 if (!object_property_set_link(OBJECT(&s->gdma[i]), "dma",
762 OBJECT(system_memory), errp)) {
763 return;
764 }
765 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gdma[i]), errp)) {
766 return;
767 }
768
769 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gdma[i]), 0, gdma_ch_addr[i]);
770 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gdma[i]), 0,
771 gic_spi[gdma_ch_intr[i]]);
772 }
773
774 for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) {
775 if (!object_property_set_link(OBJECT(&s->adma[i]), "dma",
776 OBJECT(system_memory), errp)) {
777 return;
778 }
779 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adma[i]), errp)) {
780 return;
781 }
782
783 sysbus_mmio_map(SYS_BUS_DEVICE(&s->adma[i]), 0, adma_ch_addr[i]);
784 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adma[i]), 0,
785 gic_spi[adma_ch_intr[i]]);
786 }
787
788 object_property_set_int(OBJECT(&s->qspi_irq_orgate),
789 "num-lines", NUM_QSPI_IRQ_LINES, &error_fatal);
790 qdev_realize(DEVICE(&s->qspi_irq_orgate), NULL, &error_fatal);
791 qdev_connect_gpio_out(DEVICE(&s->qspi_irq_orgate), 0, gic_spi[QSPI_IRQ]);
792
793 if (!object_property_set_link(OBJECT(&s->qspi_dma), "dma",
794 OBJECT(system_memory), errp)) {
795 return;
796 }
797 if (!sysbus_realize(SYS_BUS_DEVICE(&s->qspi_dma), errp)) {
798 return;
799 }
800
801 sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi_dma), 0, QSPI_DMA_ADDR);
802 sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi_dma), 0,
803 qdev_get_gpio_in(DEVICE(&s->qspi_irq_orgate), 0));
804
805 if (!object_property_set_link(OBJECT(&s->qspi), "stream-connected-dma",
806 OBJECT(&s->qspi_dma), errp)) {
807 return;
808 }
809 if (!sysbus_realize(SYS_BUS_DEVICE(&s->qspi), errp)) {
810 return;
811 }
812 sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 0, QSPI_ADDR);
813 sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 1, LQSPI_ADDR);
814 sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi), 0,
815 qdev_get_gpio_in(DEVICE(&s->qspi_irq_orgate), 1));
816
817 for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_BUS; i++) {
818 g_autofree gchar *bus_name = g_strdup_printf("qspi%d", i);
819 g_autofree gchar *target_bus = g_strdup_printf("spi%d", i);
820
821 /* Alias controller SPI bus to the SoC itself */
822 object_property_add_alias(OBJECT(s), bus_name,
823 OBJECT(&s->qspi), target_bus);
824 }
825
826 for (i = 0; i < XLNX_ZYNQMP_NUM_USB; i++) {
827 if (!object_property_set_link(OBJECT(&s->usb[i].sysbus_xhci), "dma",
828 OBJECT(system_memory), errp)) {
829 return;
830 }
831
832 qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), "intrs", 4);
833 qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), "slots", 2);
834
835 if (!sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), errp)) {
836 return;
837 }
838
839 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, usb_addr[i]);
840 sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 0,
841 gic_spi[usb_intr[i]]);
842 sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 1,
843 gic_spi[usb_intr[i] + 1]);
844 sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 2,
845 gic_spi[usb_intr[i] + 2]);
846 sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 3,
847 gic_spi[usb_intr[i] + 3]);
848 }
849 }
850
851 static Property xlnx_zynqmp_props[] = {
852 DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu),
853 DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false),
854 DEFINE_PROP_BOOL("virtualization", XlnxZynqMPState, virt, false),
855 DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION,
856 MemoryRegion *),
857 DEFINE_PROP_LINK("canbus0", XlnxZynqMPState, canbus[0], TYPE_CAN_BUS,
858 CanBusState *),
859 DEFINE_PROP_LINK("canbus1", XlnxZynqMPState, canbus[1], TYPE_CAN_BUS,
860 CanBusState *),
861 DEFINE_PROP_END_OF_LIST()
862 };
863
864 static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data)
865 {
866 DeviceClass *dc = DEVICE_CLASS(oc);
867
868 device_class_set_props(dc, xlnx_zynqmp_props);
869 dc->realize = xlnx_zynqmp_realize;
870 /* Reason: Uses serial_hd in realize function, thus can't be used twice */
871 dc->user_creatable = false;
872 }
873
874 static const TypeInfo xlnx_zynqmp_type_info = {
875 .name = TYPE_XLNX_ZYNQMP,
876 .parent = TYPE_DEVICE,
877 .instance_size = sizeof(XlnxZynqMPState),
878 .instance_init = xlnx_zynqmp_init,
879 .class_init = xlnx_zynqmp_class_init,
880 };
881
882 static void xlnx_zynqmp_register_types(void)
883 {
884 type_register_static(&xlnx_zynqmp_type_info);
885 }
886
887 type_init(xlnx_zynqmp_register_types)
AR7 emulation for QEMU