hw/arm/allwinner-a10.c

   1 /*
   2  * Allwinner A10 SoC emulation
   3  *
   4  * Copyright (C) 2013 Li Guang
   5  * Written by Li Guang <lig.fnst@cn.fujitsu.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  15  * for more details.
  16  */
  17
  18 #include "hw/sysbus.h"
  19 #include "hw/devices.h"
  20 #include "hw/arm/allwinner-a10.h"
  21
  22 static void aw_a10_init(Object *obj)
  23 {
  24     AwA10State *s = AW_A10(obj);
  25
  26     object_initialize(&s->cpu, sizeof(s->cpu), "cortex-a8-" TYPE_ARM_CPU);
  27     object_property_add_child(obj, "cpu", OBJECT(&s->cpu), NULL);
  28
  29     object_initialize(&s->intc, sizeof(s->intc), TYPE_AW_A10_PIC);
  30     qdev_set_parent_bus(DEVICE(&s->intc), sysbus_get_default());
  31
  32     object_initialize(&s->timer, sizeof(s->timer), TYPE_AW_A10_PIT);
  33     qdev_set_parent_bus(DEVICE(&s->timer), sysbus_get_default());
  34
  35     object_initialize(&s->emac, sizeof(s->emac), TYPE_AW_EMAC);
  36     qdev_set_parent_bus(DEVICE(&s->emac), sysbus_get_default());
  37     /* FIXME use qdev NIC properties instead of nd_table[] */
  38     if (nd_table[0].used) {
  39         qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC);
  40         qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
  41     }
  42
  43     object_initialize(&s->sata, sizeof(s->sata), TYPE_ALLWINNER_AHCI);
  44     qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default());
  45 }
  46
  47 static void aw_a10_realize(DeviceState *dev, Error **errp)
  48 {
  49     AwA10State *s = AW_A10(dev);
  50     SysBusDevice *sysbusdev;
  51     uint8_t i;
  52     qemu_irq fiq, irq;
  53     Error *err = NULL;
  54
  55     object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
  56     if (err != NULL) {
  57         error_propagate(errp, err);
  58         return;
  59     }
  60     irq = qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ);
  61     fiq = qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ);
  62
  63     object_property_set_bool(OBJECT(&s->intc), true, "realized", &err);
  64     if (err != NULL) {
  65         error_propagate(errp, err);
  66         return;
  67     }
  68     sysbusdev = SYS_BUS_DEVICE(&s->intc);
  69     sysbus_mmio_map(sysbusdev, 0, AW_A10_PIC_REG_BASE);
  70     sysbus_connect_irq(sysbusdev, 0, irq);
  71     sysbus_connect_irq(sysbusdev, 1, fiq);
  72     for (i = 0; i < AW_A10_PIC_INT_NR; i++) {
  73         s->irq[i] = qdev_get_gpio_in(DEVICE(&s->intc), i);
  74     }
  75
  76     object_property_set_bool(OBJECT(&s->timer), true, "realized", &err);
  77     if (err != NULL) {
  78         error_propagate(errp, err);
  79         return;
  80     }
  81     sysbusdev = SYS_BUS_DEVICE(&s->timer);
  82     sysbus_mmio_map(sysbusdev, 0, AW_A10_PIT_REG_BASE);
  83     sysbus_connect_irq(sysbusdev, 0, s->irq[22]);
  84     sysbus_connect_irq(sysbusdev, 1, s->irq[23]);
  85     sysbus_connect_irq(sysbusdev, 2, s->irq[24]);
  86     sysbus_connect_irq(sysbusdev, 3, s->irq[25]);
  87     sysbus_connect_irq(sysbusdev, 4, s->irq[67]);
  88     sysbus_connect_irq(sysbusdev, 5, s->irq[68]);
  89
  90     object_property_set_bool(OBJECT(&s->emac), true, "realized", &err);
  91     if (err != NULL) {
  92         error_propagate(errp, err);
  93         return;
  94     }
  95     sysbusdev = SYS_BUS_DEVICE(&s->emac);
  96     sysbus_mmio_map(sysbusdev, 0, AW_A10_EMAC_BASE);
  97     sysbus_connect_irq(sysbusdev, 0, s->irq[55]);
  98
  99     object_property_set_bool(OBJECT(&s->sata), true, "realized", &err);
 100     if (err) {
 101         error_propagate(errp, err);
 102         return;
 103     }
 104     sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, AW_A10_SATA_BASE);
 105     sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, s->irq[56]);
 106
 107     /* FIXME use a qdev chardev prop instead of serial_hds[] */
 108     serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2, s->irq[1],
 109                    115200, serial_hds[0], DEVICE_NATIVE_ENDIAN);
 110 }
 111
 112 static void aw_a10_class_init(ObjectClass *oc, void *data)
 113 {
 114     DeviceClass *dc = DEVICE_CLASS(oc);
 115
 116     dc->realize = aw_a10_realize;
 117
 118     /*
 119      * Reason: creates an ARM CPU, thus use after free(), see
 120      * arm_cpu_class_init()
 121      */
 122     dc->cannot_destroy_with_object_finalize_yet = true;
 123 }
 124
 125 static const TypeInfo aw_a10_type_info = {
 126     .name = TYPE_AW_A10,
 127     .parent = TYPE_DEVICE,
 128     .instance_size = sizeof(AwA10State),
 129     .instance_init = aw_a10_init,
 130     .class_init = aw_a10_class_init,
 131 };
 132
 133 static void aw_a10_register_types(void)
 134 {
 135     type_register_static(&aw_a10_type_info);
 136 }
 137
 138 type_init(aw_a10_register_types)