hw/arm/allwinner-a10.c

   1 /*
   2  * Allwinner A10 SoC emulation
   3  *
   4  * Copyright (C) 2013 Li Guang
   5  * Written by Li Guang <lig.fnst@cn.fujitsu.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  15  * for more details.
  16  */
  17
  18 #include "qemu/osdep.h"
  19 #include "qapi/error.h"
  20 #include "qemu/module.h"
  21 #include "hw/char/serial.h"
  22 #include "hw/sysbus.h"
  23 #include "hw/arm/allwinner-a10.h"
  24 #include "hw/misc/unimp.h"
  25 #include "sysemu/sysemu.h"
  26 #include "hw/boards.h"
  27 #include "hw/usb/hcd-ohci.h"
  28 #include "hw/loader.h"
  29 #include "target/arm/cpu-qom.h"
  30
  31 #define AW_A10_SRAM_A_BASE      0x00000000
  32 #define AW_A10_DRAMC_BASE       0x01c01000
  33 #define AW_A10_MMC0_BASE        0x01c0f000
  34 #define AW_A10_CCM_BASE         0x01c20000
  35 #define AW_A10_PIC_REG_BASE     0x01c20400
  36 #define AW_A10_PIT_REG_BASE     0x01c20c00
  37 #define AW_A10_UART0_REG_BASE   0x01c28000
  38 #define AW_A10_EMAC_BASE        0x01c0b000
  39 #define AW_A10_EHCI_BASE        0x01c14000
  40 #define AW_A10_OHCI_BASE        0x01c14400
  41 #define AW_A10_SATA_BASE        0x01c18000
  42 #define AW_A10_WDT_BASE         0x01c20c90
  43 #define AW_A10_RTC_BASE         0x01c20d00
  44 #define AW_A10_I2C0_BASE        0x01c2ac00
  45
  46 void allwinner_a10_bootrom_setup(AwA10State *s, BlockBackend *blk)
  47 {
  48     const int64_t rom_size = 32 * KiB;
  49     g_autofree uint8_t *buffer = g_new0(uint8_t, rom_size);
  50
  51     if (blk_pread(blk, 8 * KiB, rom_size, buffer, 0) < 0) {
  52         error_setg(&error_fatal, "%s: failed to read BlockBackend data",
  53                    __func__);
  54         return;
  55     }
  56
  57     rom_add_blob("allwinner-a10.bootrom", buffer, rom_size,
  58                   rom_size, AW_A10_SRAM_A_BASE,
  59                   NULL, NULL, NULL, NULL, false);
  60 }
  61
  62 static void aw_a10_init(Object *obj)
  63 {
  64     AwA10State *s = AW_A10(obj);
  65
  66     object_initialize_child(obj, "cpu", &s->cpu,
  67                             ARM_CPU_TYPE_NAME("cortex-a8"));
  68
  69     object_initialize_child(obj, "intc", &s->intc, TYPE_AW_A10_PIC);
  70
  71     object_initialize_child(obj, "timer", &s->timer, TYPE_AW_A10_PIT);
  72
  73     object_initialize_child(obj, "ccm", &s->ccm, TYPE_AW_A10_CCM);
  74
  75     object_initialize_child(obj, "dramc", &s->dramc, TYPE_AW_A10_DRAMC);
  76
  77     object_initialize_child(obj, "emac", &s->emac, TYPE_AW_EMAC);
  78
  79     object_initialize_child(obj, "sata", &s->sata, TYPE_ALLWINNER_AHCI);
  80
  81     object_initialize_child(obj, "i2c0", &s->i2c0, TYPE_AW_I2C);
  82
  83     for (size_t i = 0; i < AW_A10_NUM_USB; i++) {
  84         object_initialize_child(obj, "ehci[*]", &s->ehci[i],
  85                                 TYPE_PLATFORM_EHCI);
  86         object_initialize_child(obj, "ohci[*]", &s->ohci[i], TYPE_SYSBUS_OHCI);
  87     }
  88
  89     object_initialize_child(obj, "mmc0", &s->mmc0, TYPE_AW_SDHOST_SUN4I);
  90
  91     object_initialize_child(obj, "rtc", &s->rtc, TYPE_AW_RTC_SUN4I);
  92
  93     object_initialize_child(obj, "wdt", &s->wdt, TYPE_AW_WDT_SUN4I);
  94 }
  95
  96 static void aw_a10_realize(DeviceState *dev, Error **errp)
  97 {
  98     AwA10State *s = AW_A10(dev);
  99     SysBusDevice *sysbusdev;
 100
 101     if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) {
 102         return;
 103     }
 104
 105     if (!sysbus_realize(SYS_BUS_DEVICE(&s->intc), errp)) {
 106         return;
 107     }
 108     sysbusdev = SYS_BUS_DEVICE(&s->intc);
 109     sysbus_mmio_map(sysbusdev, 0, AW_A10_PIC_REG_BASE);
 110     sysbus_connect_irq(sysbusdev, 0,
 111                        qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
 112     sysbus_connect_irq(sysbusdev, 1,
 113                        qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
 114     qdev_pass_gpios(DEVICE(&s->intc), dev, NULL);
 115
 116     if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer), errp)) {
 117         return;
 118     }
 119     sysbusdev = SYS_BUS_DEVICE(&s->timer);
 120     sysbus_mmio_map(sysbusdev, 0, AW_A10_PIT_REG_BASE);
 121     sysbus_connect_irq(sysbusdev, 0, qdev_get_gpio_in(dev, 22));
 122     sysbus_connect_irq(sysbusdev, 1, qdev_get_gpio_in(dev, 23));
 123     sysbus_connect_irq(sysbusdev, 2, qdev_get_gpio_in(dev, 24));
 124     sysbus_connect_irq(sysbusdev, 3, qdev_get_gpio_in(dev, 25));
 125     sysbus_connect_irq(sysbusdev, 4, qdev_get_gpio_in(dev, 67));
 126     sysbus_connect_irq(sysbusdev, 5, qdev_get_gpio_in(dev, 68));
 127
 128     memory_region_init_ram(&s->sram_a, OBJECT(dev), "sram A", 48 * KiB,
 129                            &error_fatal);
 130     memory_region_add_subregion(get_system_memory(), 0x00000000, &s->sram_a);
 131     create_unimplemented_device("a10-sram-ctrl", 0x01c00000, 4 * KiB);
 132
 133     /* Clock Control Module */
 134     sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &error_fatal);
 135     sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, AW_A10_CCM_BASE);
 136
 137     /* DRAM Control Module */
 138     sysbus_realize(SYS_BUS_DEVICE(&s->dramc), &error_fatal);
 139     sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 0, AW_A10_DRAMC_BASE);
 140
 141     qemu_configure_nic_device(DEVICE(&s->emac), true, NULL);
 142     if (!sysbus_realize(SYS_BUS_DEVICE(&s->emac), errp)) {
 143         return;
 144     }
 145     sysbusdev = SYS_BUS_DEVICE(&s->emac);
 146     sysbus_mmio_map(sysbusdev, 0, AW_A10_EMAC_BASE);
 147     sysbus_connect_irq(sysbusdev, 0, qdev_get_gpio_in(dev, 55));
 148
 149     if (!sysbus_realize(SYS_BUS_DEVICE(&s->sata), errp)) {
 150         return;
 151     }
 152     sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, AW_A10_SATA_BASE);
 153     sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, qdev_get_gpio_in(dev, 56));
 154
 155     /* FIXME use a qdev chardev prop instead of serial_hd() */
 156     serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2,
 157                    qdev_get_gpio_in(dev, 1),
 158                    115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
 159
 160     for (size_t i = 0; i < AW_A10_NUM_USB; i++) {
 161         g_autofree char *bus = g_strdup_printf("usb-bus.%zu", i);
 162
 163         object_property_set_bool(OBJECT(&s->ehci[i]), "companion-enable",
 164                                  true, &error_fatal);
 165         sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), &error_fatal);
 166         sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0,
 167                         AW_A10_EHCI_BASE + i * 0x8000);
 168         sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
 169                            qdev_get_gpio_in(dev, 39 + i));
 170
 171         object_property_set_str(OBJECT(&s->ohci[i]), "masterbus", bus,
 172                                 &error_fatal);
 173         sysbus_realize(SYS_BUS_DEVICE(&s->ohci[i]), &error_fatal);
 174         sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci[i]), 0,
 175                         AW_A10_OHCI_BASE + i * 0x8000);
 176         sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci[i]), 0,
 177                            qdev_get_gpio_in(dev, 64 + i));
 178     }
 179
 180     /* SD/MMC */
 181     object_property_set_link(OBJECT(&s->mmc0), "dma-memory",
 182                              OBJECT(get_system_memory()), &error_fatal);
 183     sysbus_realize(SYS_BUS_DEVICE(&s->mmc0), &error_fatal);
 184     sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, AW_A10_MMC0_BASE);
 185     sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0, qdev_get_gpio_in(dev, 32));
 186     object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0),
 187                               "sd-bus");
 188
 189     /* RTC */
 190     sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &error_fatal);
 191     sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->rtc), 0, AW_A10_RTC_BASE, 10);
 192
 193     /* I2C */
 194     sysbus_realize(SYS_BUS_DEVICE(&s->i2c0), &error_fatal);
 195     sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c0), 0, AW_A10_I2C0_BASE);
 196     sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c0), 0, qdev_get_gpio_in(dev, 7));
 197
 198     /* WDT */
 199     sysbus_realize(SYS_BUS_DEVICE(&s->wdt), &error_fatal);
 200     sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->wdt), 0, AW_A10_WDT_BASE, 1);
 201 }
 202
 203 static void aw_a10_class_init(ObjectClass *oc, void *data)
 204 {
 205     DeviceClass *dc = DEVICE_CLASS(oc);
 206
 207     dc->realize = aw_a10_realize;
 208     /* Reason: Uses serial_hd and nd_table in realize function */
 209     dc->user_creatable = false;
 210 }
 211
 212 static const TypeInfo aw_a10_type_info = {
 213     .name = TYPE_AW_A10,
 214     .parent = TYPE_DEVICE,
 215     .instance_size = sizeof(AwA10State),
 216     .instance_init = aw_a10_init,
 217     .class_init = aw_a10_class_init,
 218 };
 219
 220 static void aw_a10_register_types(void)
 221 {
 222     type_register_static(&aw_a10_type_info);
 223 }
 224
 225 type_init(aw_a10_register_types)