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rtl8139: Fix receive buffer overflow check
[qemu/ar7.git] / hw / net / cadence_gem.c
blob494a346cf6f2d0023e9d53c32e3f858ce8117364
1 /*
2 * QEMU Cadence GEM emulation
3 *
4 * Copyright (c) 2011 Xilinx, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include <zlib.h> /* For crc32 */
26
27 #include "hw/net/cadence_gem.h"
28 #include "net/checksum.h"
29
30 #ifdef CADENCE_GEM_ERR_DEBUG
31 #define DB_PRINT(...) do { \
32 fprintf(stderr, ": %s: ", __func__); \
33 fprintf(stderr, ## __VA_ARGS__); \
34 } while (0);
35 #else
36 #define DB_PRINT(...)
37 #endif
38
39 #define GEM_NWCTRL (0x00000000/4) /* Network Control reg */
40 #define GEM_NWCFG (0x00000004/4) /* Network Config reg */
41 #define GEM_NWSTATUS (0x00000008/4) /* Network Status reg */
42 #define GEM_USERIO (0x0000000C/4) /* User IO reg */
43 #define GEM_DMACFG (0x00000010/4) /* DMA Control reg */
44 #define GEM_TXSTATUS (0x00000014/4) /* TX Status reg */
45 #define GEM_RXQBASE (0x00000018/4) /* RX Q Base address reg */
46 #define GEM_TXQBASE (0x0000001C/4) /* TX Q Base address reg */
47 #define GEM_RXSTATUS (0x00000020/4) /* RX Status reg */
48 #define GEM_ISR (0x00000024/4) /* Interrupt Status reg */
49 #define GEM_IER (0x00000028/4) /* Interrupt Enable reg */
50 #define GEM_IDR (0x0000002C/4) /* Interrupt Disable reg */
51 #define GEM_IMR (0x00000030/4) /* Interrupt Mask reg */
52 #define GEM_PHYMNTNC (0x00000034/4) /* Phy Maintenance reg */
53 #define GEM_RXPAUSE (0x00000038/4) /* RX Pause Time reg */
54 #define GEM_TXPAUSE (0x0000003C/4) /* TX Pause Time reg */
55 #define GEM_TXPARTIALSF (0x00000040/4) /* TX Partial Store and Forward */
56 #define GEM_RXPARTIALSF (0x00000044/4) /* RX Partial Store and Forward */
57 #define GEM_HASHLO (0x00000080/4) /* Hash Low address reg */
58 #define GEM_HASHHI (0x00000084/4) /* Hash High address reg */
59 #define GEM_SPADDR1LO (0x00000088/4) /* Specific addr 1 low reg */
60 #define GEM_SPADDR1HI (0x0000008C/4) /* Specific addr 1 high reg */
61 #define GEM_SPADDR2LO (0x00000090/4) /* Specific addr 2 low reg */
62 #define GEM_SPADDR2HI (0x00000094/4) /* Specific addr 2 high reg */
63 #define GEM_SPADDR3LO (0x00000098/4) /* Specific addr 3 low reg */
64 #define GEM_SPADDR3HI (0x0000009C/4) /* Specific addr 3 high reg */
65 #define GEM_SPADDR4LO (0x000000A0/4) /* Specific addr 4 low reg */
66 #define GEM_SPADDR4HI (0x000000A4/4) /* Specific addr 4 high reg */
67 #define GEM_TIDMATCH1 (0x000000A8/4) /* Type ID1 Match reg */
68 #define GEM_TIDMATCH2 (0x000000AC/4) /* Type ID2 Match reg */
69 #define GEM_TIDMATCH3 (0x000000B0/4) /* Type ID3 Match reg */
70 #define GEM_TIDMATCH4 (0x000000B4/4) /* Type ID4 Match reg */
71 #define GEM_WOLAN (0x000000B8/4) /* Wake on LAN reg */
72 #define GEM_IPGSTRETCH (0x000000BC/4) /* IPG Stretch reg */
73 #define GEM_SVLAN (0x000000C0/4) /* Stacked VLAN reg */
74 #define GEM_MODID (0x000000FC/4) /* Module ID reg */
75 #define GEM_OCTTXLO (0x00000100/4) /* Octects transmitted Low reg */
76 #define GEM_OCTTXHI (0x00000104/4) /* Octects transmitted High reg */
77 #define GEM_TXCNT (0x00000108/4) /* Error-free Frames transmitted */
78 #define GEM_TXBCNT (0x0000010C/4) /* Error-free Broadcast Frames */
79 #define GEM_TXMCNT (0x00000110/4) /* Error-free Multicast Frame */
80 #define GEM_TXPAUSECNT (0x00000114/4) /* Pause Frames Transmitted */
81 #define GEM_TX64CNT (0x00000118/4) /* Error-free 64 TX */
82 #define GEM_TX65CNT (0x0000011C/4) /* Error-free 65-127 TX */
83 #define GEM_TX128CNT (0x00000120/4) /* Error-free 128-255 TX */
84 #define GEM_TX256CNT (0x00000124/4) /* Error-free 256-511 */
85 #define GEM_TX512CNT (0x00000128/4) /* Error-free 512-1023 TX */
86 #define GEM_TX1024CNT (0x0000012C/4) /* Error-free 1024-1518 TX */
87 #define GEM_TX1519CNT (0x00000130/4) /* Error-free larger than 1519 TX */
88 #define GEM_TXURUNCNT (0x00000134/4) /* TX under run error counter */
89 #define GEM_SINGLECOLLCNT (0x00000138/4) /* Single Collision Frames */
90 #define GEM_MULTCOLLCNT (0x0000013C/4) /* Multiple Collision Frames */
91 #define GEM_EXCESSCOLLCNT (0x00000140/4) /* Excessive Collision Frames */
92 #define GEM_LATECOLLCNT (0x00000144/4) /* Late Collision Frames */
93 #define GEM_DEFERTXCNT (0x00000148/4) /* Deferred Transmission Frames */
94 #define GEM_CSENSECNT (0x0000014C/4) /* Carrier Sense Error Counter */
95 #define GEM_OCTRXLO (0x00000150/4) /* Octects Received register Low */
96 #define GEM_OCTRXHI (0x00000154/4) /* Octects Received register High */
97 #define GEM_RXCNT (0x00000158/4) /* Error-free Frames Received */
98 #define GEM_RXBROADCNT (0x0000015C/4) /* Error-free Broadcast Frames RX */
99 #define GEM_RXMULTICNT (0x00000160/4) /* Error-free Multicast Frames RX */
100 #define GEM_RXPAUSECNT (0x00000164/4) /* Pause Frames Received Counter */
101 #define GEM_RX64CNT (0x00000168/4) /* Error-free 64 byte Frames RX */
102 #define GEM_RX65CNT (0x0000016C/4) /* Error-free 65-127B Frames RX */
103 #define GEM_RX128CNT (0x00000170/4) /* Error-free 128-255B Frames RX */
104 #define GEM_RX256CNT (0x00000174/4) /* Error-free 256-512B Frames RX */
105 #define GEM_RX512CNT (0x00000178/4) /* Error-free 512-1023B Frames RX */
106 #define GEM_RX1024CNT (0x0000017C/4) /* Error-free 1024-1518B Frames RX */
107 #define GEM_RX1519CNT (0x00000180/4) /* Error-free 1519-max Frames RX */
108 #define GEM_RXUNDERCNT (0x00000184/4) /* Undersize Frames Received */
109 #define GEM_RXOVERCNT (0x00000188/4) /* Oversize Frames Received */
110 #define GEM_RXJABCNT (0x0000018C/4) /* Jabbers Received Counter */
111 #define GEM_RXFCSCNT (0x00000190/4) /* Frame Check seq. Error Counter */
112 #define GEM_RXLENERRCNT (0x00000194/4) /* Length Field Error Counter */
113 #define GEM_RXSYMERRCNT (0x00000198/4) /* Symbol Error Counter */
114 #define GEM_RXALIGNERRCNT (0x0000019C/4) /* Alignment Error Counter */
115 #define GEM_RXRSCERRCNT (0x000001A0/4) /* Receive Resource Error Counter */
116 #define GEM_RXORUNCNT (0x000001A4/4) /* Receive Overrun Counter */
117 #define GEM_RXIPCSERRCNT (0x000001A8/4) /* IP header Checksum Error Counter */
118 #define GEM_RXTCPCCNT (0x000001AC/4) /* TCP Checksum Error Counter */
119 #define GEM_RXUDPCCNT (0x000001B0/4) /* UDP Checksum Error Counter */
120
121 #define GEM_1588S (0x000001D0/4) /* 1588 Timer Seconds */
122 #define GEM_1588NS (0x000001D4/4) /* 1588 Timer Nanoseconds */
123 #define GEM_1588ADJ (0x000001D8/4) /* 1588 Timer Adjust */
124 #define GEM_1588INC (0x000001DC/4) /* 1588 Timer Increment */
125 #define GEM_PTPETXS (0x000001E0/4) /* PTP Event Frame Transmitted (s) */
126 #define GEM_PTPETXNS (0x000001E4/4) /* PTP Event Frame Transmitted (ns) */
127 #define GEM_PTPERXS (0x000001E8/4) /* PTP Event Frame Received (s) */
128 #define GEM_PTPERXNS (0x000001EC/4) /* PTP Event Frame Received (ns) */
129 #define GEM_PTPPTXS (0x000001E0/4) /* PTP Peer Frame Transmitted (s) */
130 #define GEM_PTPPTXNS (0x000001E4/4) /* PTP Peer Frame Transmitted (ns) */
131 #define GEM_PTPPRXS (0x000001E8/4) /* PTP Peer Frame Received (s) */
132 #define GEM_PTPPRXNS (0x000001EC/4) /* PTP Peer Frame Received (ns) */
133
134 /* Design Configuration Registers */
135 #define GEM_DESCONF (0x00000280/4)
136 #define GEM_DESCONF2 (0x00000284/4)
137 #define GEM_DESCONF3 (0x00000288/4)
138 #define GEM_DESCONF4 (0x0000028C/4)
139 #define GEM_DESCONF5 (0x00000290/4)
140 #define GEM_DESCONF6 (0x00000294/4)
141 #define GEM_DESCONF7 (0x00000298/4)
142
143 /*****************************************/
144 #define GEM_NWCTRL_TXSTART 0x00000200 /* Transmit Enable */
145 #define GEM_NWCTRL_TXENA 0x00000008 /* Transmit Enable */
146 #define GEM_NWCTRL_RXENA 0x00000004 /* Receive Enable */
147 #define GEM_NWCTRL_LOCALLOOP 0x00000002 /* Local Loopback */
148
149 #define GEM_NWCFG_STRIP_FCS 0x00020000 /* Strip FCS field */
150 #define GEM_NWCFG_LERR_DISC 0x00010000 /* Discard RX frames with len err */
151 #define GEM_NWCFG_BUFF_OFST_M 0x0000C000 /* Receive buffer offset mask */
152 #define GEM_NWCFG_BUFF_OFST_S 14 /* Receive buffer offset shift */
153 #define GEM_NWCFG_UCAST_HASH 0x00000080 /* accept unicast if hash match */
154 #define GEM_NWCFG_MCAST_HASH 0x00000040 /* accept multicast if hash match */
155 #define GEM_NWCFG_BCAST_REJ 0x00000020 /* Reject broadcast packets */
156 #define GEM_NWCFG_PROMISC 0x00000010 /* Accept all packets */
157
158 #define GEM_DMACFG_RBUFSZ_M 0x00FF0000 /* DMA RX Buffer Size mask */
159 #define GEM_DMACFG_RBUFSZ_S 16 /* DMA RX Buffer Size shift */
160 #define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier */
161 #define GEM_DMACFG_TXCSUM_OFFL 0x00000800 /* Transmit checksum offload */
162
163 #define GEM_TXSTATUS_TXCMPL 0x00000020 /* Transmit Complete */
164 #define GEM_TXSTATUS_USED 0x00000001 /* sw owned descriptor encountered */
165
166 #define GEM_RXSTATUS_FRMRCVD 0x00000002 /* Frame received */
167 #define GEM_RXSTATUS_NOBUF 0x00000001 /* Buffer unavailable */
168
169 /* GEM_ISR GEM_IER GEM_IDR GEM_IMR */
170 #define GEM_INT_TXCMPL 0x00000080 /* Transmit Complete */
171 #define GEM_INT_TXUSED 0x00000008
172 #define GEM_INT_RXUSED 0x00000004
173 #define GEM_INT_RXCMPL 0x00000002
174
175 #define GEM_PHYMNTNC_OP_R 0x20000000 /* read operation */
176 #define GEM_PHYMNTNC_OP_W 0x10000000 /* write operation */
177 #define GEM_PHYMNTNC_ADDR 0x0F800000 /* Address bits */
178 #define GEM_PHYMNTNC_ADDR_SHFT 23
179 #define GEM_PHYMNTNC_REG 0x007C0000 /* register bits */
180 #define GEM_PHYMNTNC_REG_SHIFT 18
181
182 /* Marvell PHY definitions */
183 #define BOARD_PHY_ADDRESS 23 /* PHY address we will emulate a device at */
184
185 #define PHY_REG_CONTROL 0
186 #define PHY_REG_STATUS 1
187 #define PHY_REG_PHYID1 2
188 #define PHY_REG_PHYID2 3
189 #define PHY_REG_ANEGADV 4
190 #define PHY_REG_LINKPABIL 5
191 #define PHY_REG_ANEGEXP 6
192 #define PHY_REG_NEXTP 7
193 #define PHY_REG_LINKPNEXTP 8
194 #define PHY_REG_100BTCTRL 9
195 #define PHY_REG_1000BTSTAT 10
196 #define PHY_REG_EXTSTAT 15
197 #define PHY_REG_PHYSPCFC_CTL 16
198 #define PHY_REG_PHYSPCFC_ST 17
199 #define PHY_REG_INT_EN 18
200 #define PHY_REG_INT_ST 19
201 #define PHY_REG_EXT_PHYSPCFC_CTL 20
202 #define PHY_REG_RXERR 21
203 #define PHY_REG_EACD 22
204 #define PHY_REG_LED 24
205 #define PHY_REG_LED_OVRD 25
206 #define PHY_REG_EXT_PHYSPCFC_CTL2 26
207 #define PHY_REG_EXT_PHYSPCFC_ST 27
208 #define PHY_REG_CABLE_DIAG 28
209
210 #define PHY_REG_CONTROL_RST 0x8000
211 #define PHY_REG_CONTROL_LOOP 0x4000
212 #define PHY_REG_CONTROL_ANEG 0x1000
213
214 #define PHY_REG_STATUS_LINK 0x0004
215 #define PHY_REG_STATUS_ANEGCMPL 0x0020
216
217 #define PHY_REG_INT_ST_ANEGCMPL 0x0800
218 #define PHY_REG_INT_ST_LINKC 0x0400
219 #define PHY_REG_INT_ST_ENERGY 0x0010
220
221 /***********************************************************************/
222 #define GEM_RX_REJECT (-1)
223 #define GEM_RX_PROMISCUOUS_ACCEPT (-2)
224 #define GEM_RX_BROADCAST_ACCEPT (-3)
225 #define GEM_RX_MULTICAST_HASH_ACCEPT (-4)
226 #define GEM_RX_UNICAST_HASH_ACCEPT (-5)
227
228 #define GEM_RX_SAR_ACCEPT 0
229
230 /***********************************************************************/
231
232 #define DESC_1_USED 0x80000000
233 #define DESC_1_LENGTH 0x00001FFF
234
235 #define DESC_1_TX_WRAP 0x40000000
236 #define DESC_1_TX_LAST 0x00008000
237
238 #define DESC_0_RX_WRAP 0x00000002
239 #define DESC_0_RX_OWNERSHIP 0x00000001
240
241 #define R_DESC_1_RX_SAR_SHIFT 25
242 #define R_DESC_1_RX_SAR_LENGTH 2
243 #define R_DESC_1_RX_SAR_MATCH (1 << 27)
244 #define R_DESC_1_RX_UNICAST_HASH (1 << 29)
245 #define R_DESC_1_RX_MULTICAST_HASH (1 << 30)
246 #define R_DESC_1_RX_BROADCAST (1 << 31)
247
248 #define DESC_1_RX_SOF 0x00004000
249 #define DESC_1_RX_EOF 0x00008000
250
251 static inline unsigned tx_desc_get_buffer(unsigned *desc)
252 {
253 return desc[0];
254 }
255
256 static inline unsigned tx_desc_get_used(unsigned *desc)
257 {
258 return (desc[1] & DESC_1_USED) ? 1 : 0;
259 }
260
261 static inline void tx_desc_set_used(unsigned *desc)
262 {
263 desc[1] |= DESC_1_USED;
264 }
265
266 static inline unsigned tx_desc_get_wrap(unsigned *desc)
267 {
268 return (desc[1] & DESC_1_TX_WRAP) ? 1 : 0;
269 }
270
271 static inline unsigned tx_desc_get_last(unsigned *desc)
272 {
273 return (desc[1] & DESC_1_TX_LAST) ? 1 : 0;
274 }
275
276 static inline unsigned tx_desc_get_length(unsigned *desc)
277 {
278 return desc[1] & DESC_1_LENGTH;
279 }
280
281 static inline void print_gem_tx_desc(unsigned *desc)
282 {
283 DB_PRINT("TXDESC:\n");
284 DB_PRINT("bufaddr: 0x%08x\n", *desc);
285 DB_PRINT("used_hw: %d\n", tx_desc_get_used(desc));
286 DB_PRINT("wrap: %d\n", tx_desc_get_wrap(desc));
287 DB_PRINT("last: %d\n", tx_desc_get_last(desc));
288 DB_PRINT("length: %d\n", tx_desc_get_length(desc));
289 }
290
291 static inline unsigned rx_desc_get_buffer(unsigned *desc)
292 {
293 return desc[0] & ~0x3UL;
294 }
295
296 static inline unsigned rx_desc_get_wrap(unsigned *desc)
297 {
298 return desc[0] & DESC_0_RX_WRAP ? 1 : 0;
299 }
300
301 static inline unsigned rx_desc_get_ownership(unsigned *desc)
302 {
303 return desc[0] & DESC_0_RX_OWNERSHIP ? 1 : 0;
304 }
305
306 static inline void rx_desc_set_ownership(unsigned *desc)
307 {
308 desc[0] |= DESC_0_RX_OWNERSHIP;
309 }
310
311 static inline void rx_desc_set_sof(unsigned *desc)
312 {
313 desc[1] |= DESC_1_RX_SOF;
314 }
315
316 static inline void rx_desc_set_eof(unsigned *desc)
317 {
318 desc[1] |= DESC_1_RX_EOF;
319 }
320
321 static inline void rx_desc_set_length(unsigned *desc, unsigned len)
322 {
323 desc[1] &= ~DESC_1_LENGTH;
324 desc[1] |= len;
325 }
326
327 static inline void rx_desc_set_broadcast(unsigned *desc)
328 {
329 desc[1] |= R_DESC_1_RX_BROADCAST;
330 }
331
332 static inline void rx_desc_set_unicast_hash(unsigned *desc)
333 {
334 desc[1] |= R_DESC_1_RX_UNICAST_HASH;
335 }
336
337 static inline void rx_desc_set_multicast_hash(unsigned *desc)
338 {
339 desc[1] |= R_DESC_1_RX_MULTICAST_HASH;
340 }
341
342 static inline void rx_desc_set_sar(unsigned *desc, int sar_idx)
343 {
344 desc[1] = deposit32(desc[1], R_DESC_1_RX_SAR_SHIFT, R_DESC_1_RX_SAR_LENGTH,
345 sar_idx);
346 desc[1] |= R_DESC_1_RX_SAR_MATCH;
347 }
348
349 /* The broadcast MAC address: 0xFFFFFFFFFFFF */
350 static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
351
352 /*
353 * gem_init_register_masks:
354 * One time initialization.
355 * Set masks to identify which register bits have magical clear properties
356 */
357 static void gem_init_register_masks(CadenceGEMState *s)
358 {
359 /* Mask of register bits which are read only */
360 memset(&s->regs_ro[0], 0, sizeof(s->regs_ro));
361 s->regs_ro[GEM_NWCTRL] = 0xFFF80000;
362 s->regs_ro[GEM_NWSTATUS] = 0xFFFFFFFF;
363 s->regs_ro[GEM_DMACFG] = 0xFE00F000;
364 s->regs_ro[GEM_TXSTATUS] = 0xFFFFFE08;
365 s->regs_ro[GEM_RXQBASE] = 0x00000003;
366 s->regs_ro[GEM_TXQBASE] = 0x00000003;
367 s->regs_ro[GEM_RXSTATUS] = 0xFFFFFFF0;
368 s->regs_ro[GEM_ISR] = 0xFFFFFFFF;
369 s->regs_ro[GEM_IMR] = 0xFFFFFFFF;
370 s->regs_ro[GEM_MODID] = 0xFFFFFFFF;
371
372 /* Mask of register bits which are clear on read */
373 memset(&s->regs_rtc[0], 0, sizeof(s->regs_rtc));
374 s->regs_rtc[GEM_ISR] = 0xFFFFFFFF;
375
376 /* Mask of register bits which are write 1 to clear */
377 memset(&s->regs_w1c[0], 0, sizeof(s->regs_w1c));
378 s->regs_w1c[GEM_TXSTATUS] = 0x000001F7;
379 s->regs_w1c[GEM_RXSTATUS] = 0x0000000F;
380
381 /* Mask of register bits which are write only */
382 memset(&s->regs_wo[0], 0, sizeof(s->regs_wo));
383 s->regs_wo[GEM_NWCTRL] = 0x00073E60;
384 s->regs_wo[GEM_IER] = 0x07FFFFFF;
385 s->regs_wo[GEM_IDR] = 0x07FFFFFF;
386 }
387
388 /*
389 * phy_update_link:
390 * Make the emulated PHY link state match the QEMU "interface" state.
391 */
392 static void phy_update_link(CadenceGEMState *s)
393 {
394 DB_PRINT("down %d\n", qemu_get_queue(s->nic)->link_down);
395
396 /* Autonegotiation status mirrors link status. */
397 if (qemu_get_queue(s->nic)->link_down) {
398 s->phy_regs[PHY_REG_STATUS] &= ~(PHY_REG_STATUS_ANEGCMPL |
399 PHY_REG_STATUS_LINK);
400 s->phy_regs[PHY_REG_INT_ST] |= PHY_REG_INT_ST_LINKC;
401 } else {
402 s->phy_regs[PHY_REG_STATUS] |= (PHY_REG_STATUS_ANEGCMPL |
403 PHY_REG_STATUS_LINK);
404 s->phy_regs[PHY_REG_INT_ST] |= (PHY_REG_INT_ST_LINKC |
405 PHY_REG_INT_ST_ANEGCMPL |
406 PHY_REG_INT_ST_ENERGY);
407 }
408 }
409
410 static int gem_can_receive(NetClientState *nc)
411 {
412 CadenceGEMState *s;
413
414 s = qemu_get_nic_opaque(nc);
415
416 /* Do nothing if receive is not enabled. */
417 if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_RXENA)) {
418 if (s->can_rx_state != 1) {
419 s->can_rx_state = 1;
420 DB_PRINT("can't receive - no enable\n");
421 }
422 return 0;
423 }
424
425 if (rx_desc_get_ownership(s->rx_desc) == 1) {
426 if (s->can_rx_state != 2) {
427 s->can_rx_state = 2;
428 DB_PRINT("can't receive - busy buffer descriptor 0x%x\n",
429 s->rx_desc_addr);
430 }
431 return 0;
432 }
433
434 if (s->can_rx_state != 0) {
435 s->can_rx_state = 0;
436 DB_PRINT("can receive 0x%x\n", s->rx_desc_addr);
437 }
438 return 1;
439 }
440
441 /*
442 * gem_update_int_status:
443 * Raise or lower interrupt based on current status.
444 */
445 static void gem_update_int_status(CadenceGEMState *s)
446 {
447 if (s->regs[GEM_ISR]) {
448 DB_PRINT("asserting int. (0x%08x)\n", s->regs[GEM_ISR]);
449 qemu_set_irq(s->irq, 1);
450 }
451 }
452
453 /*
454 * gem_receive_updatestats:
455 * Increment receive statistics.
456 */
457 static void gem_receive_updatestats(CadenceGEMState *s, const uint8_t *packet,
458 unsigned bytes)
459 {
460 uint64_t octets;
461
462 /* Total octets (bytes) received */
463 octets = ((uint64_t)(s->regs[GEM_OCTRXLO]) << 32) |
464 s->regs[GEM_OCTRXHI];
465 octets += bytes;
466 s->regs[GEM_OCTRXLO] = octets >> 32;
467 s->regs[GEM_OCTRXHI] = octets;
468
469 /* Error-free Frames received */
470 s->regs[GEM_RXCNT]++;
471
472 /* Error-free Broadcast Frames counter */
473 if (!memcmp(packet, broadcast_addr, 6)) {
474 s->regs[GEM_RXBROADCNT]++;
475 }
476
477 /* Error-free Multicast Frames counter */
478 if (packet[0] == 0x01) {
479 s->regs[GEM_RXMULTICNT]++;
480 }
481
482 if (bytes <= 64) {
483 s->regs[GEM_RX64CNT]++;
484 } else if (bytes <= 127) {
485 s->regs[GEM_RX65CNT]++;
486 } else if (bytes <= 255) {
487 s->regs[GEM_RX128CNT]++;
488 } else if (bytes <= 511) {
489 s->regs[GEM_RX256CNT]++;
490 } else if (bytes <= 1023) {
491 s->regs[GEM_RX512CNT]++;
492 } else if (bytes <= 1518) {
493 s->regs[GEM_RX1024CNT]++;
494 } else {
495 s->regs[GEM_RX1519CNT]++;
496 }
497 }
498
499 /*
500 * Get the MAC Address bit from the specified position
501 */
502 static unsigned get_bit(const uint8_t *mac, unsigned bit)
503 {
504 unsigned byte;
505
506 byte = mac[bit / 8];
507 byte >>= (bit & 0x7);
508 byte &= 1;
509
510 return byte;
511 }
512
513 /*
514 * Calculate a GEM MAC Address hash index
515 */
516 static unsigned calc_mac_hash(const uint8_t *mac)
517 {
518 int index_bit, mac_bit;
519 unsigned hash_index;
520
521 hash_index = 0;
522 mac_bit = 5;
523 for (index_bit = 5; index_bit >= 0; index_bit--) {
524 hash_index |= (get_bit(mac, mac_bit) ^
525 get_bit(mac, mac_bit + 6) ^
526 get_bit(mac, mac_bit + 12) ^
527 get_bit(mac, mac_bit + 18) ^
528 get_bit(mac, mac_bit + 24) ^
529 get_bit(mac, mac_bit + 30) ^
530 get_bit(mac, mac_bit + 36) ^
531 get_bit(mac, mac_bit + 42)) << index_bit;
532 mac_bit--;
533 }
534
535 return hash_index;
536 }
537
538 /*
539 * gem_mac_address_filter:
540 * Accept or reject this destination address?
541 * Returns:
542 * GEM_RX_REJECT: reject
543 * >= 0: Specific address accept (which matched SAR is returned)
544 * others for various other modes of accept:
545 * GEM_RM_PROMISCUOUS_ACCEPT, GEM_RX_BROADCAST_ACCEPT,
546 * GEM_RX_MULTICAST_HASH_ACCEPT or GEM_RX_UNICAST_HASH_ACCEPT
547 */
548 static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t *packet)
549 {
550 uint8_t *gem_spaddr;
551 int i;
552
553 /* Promiscuous mode? */
554 if (s->regs[GEM_NWCFG] & GEM_NWCFG_PROMISC) {
555 return GEM_RX_PROMISCUOUS_ACCEPT;
556 }
557
558 if (!memcmp(packet, broadcast_addr, 6)) {
559 /* Reject broadcast packets? */
560 if (s->regs[GEM_NWCFG] & GEM_NWCFG_BCAST_REJ) {
561 return GEM_RX_REJECT;
562 }
563 return GEM_RX_BROADCAST_ACCEPT;
564 }
565
566 /* Accept packets -w- hash match? */
567 if ((packet[0] == 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_MCAST_HASH)) ||
568 (packet[0] != 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_UCAST_HASH))) {
569 unsigned hash_index;
570
571 hash_index = calc_mac_hash(packet);
572 if (hash_index < 32) {
573 if (s->regs[GEM_HASHLO] & (1<<hash_index)) {
574 return packet[0] == 0x01 ? GEM_RX_MULTICAST_HASH_ACCEPT :
575 GEM_RX_UNICAST_HASH_ACCEPT;
576 }
577 } else {
578 hash_index -= 32;
579 if (s->regs[GEM_HASHHI] & (1<<hash_index)) {
580 return packet[0] == 0x01 ? GEM_RX_MULTICAST_HASH_ACCEPT :
581 GEM_RX_UNICAST_HASH_ACCEPT;
582 }
583 }
584 }
585
586 /* Check all 4 specific addresses */
587 gem_spaddr = (uint8_t *)&(s->regs[GEM_SPADDR1LO]);
588 for (i = 3; i >= 0; i--) {
589 if (s->sar_active[i] && !memcmp(packet, gem_spaddr + 8 * i, 6)) {
590 return GEM_RX_SAR_ACCEPT + i;
591 }
592 }
593
594 /* No address match; reject the packet */
595 return GEM_RX_REJECT;
596 }
597
598 static void gem_get_rx_desc(CadenceGEMState *s)
599 {
600 DB_PRINT("read descriptor 0x%x\n", (unsigned)s->rx_desc_addr);
601 /* read current descriptor */
602 cpu_physical_memory_read(s->rx_desc_addr,
603 (uint8_t *)s->rx_desc, sizeof(s->rx_desc));
604
605 /* Descriptor owned by software ? */
606 if (rx_desc_get_ownership(s->rx_desc) == 1) {
607 DB_PRINT("descriptor 0x%x owned by sw.\n",
608 (unsigned)s->rx_desc_addr);
609 s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_NOBUF;
610 s->regs[GEM_ISR] |= GEM_INT_RXUSED & ~(s->regs[GEM_IMR]);
611 /* Handle interrupt consequences */
612 gem_update_int_status(s);
613 }
614 }
615
616 /*
617 * gem_receive:
618 * Fit a packet handed to us by QEMU into the receive descriptor ring.
619 */
620 static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
621 {
622 CadenceGEMState *s;
623 unsigned rxbufsize, bytes_to_copy;
624 unsigned rxbuf_offset;
625 uint8_t rxbuf[2048];
626 uint8_t *rxbuf_ptr;
627 bool first_desc = true;
628 int maf;
629
630 s = qemu_get_nic_opaque(nc);
631
632 /* Is this destination MAC address "for us" ? */
633 maf = gem_mac_address_filter(s, buf);
634 if (maf == GEM_RX_REJECT) {
635 return -1;
636 }
637
638 /* Discard packets with receive length error enabled ? */
639 if (s->regs[GEM_NWCFG] & GEM_NWCFG_LERR_DISC) {
640 unsigned type_len;
641
642 /* Fish the ethertype / length field out of the RX packet */
643 type_len = buf[12] << 8 | buf[13];
644 /* It is a length field, not an ethertype */
645 if (type_len < 0x600) {
646 if (size < type_len) {
647 /* discard */
648 return -1;
649 }
650 }
651 }
652
653 /*
654 * Determine configured receive buffer offset (probably 0)
655 */
656 rxbuf_offset = (s->regs[GEM_NWCFG] & GEM_NWCFG_BUFF_OFST_M) >>
657 GEM_NWCFG_BUFF_OFST_S;
658
659 /* The configure size of each receive buffer. Determines how many
660 * buffers needed to hold this packet.
661 */
662 rxbufsize = ((s->regs[GEM_DMACFG] & GEM_DMACFG_RBUFSZ_M) >>
663 GEM_DMACFG_RBUFSZ_S) * GEM_DMACFG_RBUFSZ_MUL;
664 bytes_to_copy = size;
665
666 /* Pad to minimum length. Assume FCS field is stripped, logic
667 * below will increment it to the real minimum of 64 when
668 * not FCS stripping
669 */
670 if (size < 60) {
671 size = 60;
672 }
673
674 /* Strip of FCS field ? (usually yes) */
675 if (s->regs[GEM_NWCFG] & GEM_NWCFG_STRIP_FCS) {
676 rxbuf_ptr = (void *)buf;
677 } else {
678 unsigned crc_val;
679
680 /* The application wants the FCS field, which QEMU does not provide.
681 * We must try and calculate one.
682 */
683
684 memcpy(rxbuf, buf, size);
685 memset(rxbuf + size, 0, sizeof(rxbuf) - size);
686 rxbuf_ptr = rxbuf;
687 crc_val = cpu_to_le32(crc32(0, rxbuf, MAX(size, 60)));
688 memcpy(rxbuf + size, &crc_val, sizeof(crc_val));
689
690 bytes_to_copy += 4;
691 size += 4;
692 }
693
694 DB_PRINT("config bufsize: %d packet size: %ld\n", rxbufsize, size);
695
696 while (bytes_to_copy) {
697 /* Do nothing if receive is not enabled. */
698 if (!gem_can_receive(nc)) {
699 assert(!first_desc);
700 return -1;
701 }
702
703 DB_PRINT("copy %d bytes to 0x%x\n", MIN(bytes_to_copy, rxbufsize),
704 rx_desc_get_buffer(s->rx_desc));
705
706 /* Copy packet data to emulated DMA buffer */
707 cpu_physical_memory_write(rx_desc_get_buffer(s->rx_desc) + rxbuf_offset,
708 rxbuf_ptr, MIN(bytes_to_copy, rxbufsize));
709 rxbuf_ptr += MIN(bytes_to_copy, rxbufsize);
710 bytes_to_copy -= MIN(bytes_to_copy, rxbufsize);
711
712 /* Update the descriptor. */
713 if (first_desc) {
714 rx_desc_set_sof(s->rx_desc);
715 first_desc = false;
716 }
717 if (bytes_to_copy == 0) {
718 rx_desc_set_eof(s->rx_desc);
719 rx_desc_set_length(s->rx_desc, size);
720 }
721 rx_desc_set_ownership(s->rx_desc);
722
723 switch (maf) {
724 case GEM_RX_PROMISCUOUS_ACCEPT:
725 break;
726 case GEM_RX_BROADCAST_ACCEPT:
727 rx_desc_set_broadcast(s->rx_desc);
728 break;
729 case GEM_RX_UNICAST_HASH_ACCEPT:
730 rx_desc_set_unicast_hash(s->rx_desc);
731 break;
732 case GEM_RX_MULTICAST_HASH_ACCEPT:
733 rx_desc_set_multicast_hash(s->rx_desc);
734 break;
735 case GEM_RX_REJECT:
736 abort();
737 default: /* SAR */
738 rx_desc_set_sar(s->rx_desc, maf);
739 }
740
741 /* Descriptor write-back. */
742 cpu_physical_memory_write(s->rx_desc_addr,
743 (uint8_t *)s->rx_desc, sizeof(s->rx_desc));
744
745 /* Next descriptor */
746 if (rx_desc_get_wrap(s->rx_desc)) {
747 DB_PRINT("wrapping RX descriptor list\n");
748 s->rx_desc_addr = s->regs[GEM_RXQBASE];
749 } else {
750 DB_PRINT("incrementing RX descriptor list\n");
751 s->rx_desc_addr += 8;
752 }
753 gem_get_rx_desc(s);
754 }
755
756 /* Count it */
757 gem_receive_updatestats(s, buf, size);
758
759 s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_FRMRCVD;
760 s->regs[GEM_ISR] |= GEM_INT_RXCMPL & ~(s->regs[GEM_IMR]);
761
762 /* Handle interrupt consequences */
763 gem_update_int_status(s);
764
765 return size;
766 }
767
768 /*
769 * gem_transmit_updatestats:
770 * Increment transmit statistics.
771 */
772 static void gem_transmit_updatestats(CadenceGEMState *s, const uint8_t *packet,
773 unsigned bytes)
774 {
775 uint64_t octets;
776
777 /* Total octets (bytes) transmitted */
778 octets = ((uint64_t)(s->regs[GEM_OCTTXLO]) << 32) |
779 s->regs[GEM_OCTTXHI];
780 octets += bytes;
781 s->regs[GEM_OCTTXLO] = octets >> 32;
782 s->regs[GEM_OCTTXHI] = octets;
783
784 /* Error-free Frames transmitted */
785 s->regs[GEM_TXCNT]++;
786
787 /* Error-free Broadcast Frames counter */
788 if (!memcmp(packet, broadcast_addr, 6)) {
789 s->regs[GEM_TXBCNT]++;
790 }
791
792 /* Error-free Multicast Frames counter */
793 if (packet[0] == 0x01) {
794 s->regs[GEM_TXMCNT]++;
795 }
796
797 if (bytes <= 64) {
798 s->regs[GEM_TX64CNT]++;
799 } else if (bytes <= 127) {
800 s->regs[GEM_TX65CNT]++;
801 } else if (bytes <= 255) {
802 s->regs[GEM_TX128CNT]++;
803 } else if (bytes <= 511) {
804 s->regs[GEM_TX256CNT]++;
805 } else if (bytes <= 1023) {
806 s->regs[GEM_TX512CNT]++;
807 } else if (bytes <= 1518) {
808 s->regs[GEM_TX1024CNT]++;
809 } else {
810 s->regs[GEM_TX1519CNT]++;
811 }
812 }
813
814 /*
815 * gem_transmit:
816 * Fish packets out of the descriptor ring and feed them to QEMU
817 */
818 static void gem_transmit(CadenceGEMState *s)
819 {
820 unsigned desc[2];
821 hwaddr packet_desc_addr;
822 uint8_t tx_packet[2048];
823 uint8_t *p;
824 unsigned total_bytes;
825
826 /* Do nothing if transmit is not enabled. */
827 if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) {
828 return;
829 }
830
831 DB_PRINT("\n");
832
833 /* The packet we will hand off to QEMU.
834 * Packets scattered across multiple descriptors are gathered to this
835 * one contiguous buffer first.
836 */
837 p = tx_packet;
838 total_bytes = 0;
839
840 /* read current descriptor */
841 packet_desc_addr = s->tx_desc_addr;
842
843 DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr);
844 cpu_physical_memory_read(packet_desc_addr,
845 (uint8_t *)desc, sizeof(desc));
846 /* Handle all descriptors owned by hardware */
847 while (tx_desc_get_used(desc) == 0) {
848
849 /* Do nothing if transmit is not enabled. */
850 if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) {
851 return;
852 }
853 print_gem_tx_desc(desc);
854
855 /* The real hardware would eat this (and possibly crash).
856 * For QEMU let's lend a helping hand.
857 */
858 if ((tx_desc_get_buffer(desc) == 0) ||
859 (tx_desc_get_length(desc) == 0)) {
860 DB_PRINT("Invalid TX descriptor @ 0x%x\n",
861 (unsigned)packet_desc_addr);
862 break;
863 }
864
865 /* Gather this fragment of the packet from "dma memory" to our contig.
866 * buffer.
867 */
868 cpu_physical_memory_read(tx_desc_get_buffer(desc), p,
869 tx_desc_get_length(desc));
870 p += tx_desc_get_length(desc);
871 total_bytes += tx_desc_get_length(desc);
872
873 /* Last descriptor for this packet; hand the whole thing off */
874 if (tx_desc_get_last(desc)) {
875 unsigned desc_first[2];
876
877 /* Modify the 1st descriptor of this packet to be owned by
878 * the processor.
879 */
880 cpu_physical_memory_read(s->tx_desc_addr, (uint8_t *)desc_first,
881 sizeof(desc_first));
882 tx_desc_set_used(desc_first);
883 cpu_physical_memory_write(s->tx_desc_addr, (uint8_t *)desc_first,
884 sizeof(desc_first));
885 /* Advance the hardware current descriptor past this packet */
886 if (tx_desc_get_wrap(desc)) {
887 s->tx_desc_addr = s->regs[GEM_TXQBASE];
888 } else {
889 s->tx_desc_addr = packet_desc_addr + 8;
890 }
891 DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr);
892
893 s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_TXCMPL;
894 s->regs[GEM_ISR] |= GEM_INT_TXCMPL & ~(s->regs[GEM_IMR]);
895
896 /* Handle interrupt consequences */
897 gem_update_int_status(s);
898
899 /* Is checksum offload enabled? */
900 if (s->regs[GEM_DMACFG] & GEM_DMACFG_TXCSUM_OFFL) {
901 net_checksum_calculate(tx_packet, total_bytes);
902 }
903
904 /* Update MAC statistics */
905 gem_transmit_updatestats(s, tx_packet, total_bytes);
906
907 /* Send the packet somewhere */
908 if (s->phy_loop || (s->regs[GEM_NWCTRL] & GEM_NWCTRL_LOCALLOOP)) {
909 gem_receive(qemu_get_queue(s->nic), tx_packet, total_bytes);
910 } else {
911 qemu_send_packet(qemu_get_queue(s->nic), tx_packet,
912 total_bytes);
913 }
914
915 /* Prepare for next packet */
916 p = tx_packet;
917 total_bytes = 0;
918 }
919
920 /* read next descriptor */
921 if (tx_desc_get_wrap(desc)) {
922 packet_desc_addr = s->regs[GEM_TXQBASE];
923 } else {
924 packet_desc_addr += 8;
925 }
926 DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr);
927 cpu_physical_memory_read(packet_desc_addr,
928 (uint8_t *)desc, sizeof(desc));
929 }
930
931 if (tx_desc_get_used(desc)) {
932 s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_USED;
933 s->regs[GEM_ISR] |= GEM_INT_TXUSED & ~(s->regs[GEM_IMR]);
934 gem_update_int_status(s);
935 }
936 }
937
938 static void gem_phy_reset(CadenceGEMState *s)
939 {
940 memset(&s->phy_regs[0], 0, sizeof(s->phy_regs));
941 s->phy_regs[PHY_REG_CONTROL] = 0x1140;
942 s->phy_regs[PHY_REG_STATUS] = 0x7969;
943 s->phy_regs[PHY_REG_PHYID1] = 0x0141;
944 s->phy_regs[PHY_REG_PHYID2] = 0x0CC2;
945 s->phy_regs[PHY_REG_ANEGADV] = 0x01E1;
946 s->phy_regs[PHY_REG_LINKPABIL] = 0xCDE1;
947 s->phy_regs[PHY_REG_ANEGEXP] = 0x000F;
948 s->phy_regs[PHY_REG_NEXTP] = 0x2001;
949 s->phy_regs[PHY_REG_LINKPNEXTP] = 0x40E6;
950 s->phy_regs[PHY_REG_100BTCTRL] = 0x0300;
951 s->phy_regs[PHY_REG_1000BTSTAT] = 0x7C00;
952 s->phy_regs[PHY_REG_EXTSTAT] = 0x3000;
953 s->phy_regs[PHY_REG_PHYSPCFC_CTL] = 0x0078;
954 s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0xBC00;
955 s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL] = 0x0C60;
956 s->phy_regs[PHY_REG_LED] = 0x4100;
957 s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL2] = 0x000A;
958 s->phy_regs[PHY_REG_EXT_PHYSPCFC_ST] = 0x848B;
959
960 phy_update_link(s);
961 }
962
963 static void gem_reset(DeviceState *d)
964 {
965 int i;
966 CadenceGEMState *s = CADENCE_GEM(d);
967
968 DB_PRINT("\n");
969
970 /* Set post reset register values */
971 memset(&s->regs[0], 0, sizeof(s->regs));
972 s->regs[GEM_NWCFG] = 0x00080000;
973 s->regs[GEM_NWSTATUS] = 0x00000006;
974 s->regs[GEM_DMACFG] = 0x00020784;
975 s->regs[GEM_IMR] = 0x07ffffff;
976 s->regs[GEM_TXPAUSE] = 0x0000ffff;
977 s->regs[GEM_TXPARTIALSF] = 0x000003ff;
978 s->regs[GEM_RXPARTIALSF] = 0x000003ff;
979 s->regs[GEM_MODID] = 0x00020118;
980 s->regs[GEM_DESCONF] = 0x02500111;
981 s->regs[GEM_DESCONF2] = 0x2ab13fff;
982 s->regs[GEM_DESCONF5] = 0x002f2145;
983 s->regs[GEM_DESCONF6] = 0x00000200;
984
985 for (i = 0; i < 4; i++) {
986 s->sar_active[i] = false;
987 }
988
989 gem_phy_reset(s);
990
991 gem_update_int_status(s);
992 }
993
994 static uint16_t gem_phy_read(CadenceGEMState *s, unsigned reg_num)
995 {
996 DB_PRINT("reg: %d value: 0x%04x\n", reg_num, s->phy_regs[reg_num]);
997 return s->phy_regs[reg_num];
998 }
999
1000 static void gem_phy_write(CadenceGEMState *s, unsigned reg_num, uint16_t val)
1001 {
1002 DB_PRINT("reg: %d value: 0x%04x\n", reg_num, val);
1003
1004 switch (reg_num) {
1005 case PHY_REG_CONTROL:
1006 if (val & PHY_REG_CONTROL_RST) {
1007 /* Phy reset */
1008 gem_phy_reset(s);
1009 val &= ~(PHY_REG_CONTROL_RST | PHY_REG_CONTROL_LOOP);
1010 s->phy_loop = 0;
1011 }
1012 if (val & PHY_REG_CONTROL_ANEG) {
1013 /* Complete autonegotiation immediately */
1014 val &= ~PHY_REG_CONTROL_ANEG;
1015 s->phy_regs[PHY_REG_STATUS] |= PHY_REG_STATUS_ANEGCMPL;
1016 }
1017 if (val & PHY_REG_CONTROL_LOOP) {
1018 DB_PRINT("PHY placed in loopback\n");
1019 s->phy_loop = 1;
1020 } else {
1021 s->phy_loop = 0;
1022 }
1023 break;
1024 }
1025 s->phy_regs[reg_num] = val;
1026 }
1027
1028 /*
1029 * gem_read32:
1030 * Read a GEM register.
1031 */
1032 static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
1033 {
1034 CadenceGEMState *s;
1035 uint32_t retval;
1036
1037 s = (CadenceGEMState *)opaque;
1038
1039 offset >>= 2;
1040 retval = s->regs[offset];
1041
1042 DB_PRINT("offset: 0x%04x read: 0x%08x\n", (unsigned)offset*4, retval);
1043
1044 switch (offset) {
1045 case GEM_ISR:
1046 DB_PRINT("lowering irq on ISR read\n");
1047 qemu_set_irq(s->irq, 0);
1048 break;
1049 case GEM_PHYMNTNC:
1050 if (retval & GEM_PHYMNTNC_OP_R) {
1051 uint32_t phy_addr, reg_num;
1052
1053 phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
1054 if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) {
1055 reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
1056 retval &= 0xFFFF0000;
1057 retval |= gem_phy_read(s, reg_num);
1058 } else {
1059 retval |= 0xFFFF; /* No device at this address */
1060 }
1061 }
1062 break;
1063 }
1064
1065 /* Squash read to clear bits */
1066 s->regs[offset] &= ~(s->regs_rtc[offset]);
1067
1068 /* Do not provide write only bits */
1069 retval &= ~(s->regs_wo[offset]);
1070
1071 DB_PRINT("0x%08x\n", retval);
1072 return retval;
1073 }
1074
1075 /*
1076 * gem_write32:
1077 * Write a GEM register.
1078 */
1079 static void gem_write(void *opaque, hwaddr offset, uint64_t val,
1080 unsigned size)
1081 {
1082 CadenceGEMState *s = (CadenceGEMState *)opaque;
1083 uint32_t readonly;
1084
1085 DB_PRINT("offset: 0x%04x write: 0x%08x ", (unsigned)offset, (unsigned)val);
1086 offset >>= 2;
1087
1088 /* Squash bits which are read only in write value */
1089 val &= ~(s->regs_ro[offset]);
1090 /* Preserve (only) bits which are read only and wtc in register */
1091 readonly = s->regs[offset] & (s->regs_ro[offset] | s->regs_w1c[offset]);
1092
1093 /* Copy register write to backing store */
1094 s->regs[offset] = (val & ~s->regs_w1c[offset]) | readonly;
1095
1096 /* do w1c */
1097 s->regs[offset] &= ~(s->regs_w1c[offset] & val);
1098
1099 /* Handle register write side effects */
1100 switch (offset) {
1101 case GEM_NWCTRL:
1102 if (val & GEM_NWCTRL_RXENA) {
1103 gem_get_rx_desc(s);
1104 }
1105 if (val & GEM_NWCTRL_TXSTART) {
1106 gem_transmit(s);
1107 }
1108 if (!(val & GEM_NWCTRL_TXENA)) {
1109 /* Reset to start of Q when transmit disabled. */
1110 s->tx_desc_addr = s->regs[GEM_TXQBASE];
1111 }
1112 if (gem_can_receive(qemu_get_queue(s->nic))) {
1113 qemu_flush_queued_packets(qemu_get_queue(s->nic));
1114 }
1115 break;
1116
1117 case GEM_TXSTATUS:
1118 gem_update_int_status(s);
1119 break;
1120 case GEM_RXQBASE:
1121 s->rx_desc_addr = val;
1122 break;
1123 case GEM_TXQBASE:
1124 s->tx_desc_addr = val;
1125 break;
1126 case GEM_RXSTATUS:
1127 gem_update_int_status(s);
1128 break;
1129 case GEM_IER:
1130 s->regs[GEM_IMR] &= ~val;
1131 gem_update_int_status(s);
1132 break;
1133 case GEM_IDR:
1134 s->regs[GEM_IMR] |= val;
1135 gem_update_int_status(s);
1136 break;
1137 case GEM_SPADDR1LO:
1138 case GEM_SPADDR2LO:
1139 case GEM_SPADDR3LO:
1140 case GEM_SPADDR4LO:
1141 s->sar_active[(offset - GEM_SPADDR1LO) / 2] = false;
1142 break;
1143 case GEM_SPADDR1HI:
1144 case GEM_SPADDR2HI:
1145 case GEM_SPADDR3HI:
1146 case GEM_SPADDR4HI:
1147 s->sar_active[(offset - GEM_SPADDR1HI) / 2] = true;
1148 break;
1149 case GEM_PHYMNTNC:
1150 if (val & GEM_PHYMNTNC_OP_W) {
1151 uint32_t phy_addr, reg_num;
1152
1153 phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
1154 if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) {
1155 reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
1156 gem_phy_write(s, reg_num, val);
1157 }
1158 }
1159 break;
1160 }
1161
1162 DB_PRINT("newval: 0x%08x\n", s->regs[offset]);
1163 }
1164
1165 static const MemoryRegionOps gem_ops = {
1166 .read = gem_read,
1167 .write = gem_write,
1168 .endianness = DEVICE_LITTLE_ENDIAN,
1169 };
1170
1171 static void gem_set_link(NetClientState *nc)
1172 {
1173 DB_PRINT("\n");
1174 phy_update_link(qemu_get_nic_opaque(nc));
1175 }
1176
1177 static NetClientInfo net_gem_info = {
1178 .type = NET_CLIENT_OPTIONS_KIND_NIC,
1179 .size = sizeof(NICState),
1180 .can_receive = gem_can_receive,
1181 .receive = gem_receive,
1182 .link_status_changed = gem_set_link,
1183 };
1184
1185 static int gem_init(SysBusDevice *sbd)
1186 {
1187 DeviceState *dev = DEVICE(sbd);
1188 CadenceGEMState *s = CADENCE_GEM(dev);
1189
1190 DB_PRINT("\n");
1191
1192 gem_init_register_masks(s);
1193 memory_region_init_io(&s->iomem, OBJECT(s), &gem_ops, s,
1194 "enet", sizeof(s->regs));
1195 sysbus_init_mmio(sbd, &s->iomem);
1196 sysbus_init_irq(sbd, &s->irq);
1197 qemu_macaddr_default_if_unset(&s->conf.macaddr);
1198
1199 s->nic = qemu_new_nic(&net_gem_info, &s->conf,
1200 object_get_typename(OBJECT(dev)), dev->id, s);
1201
1202 return 0;
1203 }
1204
1205 static const VMStateDescription vmstate_cadence_gem = {
1206 .name = "cadence_gem",
1207 .version_id = 2,
1208 .minimum_version_id = 2,
1209 .fields = (VMStateField[]) {
1210 VMSTATE_UINT32_ARRAY(regs, CadenceGEMState, CADENCE_GEM_MAXREG),
1211 VMSTATE_UINT16_ARRAY(phy_regs, CadenceGEMState, 32),
1212 VMSTATE_UINT8(phy_loop, CadenceGEMState),
1213 VMSTATE_UINT32(rx_desc_addr, CadenceGEMState),
1214 VMSTATE_UINT32(tx_desc_addr, CadenceGEMState),
1215 VMSTATE_BOOL_ARRAY(sar_active, CadenceGEMState, 4),
1216 VMSTATE_END_OF_LIST(),
1217 }
1218 };
1219
1220 static Property gem_properties[] = {
1221 DEFINE_NIC_PROPERTIES(CadenceGEMState, conf),
1222 DEFINE_PROP_END_OF_LIST(),
1223 };
1224
1225 static void gem_class_init(ObjectClass *klass, void *data)
1226 {
1227 DeviceClass *dc = DEVICE_CLASS(klass);
1228 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
1229
1230 sdc->init = gem_init;
1231 dc->props = gem_properties;
1232 dc->vmsd = &vmstate_cadence_gem;
1233 dc->reset = gem_reset;
1234 }
1235
1236 static const TypeInfo gem_info = {
1237 .name = TYPE_CADENCE_GEM,
1238 .parent = TYPE_SYS_BUS_DEVICE,
1239 .instance_size = sizeof(CadenceGEMState),
1240 .class_init = gem_class_init,
1241 };
1242
1243 static void gem_register_types(void)
1244 {
1245 type_register_static(&gem_info);
1246 }
1247
1248 type_init(gem_register_types)
AR7 emulation for QEMU