hw/misc/edu: Convert to realize()
[qemu/ar7.git] / hw / intc / apic_common.c
blobad959c4e77616e27f3a6481afa78cd014bd9aaba
1 /*
2 * APIC support - common bits of emulated and KVM kernel model
4 * Copyright (c) 2004-2005 Fabrice Bellard
5 * Copyright (c) 2011 Jan Kiszka, Siemens AG
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>
20 #include "hw/i386/apic.h"
21 #include "hw/i386/apic_internal.h"
22 #include "trace.h"
23 #include "sysemu/kvm.h"
24 #include "hw/qdev.h"
25 #include "hw/sysbus.h"
27 static int apic_irq_delivered;
28 bool apic_report_tpr_access;
30 void cpu_set_apic_base(DeviceState *dev, uint64_t val)
32 trace_cpu_set_apic_base(val);
34 if (dev) {
35 APICCommonState *s = APIC_COMMON(dev);
36 APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
37 info->set_base(s, val);
41 uint64_t cpu_get_apic_base(DeviceState *dev)
43 if (dev) {
44 APICCommonState *s = APIC_COMMON(dev);
45 trace_cpu_get_apic_base((uint64_t)s->apicbase);
46 return s->apicbase;
47 } else {
48 trace_cpu_get_apic_base(MSR_IA32_APICBASE_BSP);
49 return MSR_IA32_APICBASE_BSP;
53 void cpu_set_apic_tpr(DeviceState *dev, uint8_t val)
55 APICCommonState *s;
56 APICCommonClass *info;
58 if (!dev) {
59 return;
62 s = APIC_COMMON(dev);
63 info = APIC_COMMON_GET_CLASS(s);
65 info->set_tpr(s, val);
68 uint8_t cpu_get_apic_tpr(DeviceState *dev)
70 APICCommonState *s;
71 APICCommonClass *info;
73 if (!dev) {
74 return 0;
77 s = APIC_COMMON(dev);
78 info = APIC_COMMON_GET_CLASS(s);
80 return info->get_tpr(s);
83 void apic_enable_tpr_access_reporting(DeviceState *dev, bool enable)
85 APICCommonState *s = APIC_COMMON(dev);
86 APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
88 apic_report_tpr_access = enable;
89 if (info->enable_tpr_reporting) {
90 info->enable_tpr_reporting(s, enable);
94 void apic_enable_vapic(DeviceState *dev, hwaddr paddr)
96 APICCommonState *s = APIC_COMMON(dev);
97 APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
99 s->vapic_paddr = paddr;
100 info->vapic_base_update(s);
103 void apic_handle_tpr_access_report(DeviceState *dev, target_ulong ip,
104 TPRAccess access)
106 APICCommonState *s = APIC_COMMON(dev);
108 vapic_report_tpr_access(s->vapic, CPU(s->cpu), ip, access);
111 void apic_report_irq_delivered(int delivered)
113 apic_irq_delivered += delivered;
115 trace_apic_report_irq_delivered(apic_irq_delivered);
118 void apic_reset_irq_delivered(void)
120 /* Copy this into a local variable to encourage gcc to emit a plain
121 * register for a sys/sdt.h marker. For details on this workaround, see:
122 * https://sourceware.org/bugzilla/show_bug.cgi?id=13296
124 volatile int a_i_d = apic_irq_delivered;
125 trace_apic_reset_irq_delivered(a_i_d);
127 apic_irq_delivered = 0;
130 int apic_get_irq_delivered(void)
132 trace_apic_get_irq_delivered(apic_irq_delivered);
134 return apic_irq_delivered;
137 void apic_deliver_nmi(DeviceState *dev)
139 APICCommonState *s = APIC_COMMON(dev);
140 APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
142 info->external_nmi(s);
145 bool apic_next_timer(APICCommonState *s, int64_t current_time)
147 int64_t d;
149 /* We need to store the timer state separately to support APIC
150 * implementations that maintain a non-QEMU timer, e.g. inside the
151 * host kernel. This open-coded state allows us to migrate between
152 * both models. */
153 s->timer_expiry = -1;
155 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED) {
156 return false;
159 d = (current_time - s->initial_count_load_time) >> s->count_shift;
161 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
162 if (!s->initial_count) {
163 return false;
165 d = ((d / ((uint64_t)s->initial_count + 1)) + 1) *
166 ((uint64_t)s->initial_count + 1);
167 } else {
168 if (d >= s->initial_count) {
169 return false;
171 d = (uint64_t)s->initial_count + 1;
173 s->next_time = s->initial_count_load_time + (d << s->count_shift);
174 s->timer_expiry = s->next_time;
175 return true;
178 void apic_init_reset(DeviceState *dev)
180 APICCommonState *s;
181 APICCommonClass *info;
182 int i;
184 if (!dev) {
185 return;
187 s = APIC_COMMON(dev);
188 s->tpr = 0;
189 s->spurious_vec = 0xff;
190 s->log_dest = 0;
191 s->dest_mode = 0xf;
192 memset(s->isr, 0, sizeof(s->isr));
193 memset(s->tmr, 0, sizeof(s->tmr));
194 memset(s->irr, 0, sizeof(s->irr));
195 for (i = 0; i < APIC_LVT_NB; i++) {
196 s->lvt[i] = APIC_LVT_MASKED;
198 s->esr = 0;
199 memset(s->icr, 0, sizeof(s->icr));
200 s->divide_conf = 0;
201 s->count_shift = 0;
202 s->initial_count = 0;
203 s->initial_count_load_time = 0;
204 s->next_time = 0;
205 s->wait_for_sipi = !cpu_is_bsp(s->cpu);
207 if (s->timer) {
208 timer_del(s->timer);
210 s->timer_expiry = -1;
212 info = APIC_COMMON_GET_CLASS(s);
213 if (info->reset) {
214 info->reset(s);
218 void apic_designate_bsp(DeviceState *dev, bool bsp)
220 if (dev == NULL) {
221 return;
224 APICCommonState *s = APIC_COMMON(dev);
225 if (bsp) {
226 s->apicbase |= MSR_IA32_APICBASE_BSP;
227 } else {
228 s->apicbase &= ~MSR_IA32_APICBASE_BSP;
232 static void apic_reset_common(DeviceState *dev)
234 APICCommonState *s = APIC_COMMON(dev);
235 APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
236 uint32_t bsp;
238 bsp = s->apicbase & MSR_IA32_APICBASE_BSP;
239 s->apicbase = APIC_DEFAULT_ADDRESS | bsp | MSR_IA32_APICBASE_ENABLE;
241 s->vapic_paddr = 0;
242 info->vapic_base_update(s);
244 apic_init_reset(dev);
247 /* This function is only used for old state version 1 and 2 */
248 static int apic_load_old(QEMUFile *f, void *opaque, int version_id)
250 APICCommonState *s = opaque;
251 APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
252 int i;
254 if (version_id > 2) {
255 return -EINVAL;
258 /* XXX: what if the base changes? (registered memory regions) */
259 qemu_get_be32s(f, &s->apicbase);
260 qemu_get_8s(f, &s->id);
261 qemu_get_8s(f, &s->arb_id);
262 qemu_get_8s(f, &s->tpr);
263 qemu_get_be32s(f, &s->spurious_vec);
264 qemu_get_8s(f, &s->log_dest);
265 qemu_get_8s(f, &s->dest_mode);
266 for (i = 0; i < 8; i++) {
267 qemu_get_be32s(f, &s->isr[i]);
268 qemu_get_be32s(f, &s->tmr[i]);
269 qemu_get_be32s(f, &s->irr[i]);
271 for (i = 0; i < APIC_LVT_NB; i++) {
272 qemu_get_be32s(f, &s->lvt[i]);
274 qemu_get_be32s(f, &s->esr);
275 qemu_get_be32s(f, &s->icr[0]);
276 qemu_get_be32s(f, &s->icr[1]);
277 qemu_get_be32s(f, &s->divide_conf);
278 s->count_shift = qemu_get_be32(f);
279 qemu_get_be32s(f, &s->initial_count);
280 s->initial_count_load_time = qemu_get_be64(f);
281 s->next_time = qemu_get_be64(f);
283 if (version_id >= 2) {
284 s->timer_expiry = qemu_get_be64(f);
287 if (info->post_load) {
288 info->post_load(s);
290 return 0;
293 static void apic_common_realize(DeviceState *dev, Error **errp)
295 APICCommonState *s = APIC_COMMON(dev);
296 APICCommonClass *info;
297 static DeviceState *vapic;
298 static int apic_no;
300 if (apic_no >= MAX_APICS) {
301 error_setg(errp, "%s initialization failed.",
302 object_get_typename(OBJECT(dev)));
303 return;
305 s->idx = apic_no++;
307 info = APIC_COMMON_GET_CLASS(s);
308 info->realize(dev, errp);
310 /* Note: We need at least 1M to map the VAPIC option ROM */
311 if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK &&
312 ram_size >= 1024 * 1024) {
313 vapic = sysbus_create_simple("kvmvapic", -1, NULL);
315 s->vapic = vapic;
316 if (apic_report_tpr_access && info->enable_tpr_reporting) {
317 info->enable_tpr_reporting(s, true);
322 static int apic_pre_load(void *opaque)
324 APICCommonState *s = APIC_COMMON(opaque);
326 /* The default is !cpu_is_bsp(s->cpu), but the common value is 0
327 * so that's what apic_common_sipi_needed checks for. Reset to
328 * the value that is assumed when the apic_sipi subsection is
329 * absent.
331 s->wait_for_sipi = 0;
332 return 0;
335 static void apic_dispatch_pre_save(void *opaque)
337 APICCommonState *s = APIC_COMMON(opaque);
338 APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
340 if (info->pre_save) {
341 info->pre_save(s);
345 static int apic_dispatch_post_load(void *opaque, int version_id)
347 APICCommonState *s = APIC_COMMON(opaque);
348 APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
350 if (info->post_load) {
351 info->post_load(s);
353 return 0;
356 static bool apic_common_sipi_needed(void *opaque)
358 APICCommonState *s = APIC_COMMON(opaque);
359 return s->wait_for_sipi != 0;
362 static const VMStateDescription vmstate_apic_common_sipi = {
363 .name = "apic_sipi",
364 .version_id = 1,
365 .minimum_version_id = 1,
366 .needed = apic_common_sipi_needed,
367 .fields = (VMStateField[]) {
368 VMSTATE_INT32(sipi_vector, APICCommonState),
369 VMSTATE_INT32(wait_for_sipi, APICCommonState),
370 VMSTATE_END_OF_LIST()
374 static const VMStateDescription vmstate_apic_common = {
375 .name = "apic",
376 .version_id = 3,
377 .minimum_version_id = 3,
378 .minimum_version_id_old = 1,
379 .load_state_old = apic_load_old,
380 .pre_load = apic_pre_load,
381 .pre_save = apic_dispatch_pre_save,
382 .post_load = apic_dispatch_post_load,
383 .fields = (VMStateField[]) {
384 VMSTATE_UINT32(apicbase, APICCommonState),
385 VMSTATE_UINT8(id, APICCommonState),
386 VMSTATE_UINT8(arb_id, APICCommonState),
387 VMSTATE_UINT8(tpr, APICCommonState),
388 VMSTATE_UINT32(spurious_vec, APICCommonState),
389 VMSTATE_UINT8(log_dest, APICCommonState),
390 VMSTATE_UINT8(dest_mode, APICCommonState),
391 VMSTATE_UINT32_ARRAY(isr, APICCommonState, 8),
392 VMSTATE_UINT32_ARRAY(tmr, APICCommonState, 8),
393 VMSTATE_UINT32_ARRAY(irr, APICCommonState, 8),
394 VMSTATE_UINT32_ARRAY(lvt, APICCommonState, APIC_LVT_NB),
395 VMSTATE_UINT32(esr, APICCommonState),
396 VMSTATE_UINT32_ARRAY(icr, APICCommonState, 2),
397 VMSTATE_UINT32(divide_conf, APICCommonState),
398 VMSTATE_INT32(count_shift, APICCommonState),
399 VMSTATE_UINT32(initial_count, APICCommonState),
400 VMSTATE_INT64(initial_count_load_time, APICCommonState),
401 VMSTATE_INT64(next_time, APICCommonState),
402 VMSTATE_INT64(timer_expiry,
403 APICCommonState), /* open-coded timer state */
404 VMSTATE_END_OF_LIST()
406 .subsections = (const VMStateDescription*[]) {
407 &vmstate_apic_common_sipi,
408 NULL
412 static Property apic_properties_common[] = {
413 DEFINE_PROP_UINT8("id", APICCommonState, id, -1),
414 DEFINE_PROP_UINT8("version", APICCommonState, version, 0x14),
415 DEFINE_PROP_BIT("vapic", APICCommonState, vapic_control, VAPIC_ENABLE_BIT,
416 true),
417 DEFINE_PROP_END_OF_LIST(),
420 static void apic_common_class_init(ObjectClass *klass, void *data)
422 DeviceClass *dc = DEVICE_CLASS(klass);
424 dc->vmsd = &vmstate_apic_common;
425 dc->reset = apic_reset_common;
426 dc->props = apic_properties_common;
427 dc->realize = apic_common_realize;
429 * Reason: APIC and CPU need to be wired up by
430 * x86_cpu_apic_create()
432 dc->cannot_instantiate_with_device_add_yet = true;
435 static const TypeInfo apic_common_type = {
436 .name = TYPE_APIC_COMMON,
437 .parent = TYPE_DEVICE,
438 .instance_size = sizeof(APICCommonState),
439 .class_size = sizeof(APICCommonClass),
440 .class_init = apic_common_class_init,
441 .abstract = true,
444 static void apic_common_register_types(void)
446 type_register_static(&apic_common_type);
449 type_init(apic_common_register_types)