hw/intc/apic_common.c

   1 /*
   2  *  APIC support - common bits of emulated and KVM kernel model
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *  Copyright (c) 2011      Jan Kiszka, Siemens AG
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2.1 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qemu/error-report.h"
  23 #include "qemu/module.h"
  24 #include "qapi/error.h"
  25 #include "qapi/visitor.h"
  26 #include "hw/i386/apic.h"
  27 #include "hw/i386/apic_internal.h"
  28 #include "hw/intc/kvm_irqcount.h"
  29 #include "trace.h"
  30 #include "hw/boards.h"
  31 #include "sysemu/kvm.h"
  32 #include "hw/qdev-properties.h"
  33 #include "hw/sysbus.h"
  34 #include "migration/vmstate.h"
  35
  36 bool apic_report_tpr_access;
  37
  38 int cpu_set_apic_base(DeviceState *dev, uint64_t val)
  39 {
  40     trace_cpu_set_apic_base(val);
  41
  42     if (dev) {
  43         APICCommonState *s = APIC_COMMON(dev);
  44         APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
  45         /* Reset possibly modified xAPIC ID */
  46         s->id = s->initial_apic_id;
  47         return info->set_base(s, val);
  48     }
  49
  50     return 0;
  51 }
  52
  53 uint64_t cpu_get_apic_base(DeviceState *dev)
  54 {
  55     if (dev) {
  56         APICCommonState *s = APIC_COMMON(dev);
  57         trace_cpu_get_apic_base((uint64_t)s->apicbase);
  58         return s->apicbase;
  59     } else {
  60         trace_cpu_get_apic_base(MSR_IA32_APICBASE_BSP);
  61         return MSR_IA32_APICBASE_BSP;
  62     }
  63 }
  64
  65 bool cpu_is_apic_enabled(DeviceState *dev)
  66 {
  67     APICCommonState *s;
  68
  69     if (!dev) {
  70         return false;
  71     }
  72
  73     s = APIC_COMMON(dev);
  74
  75     return s->apicbase & MSR_IA32_APICBASE_ENABLE;
  76 }
  77
  78 void cpu_set_apic_tpr(DeviceState *dev, uint8_t val)
  79 {
  80     APICCommonState *s;
  81     APICCommonClass *info;
  82
  83     if (!dev) {
  84         return;
  85     }
  86
  87     s = APIC_COMMON(dev);
  88     info = APIC_COMMON_GET_CLASS(s);
  89
  90     info->set_tpr(s, val);
  91 }
  92
  93 uint8_t cpu_get_apic_tpr(DeviceState *dev)
  94 {
  95     APICCommonState *s;
  96     APICCommonClass *info;
  97
  98     if (!dev) {
  99         return 0;
 100     }
 101
 102     s = APIC_COMMON(dev);
 103     info = APIC_COMMON_GET_CLASS(s);
 104
 105     return info->get_tpr(s);
 106 }
 107
 108 void apic_enable_tpr_access_reporting(DeviceState *dev, bool enable)
 109 {
 110     APICCommonState *s = APIC_COMMON(dev);
 111     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 112
 113     apic_report_tpr_access = enable;
 114     if (info->enable_tpr_reporting) {
 115         info->enable_tpr_reporting(s, enable);
 116     }
 117 }
 118
 119 void apic_enable_vapic(DeviceState *dev, hwaddr paddr)
 120 {
 121     APICCommonState *s = APIC_COMMON(dev);
 122     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 123
 124     s->vapic_paddr = paddr;
 125     info->vapic_base_update(s);
 126 }
 127
 128 void apic_handle_tpr_access_report(DeviceState *dev, target_ulong ip,
 129                                    TPRAccess access)
 130 {
 131     APICCommonState *s = APIC_COMMON(dev);
 132
 133     vapic_report_tpr_access(s->vapic, CPU(s->cpu), ip, access);
 134 }
 135
 136 void apic_deliver_nmi(DeviceState *dev)
 137 {
 138     APICCommonState *s = APIC_COMMON(dev);
 139     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 140
 141     info->external_nmi(s);
 142 }
 143
 144 bool apic_next_timer(APICCommonState *s, int64_t current_time)
 145 {
 146     int64_t d;
 147
 148     /* We need to store the timer state separately to support APIC
 149      * implementations that maintain a non-QEMU timer, e.g. inside the
 150      * host kernel. This open-coded state allows us to migrate between
 151      * both models. */
 152     s->timer_expiry = -1;
 153
 154     if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED) {
 155         return false;
 156     }
 157
 158     d = (current_time - s->initial_count_load_time) >> s->count_shift;
 159
 160     if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 161         if (!s->initial_count) {
 162             return false;
 163         }
 164         d = ((d / ((uint64_t)s->initial_count + 1)) + 1) *
 165             ((uint64_t)s->initial_count + 1);
 166     } else {
 167         if (d >= s->initial_count) {
 168             return false;
 169         }
 170         d = (uint64_t)s->initial_count + 1;
 171     }
 172     s->next_time = s->initial_count_load_time + (d << s->count_shift);
 173     s->timer_expiry = s->next_time;
 174     return true;
 175 }
 176
 177 uint32_t apic_get_current_count(APICCommonState *s)
 178 {
 179     int64_t d;
 180     uint32_t val;
 181     d = (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->initial_count_load_time) >>
 182         s->count_shift;
 183     if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 184         /* periodic */
 185         val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
 186     } else {
 187         if (d >= s->initial_count) {
 188             val = 0;
 189         } else {
 190             val = s->initial_count - d;
 191         }
 192     }
 193     return val;
 194 }
 195
 196 void apic_init_reset(DeviceState *dev)
 197 {
 198     APICCommonState *s;
 199     APICCommonClass *info;
 200     int i;
 201
 202     if (!dev) {
 203         return;
 204     }
 205     s = APIC_COMMON(dev);
 206     s->tpr = 0;
 207     s->spurious_vec = 0xff;
 208     s->log_dest = 0;
 209     s->dest_mode = 0xf;
 210     memset(s->isr, 0, sizeof(s->isr));
 211     memset(s->tmr, 0, sizeof(s->tmr));
 212     memset(s->irr, 0, sizeof(s->irr));
 213     for (i = 0; i < APIC_LVT_NB; i++) {
 214         s->lvt[i] = APIC_LVT_MASKED;
 215     }
 216     s->esr = 0;
 217     memset(s->icr, 0, sizeof(s->icr));
 218     s->divide_conf = 0;
 219     s->count_shift = 0;
 220     s->initial_count = 0;
 221     s->initial_count_load_time = 0;
 222     s->next_time = 0;
 223     s->wait_for_sipi = !cpu_is_bsp(s->cpu);
 224
 225     if (s->timer) {
 226         timer_del(s->timer);
 227     }
 228     s->timer_expiry = -1;
 229
 230     info = APIC_COMMON_GET_CLASS(s);
 231     if (info->reset) {
 232         info->reset(s);
 233     }
 234 }
 235
 236 void apic_designate_bsp(DeviceState *dev, bool bsp)
 237 {
 238     if (dev == NULL) {
 239         return;
 240     }
 241
 242     APICCommonState *s = APIC_COMMON(dev);
 243     if (bsp) {
 244         s->apicbase |= MSR_IA32_APICBASE_BSP;
 245     } else {
 246         s->apicbase &= ~MSR_IA32_APICBASE_BSP;
 247     }
 248 }
 249
 250 static void apic_reset_common(DeviceState *dev)
 251 {
 252     APICCommonState *s = APIC_COMMON(dev);
 253     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 254     uint32_t bsp;
 255
 256     bsp = s->apicbase & MSR_IA32_APICBASE_BSP;
 257     s->apicbase = APIC_DEFAULT_ADDRESS | bsp | MSR_IA32_APICBASE_ENABLE;
 258     s->id = s->initial_apic_id;
 259
 260     kvm_reset_irq_delivered();
 261
 262     s->vapic_paddr = 0;
 263     info->vapic_base_update(s);
 264
 265     apic_init_reset(dev);
 266 }
 267
 268 static const VMStateDescription vmstate_apic_common;
 269
 270 static void apic_common_realize(DeviceState *dev, Error **errp)
 271 {
 272     ERRP_GUARD();
 273     APICCommonState *s = APIC_COMMON(dev);
 274     APICCommonClass *info;
 275     static DeviceState *vapic;
 276     uint32_t instance_id = s->initial_apic_id;
 277
 278     /* Normally initial APIC ID should be no more than hundreds */
 279     assert(instance_id != VMSTATE_INSTANCE_ID_ANY);
 280
 281     info = APIC_COMMON_GET_CLASS(s);
 282     info->realize(dev, errp);
 283     if (*errp) {
 284         return;
 285     }
 286
 287     /* Note: We need at least 1M to map the VAPIC option ROM */
 288     if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK &&
 289             current_machine->ram_size >= 1024 * 1024) {
 290         vapic = sysbus_create_simple("kvmvapic", -1, NULL);
 291     }
 292     s->vapic = vapic;
 293     if (apic_report_tpr_access && info->enable_tpr_reporting) {
 294         info->enable_tpr_reporting(s, true);
 295     }
 296
 297     if (s->legacy_instance_id) {
 298         instance_id = VMSTATE_INSTANCE_ID_ANY;
 299     }
 300     vmstate_register_with_alias_id(NULL, instance_id, &vmstate_apic_common,
 301                                    s, -1, 0, NULL);
 302
 303     /* APIC LDR in x2APIC mode */
 304     s->extended_log_dest = ((s->initial_apic_id >> 4) << 16) |
 305                             (1 << (s->initial_apic_id & 0xf));
 306 }
 307
 308 static void apic_common_unrealize(DeviceState *dev)
 309 {
 310     APICCommonState *s = APIC_COMMON(dev);
 311     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 312
 313     vmstate_unregister(NULL, &vmstate_apic_common, s);
 314     info->unrealize(dev);
 315
 316     if (apic_report_tpr_access && info->enable_tpr_reporting) {
 317         info->enable_tpr_reporting(s, false);
 318     }
 319 }
 320
 321 static int apic_pre_load(void *opaque)
 322 {
 323     APICCommonState *s = APIC_COMMON(opaque);
 324
 325     /* The default is !cpu_is_bsp(s->cpu), but the common value is 0
 326      * so that's what apic_common_sipi_needed checks for.  Reset to
 327      * the value that is assumed when the apic_sipi subsection is
 328      * absent.
 329      */
 330     s->wait_for_sipi = 0;
 331     return 0;
 332 }
 333
 334 static int apic_dispatch_pre_save(void *opaque)
 335 {
 336     APICCommonState *s = APIC_COMMON(opaque);
 337     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 338
 339     if (info->pre_save) {
 340         info->pre_save(s);
 341     }
 342
 343     return 0;
 344 }
 345
 346 static int apic_dispatch_post_load(void *opaque, int version_id)
 347 {
 348     APICCommonState *s = APIC_COMMON(opaque);
 349     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 350
 351     if (info->post_load) {
 352         info->post_load(s);
 353     }
 354     return 0;
 355 }
 356
 357 static bool apic_common_sipi_needed(void *opaque)
 358 {
 359     APICCommonState *s = APIC_COMMON(opaque);
 360     return s->wait_for_sipi != 0;
 361 }
 362
 363 static const VMStateDescription vmstate_apic_common_sipi = {
 364     .name = "apic_sipi",
 365     .version_id = 1,
 366     .minimum_version_id = 1,
 367     .needed = apic_common_sipi_needed,
 368     .fields = (const VMStateField[]) {
 369         VMSTATE_INT32(sipi_vector, APICCommonState),
 370         VMSTATE_INT32(wait_for_sipi, APICCommonState),
 371         VMSTATE_END_OF_LIST()
 372     }
 373 };
 374
 375 static const VMStateDescription vmstate_apic_common = {
 376     .name = "apic",
 377     .version_id = 3,
 378     .minimum_version_id = 3,
 379     .pre_load = apic_pre_load,
 380     .pre_save = apic_dispatch_pre_save,
 381     .post_load = apic_dispatch_post_load,
 382     .fields = (const VMStateField[]) {
 383         VMSTATE_UINT32(apicbase, APICCommonState),
 384         VMSTATE_UINT8(id, APICCommonState),
 385         VMSTATE_UINT8(arb_id, APICCommonState),
 386         VMSTATE_UINT8(tpr, APICCommonState),
 387         VMSTATE_UINT32(spurious_vec, APICCommonState),
 388         VMSTATE_UINT8(log_dest, APICCommonState),
 389         VMSTATE_UINT8(dest_mode, APICCommonState),
 390         VMSTATE_UINT32_ARRAY(isr, APICCommonState, 8),
 391         VMSTATE_UINT32_ARRAY(tmr, APICCommonState, 8),
 392         VMSTATE_UINT32_ARRAY(irr, APICCommonState, 8),
 393         VMSTATE_UINT32_ARRAY(lvt, APICCommonState, APIC_LVT_NB),
 394         VMSTATE_UINT32(esr, APICCommonState),
 395         VMSTATE_UINT32_ARRAY(icr, APICCommonState, 2),
 396         VMSTATE_UINT32(divide_conf, APICCommonState),
 397         VMSTATE_INT32(count_shift, APICCommonState),
 398         VMSTATE_UINT32(initial_count, APICCommonState),
 399         VMSTATE_INT64(initial_count_load_time, APICCommonState),
 400         VMSTATE_INT64(next_time, APICCommonState),
 401         VMSTATE_INT64(timer_expiry,
 402                       APICCommonState), /* open-coded timer state */
 403         VMSTATE_END_OF_LIST()
 404     },
 405     .subsections = (const VMStateDescription * const []) {
 406         &vmstate_apic_common_sipi,
 407         NULL
 408     }
 409 };
 410
 411 static Property apic_properties_common[] = {
 412     DEFINE_PROP_UINT8("version", APICCommonState, version, 0x14),
 413     DEFINE_PROP_BIT("vapic", APICCommonState, vapic_control, VAPIC_ENABLE_BIT,
 414                     true),
 415     DEFINE_PROP_BOOL("legacy-instance-id", APICCommonState, legacy_instance_id,
 416                      false),
 417     DEFINE_PROP_END_OF_LIST(),
 418 };
 419
 420 static void apic_common_get_id(Object *obj, Visitor *v, const char *name,
 421                                void *opaque, Error **errp)
 422 {
 423     APICCommonState *s = APIC_COMMON(obj);
 424     uint32_t value;
 425
 426     value = s->apicbase & MSR_IA32_APICBASE_EXTD ? s->initial_apic_id : s->id;
 427     visit_type_uint32(v, name, &value, errp);
 428 }
 429
 430 static void apic_common_set_id(Object *obj, Visitor *v, const char *name,
 431                                void *opaque, Error **errp)
 432 {
 433     APICCommonState *s = APIC_COMMON(obj);
 434     DeviceState *dev = DEVICE(obj);
 435     uint32_t value;
 436
 437     if (dev->realized) {
 438         qdev_prop_set_after_realize(dev, name, errp);
 439         return;
 440     }
 441
 442     if (!visit_type_uint32(v, name, &value, errp)) {
 443         return;
 444     }
 445
 446     if (value >= 255 && !cpu_has_x2apic_feature(&s->cpu->env)) {
 447         error_setg(errp, "APIC ID %d requires x2APIC feature in CPU", value);
 448         return;
 449     }
 450
 451     s->initial_apic_id = value;
 452     s->id = (uint8_t)value;
 453 }
 454
 455 static void apic_common_initfn(Object *obj)
 456 {
 457     APICCommonState *s = APIC_COMMON(obj);
 458
 459     s->id = s->initial_apic_id = -1;
 460     object_property_add(obj, "id", "uint32",
 461                         apic_common_get_id,
 462                         apic_common_set_id, NULL, NULL);
 463 }
 464
 465 static void apic_common_class_init(ObjectClass *klass, void *data)
 466 {
 467     DeviceClass *dc = DEVICE_CLASS(klass);
 468
 469     dc->reset = apic_reset_common;
 470     device_class_set_props(dc, apic_properties_common);
 471     dc->realize = apic_common_realize;
 472     dc->unrealize = apic_common_unrealize;
 473     /*
 474      * Reason: APIC and CPU need to be wired up by
 475      * x86_cpu_apic_create()
 476      */
 477     dc->user_creatable = false;
 478 }
 479
 480 static const TypeInfo apic_common_type = {
 481     .name = TYPE_APIC_COMMON,
 482     .parent = TYPE_DEVICE,
 483     .instance_size = sizeof(APICCommonState),
 484     .instance_init = apic_common_initfn,
 485     .class_size = sizeof(APICCommonClass),
 486     .class_init = apic_common_class_init,
 487     .abstract = true,
 488 };
 489
 490 static void apic_common_register_types(void)
 491 {
 492     type_register_static(&apic_common_type);
 493 }
 494
 495 type_init(apic_common_register_types)