2 * ARM Generic/Distributed Interrupt Controller
4 * Copyright (c) 2006-2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL.
10 /* This file contains implementation code for the RealView EB interrupt
11 * controller, MPCore distributed interrupt controller and ARMv7-M
12 * Nested Vectored Interrupt Controller.
13 * It is compiled in two ways:
14 * (1) as a standalone file to produce a sysbus device which is a GIC
15 * that can be used on the realview board and as one of the builtin
16 * private peripherals for the ARM MP CPUs (11MPCore, A9, etc)
17 * (2) by being directly #included into armv7m_nvic.c to produce the
21 #include "qemu/osdep.h"
23 #include "hw/sysbus.h"
24 #include "gic_internal.h"
25 #include "qapi/error.h"
26 #include "hw/core/cpu.h"
28 #include "qemu/module.h"
30 #include "sysemu/kvm.h"
31 #include "sysemu/qtest.h"
33 /* #define DEBUG_GIC */
36 #define DEBUG_GIC_GATE 1
38 #define DEBUG_GIC_GATE 0
41 #define DPRINTF(fmt, ...) do { \
42 if (DEBUG_GIC_GATE) { \
43 fprintf(stderr, "%s: " fmt, __func__, ## __VA_ARGS__); \
47 static const uint8_t gic_id_11mpcore
[] = {
48 0x00, 0x00, 0x00, 0x00, 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1
51 static const uint8_t gic_id_gicv1
[] = {
52 0x04, 0x00, 0x00, 0x00, 0x90, 0xb3, 0x1b, 0x00, 0x0d, 0xf0, 0x05, 0xb1
55 static const uint8_t gic_id_gicv2
[] = {
56 0x04, 0x00, 0x00, 0x00, 0x90, 0xb4, 0x2b, 0x00, 0x0d, 0xf0, 0x05, 0xb1
59 static inline int gic_get_current_cpu(GICState
*s
)
61 if (!qtest_enabled() && s
->num_cpu
> 1) {
62 return current_cpu
->cpu_index
;
67 static inline int gic_get_current_vcpu(GICState
*s
)
69 return gic_get_current_cpu(s
) + GIC_NCPU
;
72 /* Return true if this GIC config has interrupt groups, which is
73 * true if we're a GICv2, or a GICv1 with the security extensions.
75 static inline bool gic_has_groups(GICState
*s
)
77 return s
->revision
== 2 || s
->security_extn
;
80 static inline bool gic_cpu_ns_access(GICState
*s
, int cpu
, MemTxAttrs attrs
)
82 return !gic_is_vcpu(cpu
) && s
->security_extn
&& !attrs
.secure
;
85 static inline void gic_get_best_irq(GICState
*s
, int cpu
,
86 int *best_irq
, int *best_prio
, int *group
)
94 for (irq
= 0; irq
< s
->num_irq
; irq
++) {
95 if (GIC_DIST_TEST_ENABLED(irq
, cm
) && gic_test_pending(s
, irq
, cm
) &&
96 (!GIC_DIST_TEST_ACTIVE(irq
, cm
)) &&
97 (irq
< GIC_INTERNAL
|| GIC_DIST_TARGET(irq
) & cm
)) {
98 if (GIC_DIST_GET_PRIORITY(irq
, cpu
) < *best_prio
) {
99 *best_prio
= GIC_DIST_GET_PRIORITY(irq
, cpu
);
105 if (*best_irq
< 1023) {
106 *group
= GIC_DIST_TEST_GROUP(*best_irq
, cm
);
110 static inline void gic_get_best_virq(GICState
*s
, int cpu
,
111 int *best_irq
, int *best_prio
, int *group
)
118 for (lr_idx
= 0; lr_idx
< s
->num_lrs
; lr_idx
++) {
119 uint32_t lr_entry
= s
->h_lr
[lr_idx
][cpu
];
120 int state
= GICH_LR_STATE(lr_entry
);
122 if (state
== GICH_LR_STATE_PENDING
) {
123 int prio
= GICH_LR_PRIORITY(lr_entry
);
125 if (prio
< *best_prio
) {
127 *best_irq
= GICH_LR_VIRT_ID(lr_entry
);
128 *group
= GICH_LR_GROUP(lr_entry
);
134 /* Return true if IRQ signaling is enabled for the given cpu and at least one
135 * of the given groups:
136 * - in the non-virt case, the distributor must be enabled for one of the
138 * - in the virt case, the virtual interface must be enabled.
139 * - in all cases, the (v)CPU interface must be enabled for one of the given
142 static inline bool gic_irq_signaling_enabled(GICState
*s
, int cpu
, bool virt
,
145 int cpu_iface
= virt
? (cpu
+ GIC_NCPU
) : cpu
;
147 if (!virt
&& !(s
->ctlr
& group_mask
)) {
151 if (virt
&& !(s
->h_hcr
[cpu
] & R_GICH_HCR_EN_MASK
)) {
155 if (!(s
->cpu_ctlr
[cpu_iface
] & group_mask
)) {
162 /* TODO: Many places that call this routine could be optimized. */
163 /* Update interrupt status after enabled or pending bits have been changed. */
164 static inline void gic_update_internal(GICState
*s
, bool virt
)
168 int irq_level
, fiq_level
;
171 qemu_irq
*irq_lines
= virt
? s
->parent_virq
: s
->parent_irq
;
172 qemu_irq
*fiq_lines
= virt
? s
->parent_vfiq
: s
->parent_fiq
;
174 for (cpu
= 0; cpu
< s
->num_cpu
; cpu
++) {
175 cpu_iface
= virt
? (cpu
+ GIC_NCPU
) : cpu
;
177 s
->current_pending
[cpu_iface
] = 1023;
178 if (!gic_irq_signaling_enabled(s
, cpu
, virt
,
179 GICD_CTLR_EN_GRP0
| GICD_CTLR_EN_GRP1
)) {
180 qemu_irq_lower(irq_lines
[cpu
]);
181 qemu_irq_lower(fiq_lines
[cpu
]);
186 gic_get_best_virq(s
, cpu
, &best_irq
, &best_prio
, &group
);
188 gic_get_best_irq(s
, cpu
, &best_irq
, &best_prio
, &group
);
191 if (best_irq
!= 1023) {
192 trace_gic_update_bestirq(virt
? "vcpu" : "cpu", cpu
,
194 s
->priority_mask
[cpu_iface
],
195 s
->running_priority
[cpu_iface
]);
198 irq_level
= fiq_level
= 0;
200 if (best_prio
< s
->priority_mask
[cpu_iface
]) {
201 s
->current_pending
[cpu_iface
] = best_irq
;
202 if (best_prio
< s
->running_priority
[cpu_iface
]) {
203 if (gic_irq_signaling_enabled(s
, cpu
, virt
, 1 << group
)) {
205 s
->cpu_ctlr
[cpu_iface
] & GICC_CTLR_FIQ_EN
) {
206 DPRINTF("Raised pending FIQ %d (cpu %d)\n",
207 best_irq
, cpu_iface
);
209 trace_gic_update_set_irq(cpu
, virt
? "vfiq" : "fiq",
212 DPRINTF("Raised pending IRQ %d (cpu %d)\n",
213 best_irq
, cpu_iface
);
215 trace_gic_update_set_irq(cpu
, virt
? "virq" : "irq",
222 qemu_set_irq(irq_lines
[cpu
], irq_level
);
223 qemu_set_irq(fiq_lines
[cpu
], fiq_level
);
227 static void gic_update(GICState
*s
)
229 gic_update_internal(s
, false);
232 /* Return true if this LR is empty, i.e. the corresponding bit
235 static inline bool gic_lr_entry_is_free(uint32_t entry
)
237 return (GICH_LR_STATE(entry
) == GICH_LR_STATE_INVALID
)
238 && (GICH_LR_HW(entry
) || !GICH_LR_EOI(entry
));
241 /* Return true if this LR should trigger an EOI maintenance interrupt, i.e. the
242 * corrsponding bit in EISR is set.
244 static inline bool gic_lr_entry_is_eoi(uint32_t entry
)
246 return (GICH_LR_STATE(entry
) == GICH_LR_STATE_INVALID
)
247 && !GICH_LR_HW(entry
) && GICH_LR_EOI(entry
);
250 static inline void gic_extract_lr_info(GICState
*s
, int cpu
,
251 int *num_eoi
, int *num_valid
, int *num_pending
)
259 for (lr_idx
= 0; lr_idx
< s
->num_lrs
; lr_idx
++) {
260 uint32_t *entry
= &s
->h_lr
[lr_idx
][cpu
];
262 if (gic_lr_entry_is_eoi(*entry
)) {
266 if (GICH_LR_STATE(*entry
) != GICH_LR_STATE_INVALID
) {
270 if (GICH_LR_STATE(*entry
) == GICH_LR_STATE_PENDING
) {
276 static void gic_compute_misr(GICState
*s
, int cpu
)
279 int vcpu
= cpu
+ GIC_NCPU
;
281 int num_eoi
, num_valid
, num_pending
;
283 gic_extract_lr_info(s
, cpu
, &num_eoi
, &num_valid
, &num_pending
);
287 value
|= R_GICH_MISR_EOI_MASK
;
290 /* U: true if only 0 or 1 LR entry is valid */
291 if ((s
->h_hcr
[cpu
] & R_GICH_HCR_UIE_MASK
) && (num_valid
< 2)) {
292 value
|= R_GICH_MISR_U_MASK
;
295 /* LRENP: EOICount is not 0 */
296 if ((s
->h_hcr
[cpu
] & R_GICH_HCR_LRENPIE_MASK
) &&
297 ((s
->h_hcr
[cpu
] & R_GICH_HCR_EOICount_MASK
) != 0)) {
298 value
|= R_GICH_MISR_LRENP_MASK
;
301 /* NP: no pending interrupts */
302 if ((s
->h_hcr
[cpu
] & R_GICH_HCR_NPIE_MASK
) && (num_pending
== 0)) {
303 value
|= R_GICH_MISR_NP_MASK
;
306 /* VGrp0E: group0 virq signaling enabled */
307 if ((s
->h_hcr
[cpu
] & R_GICH_HCR_VGRP0EIE_MASK
) &&
308 (s
->cpu_ctlr
[vcpu
] & GICC_CTLR_EN_GRP0
)) {
309 value
|= R_GICH_MISR_VGrp0E_MASK
;
312 /* VGrp0D: group0 virq signaling disabled */
313 if ((s
->h_hcr
[cpu
] & R_GICH_HCR_VGRP0DIE_MASK
) &&
314 !(s
->cpu_ctlr
[vcpu
] & GICC_CTLR_EN_GRP0
)) {
315 value
|= R_GICH_MISR_VGrp0D_MASK
;
318 /* VGrp1E: group1 virq signaling enabled */
319 if ((s
->h_hcr
[cpu
] & R_GICH_HCR_VGRP1EIE_MASK
) &&
320 (s
->cpu_ctlr
[vcpu
] & GICC_CTLR_EN_GRP1
)) {
321 value
|= R_GICH_MISR_VGrp1E_MASK
;
324 /* VGrp1D: group1 virq signaling disabled */
325 if ((s
->h_hcr
[cpu
] & R_GICH_HCR_VGRP1DIE_MASK
) &&
326 !(s
->cpu_ctlr
[vcpu
] & GICC_CTLR_EN_GRP1
)) {
327 value
|= R_GICH_MISR_VGrp1D_MASK
;
330 s
->h_misr
[cpu
] = value
;
333 static void gic_update_maintenance(GICState
*s
)
338 for (cpu
= 0; cpu
< s
->num_cpu
; cpu
++) {
339 gic_compute_misr(s
, cpu
);
340 maint_level
= (s
->h_hcr
[cpu
] & R_GICH_HCR_EN_MASK
) && s
->h_misr
[cpu
];
342 trace_gic_update_maintenance_irq(cpu
, maint_level
);
343 qemu_set_irq(s
->maintenance_irq
[cpu
], maint_level
);
347 static void gic_update_virt(GICState
*s
)
349 gic_update_internal(s
, true);
350 gic_update_maintenance(s
);
353 static void gic_set_irq_11mpcore(GICState
*s
, int irq
, int level
,
357 GIC_DIST_SET_LEVEL(irq
, cm
);
358 if (GIC_DIST_TEST_EDGE_TRIGGER(irq
) || GIC_DIST_TEST_ENABLED(irq
, cm
)) {
359 DPRINTF("Set %d pending mask %x\n", irq
, target
);
360 GIC_DIST_SET_PENDING(irq
, target
);
363 GIC_DIST_CLEAR_LEVEL(irq
, cm
);
367 static void gic_set_irq_generic(GICState
*s
, int irq
, int level
,
371 GIC_DIST_SET_LEVEL(irq
, cm
);
372 DPRINTF("Set %d pending mask %x\n", irq
, target
);
373 if (GIC_DIST_TEST_EDGE_TRIGGER(irq
)) {
374 GIC_DIST_SET_PENDING(irq
, target
);
377 GIC_DIST_CLEAR_LEVEL(irq
, cm
);
381 /* Process a change in an external IRQ input. */
382 static void gic_set_irq(void *opaque
, int irq
, int level
)
384 /* Meaning of the 'irq' parameter:
385 * [0..N-1] : external interrupts
386 * [N..N+31] : PPI (internal) interrupts for CPU 0
387 * [N+32..N+63] : PPI (internal interrupts for CPU 1
390 GICState
*s
= (GICState
*)opaque
;
392 if (irq
< (s
->num_irq
- GIC_INTERNAL
)) {
393 /* The first external input line is internal interrupt 32. */
396 target
= GIC_DIST_TARGET(irq
);
399 irq
-= (s
->num_irq
- GIC_INTERNAL
);
400 cpu
= irq
/ GIC_INTERNAL
;
406 assert(irq
>= GIC_NR_SGIS
);
408 if (level
== GIC_DIST_TEST_LEVEL(irq
, cm
)) {
412 if (s
->revision
== REV_11MPCORE
) {
413 gic_set_irq_11mpcore(s
, irq
, level
, cm
, target
);
415 gic_set_irq_generic(s
, irq
, level
, cm
, target
);
417 trace_gic_set_irq(irq
, level
, cm
, target
);
422 static uint16_t gic_get_current_pending_irq(GICState
*s
, int cpu
,
425 uint16_t pending_irq
= s
->current_pending
[cpu
];
427 if (pending_irq
< GIC_MAXIRQ
&& gic_has_groups(s
)) {
428 int group
= gic_test_group(s
, pending_irq
, cpu
);
430 /* On a GIC without the security extensions, reading this register
431 * behaves in the same way as a secure access to a GIC with them.
433 bool secure
= !gic_cpu_ns_access(s
, cpu
, attrs
);
435 if (group
== 0 && !secure
) {
436 /* Group0 interrupts hidden from Non-secure access */
439 if (group
== 1 && secure
&& !(s
->cpu_ctlr
[cpu
] & GICC_CTLR_ACK_CTL
)) {
440 /* Group1 interrupts only seen by Secure access if
449 static int gic_get_group_priority(GICState
*s
, int cpu
, int irq
)
451 /* Return the group priority of the specified interrupt
452 * (which is the top bits of its priority, with the number
453 * of bits masked determined by the applicable binary point register).
458 if (gic_has_groups(s
) &&
459 !(s
->cpu_ctlr
[cpu
] & GICC_CTLR_CBPR
) &&
460 gic_test_group(s
, irq
, cpu
)) {
461 bpr
= s
->abpr
[cpu
] - 1;
467 /* a BPR of 0 means the group priority bits are [7:1];
468 * a BPR of 1 means they are [7:2], and so on down to
469 * a BPR of 7 meaning no group priority bits at all.
471 mask
= ~0U << ((bpr
& 7) + 1);
473 return gic_get_priority(s
, irq
, cpu
) & mask
;
476 static void gic_activate_irq(GICState
*s
, int cpu
, int irq
)
478 /* Set the appropriate Active Priority Register bit for this IRQ,
479 * and update the running priority.
481 int prio
= gic_get_group_priority(s
, cpu
, irq
);
482 int min_bpr
= gic_is_vcpu(cpu
) ? GIC_VIRT_MIN_BPR
: GIC_MIN_BPR
;
483 int preemption_level
= prio
>> (min_bpr
+ 1);
484 int regno
= preemption_level
/ 32;
485 int bitno
= preemption_level
% 32;
486 uint32_t *papr
= NULL
;
488 if (gic_is_vcpu(cpu
)) {
490 papr
= &s
->h_apr
[gic_get_vcpu_real_id(cpu
)];
491 } else if (gic_has_groups(s
) && gic_test_group(s
, irq
, cpu
)) {
492 papr
= &s
->nsapr
[regno
][cpu
];
494 papr
= &s
->apr
[regno
][cpu
];
497 *papr
|= (1 << bitno
);
499 s
->running_priority
[cpu
] = prio
;
500 gic_set_active(s
, irq
, cpu
);
503 static int gic_get_prio_from_apr_bits(GICState
*s
, int cpu
)
505 /* Recalculate the current running priority for this CPU based
506 * on the set bits in the Active Priority Registers.
510 if (gic_is_vcpu(cpu
)) {
511 uint32_t apr
= s
->h_apr
[gic_get_vcpu_real_id(cpu
)];
513 return ctz32(apr
) << (GIC_VIRT_MIN_BPR
+ 1);
519 for (i
= 0; i
< GIC_NR_APRS
; i
++) {
520 uint32_t apr
= s
->apr
[i
][cpu
] | s
->nsapr
[i
][cpu
];
524 return (i
* 32 + ctz32(apr
)) << (GIC_MIN_BPR
+ 1);
529 static void gic_drop_prio(GICState
*s
, int cpu
, int group
)
531 /* Drop the priority of the currently active interrupt in the
534 * Note that we can guarantee (because of the requirement to nest
535 * GICC_IAR reads [which activate an interrupt and raise priority]
536 * with GICC_EOIR writes [which drop the priority for the interrupt])
537 * that the interrupt we're being called for is the highest priority
538 * active interrupt, meaning that it has the lowest set bit in the
541 * If the guest does not honour the ordering constraints then the
542 * behaviour of the GIC is UNPREDICTABLE, which for us means that
543 * the values of the APR registers might become incorrect and the
544 * running priority will be wrong, so interrupts that should preempt
545 * might not do so, and interrupts that should not preempt might do so.
547 if (gic_is_vcpu(cpu
)) {
548 int rcpu
= gic_get_vcpu_real_id(cpu
);
550 if (s
->h_apr
[rcpu
]) {
551 /* Clear lowest set bit */
552 s
->h_apr
[rcpu
] &= s
->h_apr
[rcpu
] - 1;
557 for (i
= 0; i
< GIC_NR_APRS
; i
++) {
558 uint32_t *papr
= group
? &s
->nsapr
[i
][cpu
] : &s
->apr
[i
][cpu
];
562 /* Clear lowest set bit */
568 s
->running_priority
[cpu
] = gic_get_prio_from_apr_bits(s
, cpu
);
571 static inline uint32_t gic_clear_pending_sgi(GICState
*s
, int irq
, int cpu
)
576 if (!gic_is_vcpu(cpu
)) {
577 /* Lookup the source CPU for the SGI and clear this in the
578 * sgi_pending map. Return the src and clear the overall pending
579 * state on this CPU if the SGI is not pending from any CPUs.
581 assert(s
->sgi_pending
[irq
][cpu
] != 0);
582 src
= ctz32(s
->sgi_pending
[irq
][cpu
]);
583 s
->sgi_pending
[irq
][cpu
] &= ~(1 << src
);
584 if (s
->sgi_pending
[irq
][cpu
] == 0) {
585 gic_clear_pending(s
, irq
, cpu
);
587 ret
= irq
| ((src
& 0x7) << 10);
589 uint32_t *lr_entry
= gic_get_lr_entry(s
, irq
, cpu
);
590 src
= GICH_LR_CPUID(*lr_entry
);
592 gic_clear_pending(s
, irq
, cpu
);
593 ret
= irq
| (src
<< 10);
599 uint32_t gic_acknowledge_irq(GICState
*s
, int cpu
, MemTxAttrs attrs
)
603 /* gic_get_current_pending_irq() will return 1022 or 1023 appropriately
604 * for the case where this GIC supports grouping and the pending interrupt
605 * is in the wrong group.
607 irq
= gic_get_current_pending_irq(s
, cpu
, attrs
);
608 trace_gic_acknowledge_irq(gic_is_vcpu(cpu
) ? "vcpu" : "cpu",
609 gic_get_vcpu_real_id(cpu
), irq
);
611 if (irq
>= GIC_MAXIRQ
) {
612 DPRINTF("ACK, no pending interrupt or it is hidden: %d\n", irq
);
616 if (gic_get_priority(s
, irq
, cpu
) >= s
->running_priority
[cpu
]) {
617 DPRINTF("ACK, pending interrupt (%d) has insufficient priority\n", irq
);
621 gic_activate_irq(s
, cpu
, irq
);
623 if (s
->revision
== REV_11MPCORE
) {
624 /* Clear pending flags for both level and edge triggered interrupts.
625 * Level triggered IRQs will be reasserted once they become inactive.
627 gic_clear_pending(s
, irq
, cpu
);
630 if (irq
< GIC_NR_SGIS
) {
631 ret
= gic_clear_pending_sgi(s
, irq
, cpu
);
633 gic_clear_pending(s
, irq
, cpu
);
638 if (gic_is_vcpu(cpu
)) {
643 DPRINTF("ACK %d\n", irq
);
647 static uint32_t gic_fullprio_mask(GICState
*s
, int cpu
)
650 * Return a mask word which clears the unimplemented priority
651 * bits from a priority value for an interrupt. (Not to be
652 * confused with the group priority, whose mask depends on BPR.)
656 if (gic_is_vcpu(cpu
)) {
657 priBits
= GIC_VIRT_MAX_GROUP_PRIO_BITS
;
659 priBits
= s
->n_prio_bits
;
661 return ~0U << (8 - priBits
);
664 void gic_dist_set_priority(GICState
*s
, int cpu
, int irq
, uint8_t val
,
667 if (s
->security_extn
&& !attrs
.secure
) {
668 if (!GIC_DIST_TEST_GROUP(irq
, (1 << cpu
))) {
669 return; /* Ignore Non-secure access of Group0 IRQ */
671 val
= 0x80 | (val
>> 1); /* Non-secure view */
674 val
&= gic_fullprio_mask(s
, cpu
);
676 if (irq
< GIC_INTERNAL
) {
677 s
->priority1
[irq
][cpu
] = val
;
679 s
->priority2
[(irq
) - GIC_INTERNAL
] = val
;
683 static uint32_t gic_dist_get_priority(GICState
*s
, int cpu
, int irq
,
686 uint32_t prio
= GIC_DIST_GET_PRIORITY(irq
, cpu
);
688 if (s
->security_extn
&& !attrs
.secure
) {
689 if (!GIC_DIST_TEST_GROUP(irq
, (1 << cpu
))) {
690 return 0; /* Non-secure access cannot read priority of Group0 IRQ */
692 prio
= (prio
<< 1) & 0xff; /* Non-secure view */
694 return prio
& gic_fullprio_mask(s
, cpu
);
697 static void gic_set_priority_mask(GICState
*s
, int cpu
, uint8_t pmask
,
700 if (gic_cpu_ns_access(s
, cpu
, attrs
)) {
701 if (s
->priority_mask
[cpu
] & 0x80) {
702 /* Priority Mask in upper half */
703 pmask
= 0x80 | (pmask
>> 1);
705 /* Non-secure write ignored if priority mask is in lower half */
709 s
->priority_mask
[cpu
] = pmask
& gic_fullprio_mask(s
, cpu
);
712 static uint32_t gic_get_priority_mask(GICState
*s
, int cpu
, MemTxAttrs attrs
)
714 uint32_t pmask
= s
->priority_mask
[cpu
];
716 if (gic_cpu_ns_access(s
, cpu
, attrs
)) {
718 /* Priority Mask in upper half, return Non-secure view */
719 pmask
= (pmask
<< 1) & 0xff;
721 /* Priority Mask in lower half, RAZ */
728 static uint32_t gic_get_cpu_control(GICState
*s
, int cpu
, MemTxAttrs attrs
)
730 uint32_t ret
= s
->cpu_ctlr
[cpu
];
732 if (gic_cpu_ns_access(s
, cpu
, attrs
)) {
733 /* Construct the NS banked view of GICC_CTLR from the correct
734 * bits of the S banked view. We don't need to move the bypass
735 * control bits because we don't implement that (IMPDEF) part
736 * of the GIC architecture.
738 ret
= (ret
& (GICC_CTLR_EN_GRP1
| GICC_CTLR_EOIMODE_NS
)) >> 1;
743 static void gic_set_cpu_control(GICState
*s
, int cpu
, uint32_t value
,
748 if (gic_cpu_ns_access(s
, cpu
, attrs
)) {
749 /* The NS view can only write certain bits in the register;
750 * the rest are unchanged
752 mask
= GICC_CTLR_EN_GRP1
;
753 if (s
->revision
== 2) {
754 mask
|= GICC_CTLR_EOIMODE_NS
;
756 s
->cpu_ctlr
[cpu
] &= ~mask
;
757 s
->cpu_ctlr
[cpu
] |= (value
<< 1) & mask
;
759 if (s
->revision
== 2) {
760 mask
= s
->security_extn
? GICC_CTLR_V2_S_MASK
: GICC_CTLR_V2_MASK
;
762 mask
= s
->security_extn
? GICC_CTLR_V1_S_MASK
: GICC_CTLR_V1_MASK
;
764 s
->cpu_ctlr
[cpu
] = value
& mask
;
766 DPRINTF("CPU Interface %d: Group0 Interrupts %sabled, "
767 "Group1 Interrupts %sabled\n", cpu
,
768 (s
->cpu_ctlr
[cpu
] & GICC_CTLR_EN_GRP0
) ? "En" : "Dis",
769 (s
->cpu_ctlr
[cpu
] & GICC_CTLR_EN_GRP1
) ? "En" : "Dis");
772 static uint8_t gic_get_running_priority(GICState
*s
, int cpu
, MemTxAttrs attrs
)
774 if ((s
->revision
!= REV_11MPCORE
) && (s
->running_priority
[cpu
] > 0xff)) {
779 if (gic_cpu_ns_access(s
, cpu
, attrs
)) {
780 if (s
->running_priority
[cpu
] & 0x80) {
781 /* Running priority in upper half of range: return the Non-secure
782 * view of the priority.
784 return s
->running_priority
[cpu
] << 1;
786 /* Running priority in lower half of range: RAZ */
790 return s
->running_priority
[cpu
];
794 /* Return true if we should split priority drop and interrupt deactivation,
795 * ie whether the relevant EOIMode bit is set.
797 static bool gic_eoi_split(GICState
*s
, int cpu
, MemTxAttrs attrs
)
799 if (s
->revision
!= 2) {
800 /* Before GICv2 prio-drop and deactivate are not separable */
803 if (gic_cpu_ns_access(s
, cpu
, attrs
)) {
804 return s
->cpu_ctlr
[cpu
] & GICC_CTLR_EOIMODE_NS
;
806 return s
->cpu_ctlr
[cpu
] & GICC_CTLR_EOIMODE
;
809 static void gic_deactivate_irq(GICState
*s
, int cpu
, int irq
, MemTxAttrs attrs
)
813 if (irq
>= GIC_MAXIRQ
|| (!gic_is_vcpu(cpu
) && irq
>= s
->num_irq
)) {
815 * This handles two cases:
816 * 1. If software writes the ID of a spurious interrupt [ie 1023]
817 * to the GICC_DIR, the GIC ignores that write.
818 * 2. If software writes the number of a non-existent interrupt
819 * this must be a subcase of "value written is not an active interrupt"
820 * and so this is UNPREDICTABLE. We choose to ignore it. For vCPUs,
821 * all IRQs potentially exist, so this limit does not apply.
826 if (!gic_eoi_split(s
, cpu
, attrs
)) {
827 /* This is UNPREDICTABLE; we choose to ignore it */
828 qemu_log_mask(LOG_GUEST_ERROR
,
829 "gic_deactivate_irq: GICC_DIR write when EOIMode clear");
833 if (gic_is_vcpu(cpu
) && !gic_virq_is_valid(s
, irq
, cpu
)) {
834 /* This vIRQ does not have an LR entry which is either active or
835 * pending and active. Increment EOICount and ignore the write.
837 int rcpu
= gic_get_vcpu_real_id(cpu
);
838 s
->h_hcr
[rcpu
] += 1 << R_GICH_HCR_EOICount_SHIFT
;
840 /* Update the virtual interface in case a maintenance interrupt should
847 group
= gic_has_groups(s
) && gic_test_group(s
, irq
, cpu
);
849 if (gic_cpu_ns_access(s
, cpu
, attrs
) && !group
) {
850 DPRINTF("Non-secure DI for Group0 interrupt %d ignored\n", irq
);
854 gic_clear_active(s
, irq
, cpu
);
857 static void gic_complete_irq(GICState
*s
, int cpu
, int irq
, MemTxAttrs attrs
)
862 DPRINTF("EOI %d\n", irq
);
863 if (gic_is_vcpu(cpu
)) {
864 /* The call to gic_prio_drop() will clear a bit in GICH_APR iff the
865 * running prio is < 0x100.
867 bool prio_drop
= s
->running_priority
[cpu
] < 0x100;
869 if (irq
>= GIC_MAXIRQ
) {
870 /* Ignore spurious interrupt */
874 gic_drop_prio(s
, cpu
, 0);
876 if (!gic_eoi_split(s
, cpu
, attrs
)) {
877 bool valid
= gic_virq_is_valid(s
, irq
, cpu
);
878 if (prio_drop
&& !valid
) {
879 /* We are in a situation where:
880 * - V_CTRL.EOIMode is false (no EOI split),
881 * - The call to gic_drop_prio() cleared a bit in GICH_APR,
882 * - This vIRQ does not have an LR entry which is either
883 * active or pending and active.
884 * In that case, we must increment EOICount.
886 int rcpu
= gic_get_vcpu_real_id(cpu
);
887 s
->h_hcr
[rcpu
] += 1 << R_GICH_HCR_EOICount_SHIFT
;
889 gic_clear_active(s
, irq
, cpu
);
897 if (irq
>= s
->num_irq
) {
898 /* This handles two cases:
899 * 1. If software writes the ID of a spurious interrupt [ie 1023]
900 * to the GICC_EOIR, the GIC ignores that write.
901 * 2. If software writes the number of a non-existent interrupt
902 * this must be a subcase of "value written does not match the last
903 * valid interrupt value read from the Interrupt Acknowledge
904 * register" and so this is UNPREDICTABLE. We choose to ignore it.
908 if (s
->running_priority
[cpu
] == 0x100) {
909 return; /* No active IRQ. */
912 if (s
->revision
== REV_11MPCORE
) {
913 /* Mark level triggered interrupts as pending if they are still
915 if (!GIC_DIST_TEST_EDGE_TRIGGER(irq
) && GIC_DIST_TEST_ENABLED(irq
, cm
)
916 && GIC_DIST_TEST_LEVEL(irq
, cm
)
917 && (GIC_DIST_TARGET(irq
) & cm
) != 0) {
918 DPRINTF("Set %d pending mask %x\n", irq
, cm
);
919 GIC_DIST_SET_PENDING(irq
, cm
);
923 group
= gic_has_groups(s
) && gic_test_group(s
, irq
, cpu
);
925 if (gic_cpu_ns_access(s
, cpu
, attrs
) && !group
) {
926 DPRINTF("Non-secure EOI for Group0 interrupt %d ignored\n", irq
);
930 /* Secure EOI with GICC_CTLR.AckCtl == 0 when the IRQ is a Group 1
931 * interrupt is UNPREDICTABLE. We choose to handle it as if AckCtl == 1,
932 * i.e. go ahead and complete the irq anyway.
935 gic_drop_prio(s
, cpu
, group
);
937 /* In GICv2 the guest can choose to split priority-drop and deactivate */
938 if (!gic_eoi_split(s
, cpu
, attrs
)) {
939 gic_clear_active(s
, irq
, cpu
);
944 static uint32_t gic_dist_readb(void *opaque
, hwaddr offset
, MemTxAttrs attrs
)
946 GICState
*s
= (GICState
*)opaque
;
954 cpu
= gic_get_current_cpu(s
);
956 if (offset
< 0x100) {
957 if (offset
== 0) { /* GICD_CTLR */
958 if (s
->security_extn
&& !attrs
.secure
) {
959 /* The NS bank of this register is just an alias of the
960 * EnableGrp1 bit in the S bank version.
962 return extract32(s
->ctlr
, 1, 1);
968 /* Interrupt Controller Type Register */
969 return ((s
->num_irq
/ 32) - 1)
970 | ((s
->num_cpu
- 1) << 5)
971 | (s
->security_extn
<< 10);
974 if (offset
>= 0x80) {
975 /* Interrupt Group Registers: these RAZ/WI if this is an NS
976 * access to a GIC with the security extensions, or if the GIC
977 * doesn't have groups at all.
980 if (!(s
->security_extn
&& !attrs
.secure
) && gic_has_groups(s
)) {
981 /* Every byte offset holds 8 group status bits */
982 irq
= (offset
- 0x080) * 8;
983 if (irq
>= s
->num_irq
) {
986 for (i
= 0; i
< 8; i
++) {
987 if (GIC_DIST_TEST_GROUP(irq
+ i
, cm
)) {
995 } else if (offset
< 0x200) {
996 /* Interrupt Set/Clear Enable. */
998 irq
= (offset
- 0x100) * 8;
1000 irq
= (offset
- 0x180) * 8;
1001 if (irq
>= s
->num_irq
)
1004 for (i
= 0; i
< 8; i
++) {
1005 if (s
->security_extn
&& !attrs
.secure
&&
1006 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
1007 continue; /* Ignore Non-secure access of Group0 IRQ */
1010 if (GIC_DIST_TEST_ENABLED(irq
+ i
, cm
)) {
1014 } else if (offset
< 0x300) {
1015 /* Interrupt Set/Clear Pending. */
1017 irq
= (offset
- 0x200) * 8;
1019 irq
= (offset
- 0x280) * 8;
1020 if (irq
>= s
->num_irq
)
1023 mask
= (irq
< GIC_INTERNAL
) ? cm
: ALL_CPU_MASK
;
1024 for (i
= 0; i
< 8; i
++) {
1025 if (s
->security_extn
&& !attrs
.secure
&&
1026 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
1027 continue; /* Ignore Non-secure access of Group0 IRQ */
1030 if (gic_test_pending(s
, irq
+ i
, mask
)) {
1034 } else if (offset
< 0x400) {
1035 /* Interrupt Set/Clear Active. */
1036 if (offset
< 0x380) {
1037 irq
= (offset
- 0x300) * 8;
1038 } else if (s
->revision
== 2) {
1039 irq
= (offset
- 0x380) * 8;
1044 if (irq
>= s
->num_irq
)
1047 mask
= (irq
< GIC_INTERNAL
) ? cm
: ALL_CPU_MASK
;
1048 for (i
= 0; i
< 8; i
++) {
1049 if (s
->security_extn
&& !attrs
.secure
&&
1050 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
1051 continue; /* Ignore Non-secure access of Group0 IRQ */
1054 if (GIC_DIST_TEST_ACTIVE(irq
+ i
, mask
)) {
1058 } else if (offset
< 0x800) {
1059 /* Interrupt Priority. */
1060 irq
= (offset
- 0x400);
1061 if (irq
>= s
->num_irq
)
1063 res
= gic_dist_get_priority(s
, cpu
, irq
, attrs
);
1064 } else if (offset
< 0xc00) {
1065 /* Interrupt CPU Target. */
1066 if (s
->num_cpu
== 1 && s
->revision
!= REV_11MPCORE
) {
1067 /* For uniprocessor GICs these RAZ/WI */
1070 irq
= (offset
- 0x800);
1071 if (irq
>= s
->num_irq
) {
1074 if (irq
< 29 && s
->revision
== REV_11MPCORE
) {
1076 } else if (irq
< GIC_INTERNAL
) {
1079 res
= GIC_DIST_TARGET(irq
);
1082 } else if (offset
< 0xf00) {
1083 /* Interrupt Configuration. */
1084 irq
= (offset
- 0xc00) * 4;
1085 if (irq
>= s
->num_irq
)
1088 for (i
= 0; i
< 4; i
++) {
1089 if (s
->security_extn
&& !attrs
.secure
&&
1090 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
1091 continue; /* Ignore Non-secure access of Group0 IRQ */
1094 if (GIC_DIST_TEST_MODEL(irq
+ i
)) {
1095 res
|= (1 << (i
* 2));
1097 if (GIC_DIST_TEST_EDGE_TRIGGER(irq
+ i
)) {
1098 res
|= (2 << (i
* 2));
1101 } else if (offset
< 0xf10) {
1103 } else if (offset
< 0xf30) {
1104 if (s
->revision
== REV_11MPCORE
) {
1108 if (offset
< 0xf20) {
1109 /* GICD_CPENDSGIRn */
1110 irq
= (offset
- 0xf10);
1112 irq
= (offset
- 0xf20);
1113 /* GICD_SPENDSGIRn */
1116 if (s
->security_extn
&& !attrs
.secure
&&
1117 !GIC_DIST_TEST_GROUP(irq
, 1 << cpu
)) {
1118 res
= 0; /* Ignore Non-secure access of Group0 IRQ */
1120 res
= s
->sgi_pending
[irq
][cpu
];
1122 } else if (offset
< 0xfd0) {
1124 } else if (offset
< 0x1000) {
1128 switch (s
->revision
) {
1130 res
= gic_id_11mpcore
[(offset
- 0xfd0) >> 2];
1133 res
= gic_id_gicv1
[(offset
- 0xfd0) >> 2];
1136 res
= gic_id_gicv2
[(offset
- 0xfd0) >> 2];
1143 g_assert_not_reached();
1147 qemu_log_mask(LOG_GUEST_ERROR
,
1148 "gic_dist_readb: Bad offset %x\n", (int)offset
);
1152 static MemTxResult
gic_dist_read(void *opaque
, hwaddr offset
, uint64_t *data
,
1153 unsigned size
, MemTxAttrs attrs
)
1157 *data
= gic_dist_readb(opaque
, offset
, attrs
);
1160 *data
= gic_dist_readb(opaque
, offset
, attrs
);
1161 *data
|= gic_dist_readb(opaque
, offset
+ 1, attrs
) << 8;
1164 *data
= gic_dist_readb(opaque
, offset
, attrs
);
1165 *data
|= gic_dist_readb(opaque
, offset
+ 1, attrs
) << 8;
1166 *data
|= gic_dist_readb(opaque
, offset
+ 2, attrs
) << 16;
1167 *data
|= gic_dist_readb(opaque
, offset
+ 3, attrs
) << 24;
1173 trace_gic_dist_read(offset
, size
, *data
);
1177 static void gic_dist_writeb(void *opaque
, hwaddr offset
,
1178 uint32_t value
, MemTxAttrs attrs
)
1180 GICState
*s
= (GICState
*)opaque
;
1185 cpu
= gic_get_current_cpu(s
);
1186 if (offset
< 0x100) {
1188 if (s
->security_extn
&& !attrs
.secure
) {
1189 /* NS version is just an alias of the S version's bit 1 */
1190 s
->ctlr
= deposit32(s
->ctlr
, 1, 1, value
);
1191 } else if (gic_has_groups(s
)) {
1192 s
->ctlr
= value
& (GICD_CTLR_EN_GRP0
| GICD_CTLR_EN_GRP1
);
1194 s
->ctlr
= value
& GICD_CTLR_EN_GRP0
;
1196 DPRINTF("Distributor: Group0 %sabled; Group 1 %sabled\n",
1197 s
->ctlr
& GICD_CTLR_EN_GRP0
? "En" : "Dis",
1198 s
->ctlr
& GICD_CTLR_EN_GRP1
? "En" : "Dis");
1199 } else if (offset
< 4) {
1201 } else if (offset
>= 0x80) {
1202 /* Interrupt Group Registers: RAZ/WI for NS access to secure
1203 * GIC, or for GICs without groups.
1205 if (!(s
->security_extn
&& !attrs
.secure
) && gic_has_groups(s
)) {
1206 /* Every byte offset holds 8 group status bits */
1207 irq
= (offset
- 0x80) * 8;
1208 if (irq
>= s
->num_irq
) {
1211 for (i
= 0; i
< 8; i
++) {
1212 /* Group bits are banked for private interrupts */
1213 int cm
= (irq
< GIC_INTERNAL
) ? (1 << cpu
) : ALL_CPU_MASK
;
1214 if (value
& (1 << i
)) {
1215 /* Group1 (Non-secure) */
1216 GIC_DIST_SET_GROUP(irq
+ i
, cm
);
1218 /* Group0 (Secure) */
1219 GIC_DIST_CLEAR_GROUP(irq
+ i
, cm
);
1226 } else if (offset
< 0x180) {
1227 /* Interrupt Set Enable. */
1228 irq
= (offset
- 0x100) * 8;
1229 if (irq
>= s
->num_irq
)
1231 if (irq
< GIC_NR_SGIS
) {
1235 for (i
= 0; i
< 8; i
++) {
1236 if (value
& (1 << i
)) {
1238 (irq
< GIC_INTERNAL
) ? (1 << cpu
)
1239 : GIC_DIST_TARGET(irq
+ i
);
1240 int cm
= (irq
< GIC_INTERNAL
) ? (1 << cpu
) : ALL_CPU_MASK
;
1242 if (s
->security_extn
&& !attrs
.secure
&&
1243 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
1244 continue; /* Ignore Non-secure access of Group0 IRQ */
1247 if (!GIC_DIST_TEST_ENABLED(irq
+ i
, cm
)) {
1248 DPRINTF("Enabled IRQ %d\n", irq
+ i
);
1249 trace_gic_enable_irq(irq
+ i
);
1251 GIC_DIST_SET_ENABLED(irq
+ i
, cm
);
1252 /* If a raised level triggered IRQ enabled then mark
1254 if (GIC_DIST_TEST_LEVEL(irq
+ i
, mask
)
1255 && !GIC_DIST_TEST_EDGE_TRIGGER(irq
+ i
)) {
1256 DPRINTF("Set %d pending mask %x\n", irq
+ i
, mask
);
1257 GIC_DIST_SET_PENDING(irq
+ i
, mask
);
1261 } else if (offset
< 0x200) {
1262 /* Interrupt Clear Enable. */
1263 irq
= (offset
- 0x180) * 8;
1264 if (irq
>= s
->num_irq
)
1266 if (irq
< GIC_NR_SGIS
) {
1270 for (i
= 0; i
< 8; i
++) {
1271 if (value
& (1 << i
)) {
1272 int cm
= (irq
< GIC_INTERNAL
) ? (1 << cpu
) : ALL_CPU_MASK
;
1274 if (s
->security_extn
&& !attrs
.secure
&&
1275 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
1276 continue; /* Ignore Non-secure access of Group0 IRQ */
1279 if (GIC_DIST_TEST_ENABLED(irq
+ i
, cm
)) {
1280 DPRINTF("Disabled IRQ %d\n", irq
+ i
);
1281 trace_gic_disable_irq(irq
+ i
);
1283 GIC_DIST_CLEAR_ENABLED(irq
+ i
, cm
);
1286 } else if (offset
< 0x280) {
1287 /* Interrupt Set Pending. */
1288 irq
= (offset
- 0x200) * 8;
1289 if (irq
>= s
->num_irq
)
1291 if (irq
< GIC_NR_SGIS
) {
1295 for (i
= 0; i
< 8; i
++) {
1296 if (value
& (1 << i
)) {
1297 if (s
->security_extn
&& !attrs
.secure
&&
1298 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
1299 continue; /* Ignore Non-secure access of Group0 IRQ */
1302 GIC_DIST_SET_PENDING(irq
+ i
, GIC_DIST_TARGET(irq
+ i
));
1305 } else if (offset
< 0x300) {
1306 /* Interrupt Clear Pending. */
1307 irq
= (offset
- 0x280) * 8;
1308 if (irq
>= s
->num_irq
)
1310 if (irq
< GIC_NR_SGIS
) {
1314 for (i
= 0; i
< 8; i
++) {
1315 if (s
->security_extn
&& !attrs
.secure
&&
1316 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
1317 continue; /* Ignore Non-secure access of Group0 IRQ */
1320 /* ??? This currently clears the pending bit for all CPUs, even
1321 for per-CPU interrupts. It's unclear whether this is the
1323 if (value
& (1 << i
)) {
1324 GIC_DIST_CLEAR_PENDING(irq
+ i
, ALL_CPU_MASK
);
1327 } else if (offset
< 0x380) {
1328 /* Interrupt Set Active. */
1329 if (s
->revision
!= 2) {
1333 irq
= (offset
- 0x300) * 8;
1334 if (irq
>= s
->num_irq
) {
1338 /* This register is banked per-cpu for PPIs */
1339 int cm
= irq
< GIC_INTERNAL
? (1 << cpu
) : ALL_CPU_MASK
;
1341 for (i
= 0; i
< 8; i
++) {
1342 if (s
->security_extn
&& !attrs
.secure
&&
1343 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
1344 continue; /* Ignore Non-secure access of Group0 IRQ */
1347 if (value
& (1 << i
)) {
1348 GIC_DIST_SET_ACTIVE(irq
+ i
, cm
);
1351 } else if (offset
< 0x400) {
1352 /* Interrupt Clear Active. */
1353 if (s
->revision
!= 2) {
1357 irq
= (offset
- 0x380) * 8;
1358 if (irq
>= s
->num_irq
) {
1362 /* This register is banked per-cpu for PPIs */
1363 int cm
= irq
< GIC_INTERNAL
? (1 << cpu
) : ALL_CPU_MASK
;
1365 for (i
= 0; i
< 8; i
++) {
1366 if (s
->security_extn
&& !attrs
.secure
&&
1367 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
1368 continue; /* Ignore Non-secure access of Group0 IRQ */
1371 if (value
& (1 << i
)) {
1372 GIC_DIST_CLEAR_ACTIVE(irq
+ i
, cm
);
1375 } else if (offset
< 0x800) {
1376 /* Interrupt Priority. */
1377 irq
= (offset
- 0x400);
1378 if (irq
>= s
->num_irq
)
1380 gic_dist_set_priority(s
, cpu
, irq
, value
, attrs
);
1381 } else if (offset
< 0xc00) {
1382 /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the
1383 * annoying exception of the 11MPCore's GIC.
1385 if (s
->num_cpu
!= 1 || s
->revision
== REV_11MPCORE
) {
1386 irq
= (offset
- 0x800);
1387 if (irq
>= s
->num_irq
) {
1390 if (irq
< 29 && s
->revision
== REV_11MPCORE
) {
1392 } else if (irq
< GIC_INTERNAL
) {
1393 value
= ALL_CPU_MASK
;
1395 s
->irq_target
[irq
] = value
& ALL_CPU_MASK
;
1397 } else if (offset
< 0xf00) {
1398 /* Interrupt Configuration. */
1399 irq
= (offset
- 0xc00) * 4;
1400 if (irq
>= s
->num_irq
)
1402 if (irq
< GIC_NR_SGIS
)
1404 for (i
= 0; i
< 4; i
++) {
1405 if (s
->security_extn
&& !attrs
.secure
&&
1406 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
1407 continue; /* Ignore Non-secure access of Group0 IRQ */
1410 if (s
->revision
== REV_11MPCORE
) {
1411 if (value
& (1 << (i
* 2))) {
1412 GIC_DIST_SET_MODEL(irq
+ i
);
1414 GIC_DIST_CLEAR_MODEL(irq
+ i
);
1417 if (value
& (2 << (i
* 2))) {
1418 GIC_DIST_SET_EDGE_TRIGGER(irq
+ i
);
1420 GIC_DIST_CLEAR_EDGE_TRIGGER(irq
+ i
);
1423 } else if (offset
< 0xf10) {
1424 /* 0xf00 is only handled for 32-bit writes. */
1426 } else if (offset
< 0xf20) {
1427 /* GICD_CPENDSGIRn */
1428 if (s
->revision
== REV_11MPCORE
) {
1431 irq
= (offset
- 0xf10);
1433 if (!s
->security_extn
|| attrs
.secure
||
1434 GIC_DIST_TEST_GROUP(irq
, 1 << cpu
)) {
1435 s
->sgi_pending
[irq
][cpu
] &= ~value
;
1436 if (s
->sgi_pending
[irq
][cpu
] == 0) {
1437 GIC_DIST_CLEAR_PENDING(irq
, 1 << cpu
);
1440 } else if (offset
< 0xf30) {
1441 /* GICD_SPENDSGIRn */
1442 if (s
->revision
== REV_11MPCORE
) {
1445 irq
= (offset
- 0xf20);
1447 if (!s
->security_extn
|| attrs
.secure
||
1448 GIC_DIST_TEST_GROUP(irq
, 1 << cpu
)) {
1449 GIC_DIST_SET_PENDING(irq
, 1 << cpu
);
1450 s
->sgi_pending
[irq
][cpu
] |= value
;
1458 qemu_log_mask(LOG_GUEST_ERROR
,
1459 "gic_dist_writeb: Bad offset %x\n", (int)offset
);
1462 static void gic_dist_writew(void *opaque
, hwaddr offset
,
1463 uint32_t value
, MemTxAttrs attrs
)
1465 gic_dist_writeb(opaque
, offset
, value
& 0xff, attrs
);
1466 gic_dist_writeb(opaque
, offset
+ 1, value
>> 8, attrs
);
1469 static void gic_dist_writel(void *opaque
, hwaddr offset
,
1470 uint32_t value
, MemTxAttrs attrs
)
1472 GICState
*s
= (GICState
*)opaque
;
1473 if (offset
== 0xf00) {
1479 cpu
= gic_get_current_cpu(s
);
1481 switch ((value
>> 24) & 3) {
1483 mask
= (value
>> 16) & ALL_CPU_MASK
;
1486 mask
= ALL_CPU_MASK
^ (1 << cpu
);
1492 DPRINTF("Bad Soft Int target filter\n");
1493 mask
= ALL_CPU_MASK
;
1496 GIC_DIST_SET_PENDING(irq
, mask
);
1497 target_cpu
= ctz32(mask
);
1498 while (target_cpu
< GIC_NCPU
) {
1499 s
->sgi_pending
[irq
][target_cpu
] |= (1 << cpu
);
1500 mask
&= ~(1 << target_cpu
);
1501 target_cpu
= ctz32(mask
);
1506 gic_dist_writew(opaque
, offset
, value
& 0xffff, attrs
);
1507 gic_dist_writew(opaque
, offset
+ 2, value
>> 16, attrs
);
1510 static MemTxResult
gic_dist_write(void *opaque
, hwaddr offset
, uint64_t data
,
1511 unsigned size
, MemTxAttrs attrs
)
1513 trace_gic_dist_write(offset
, size
, data
);
1517 gic_dist_writeb(opaque
, offset
, data
, attrs
);
1520 gic_dist_writew(opaque
, offset
, data
, attrs
);
1523 gic_dist_writel(opaque
, offset
, data
, attrs
);
1530 static inline uint32_t gic_apr_ns_view(GICState
*s
, int cpu
, int regno
)
1532 /* Return the Nonsecure view of GICC_APR<regno>. This is the
1533 * second half of GICC_NSAPR.
1535 switch (GIC_MIN_BPR
) {
1538 return s
->nsapr
[regno
+ 2][cpu
];
1543 return s
->nsapr
[regno
+ 1][cpu
];
1548 return extract32(s
->nsapr
[0][cpu
], 16, 16);
1553 return extract32(s
->nsapr
[0][cpu
], 8, 8);
1557 g_assert_not_reached();
1562 static inline void gic_apr_write_ns_view(GICState
*s
, int cpu
, int regno
,
1565 /* Write the Nonsecure view of GICC_APR<regno>. */
1566 switch (GIC_MIN_BPR
) {
1569 s
->nsapr
[regno
+ 2][cpu
] = value
;
1574 s
->nsapr
[regno
+ 1][cpu
] = value
;
1579 s
->nsapr
[0][cpu
] = deposit32(s
->nsapr
[0][cpu
], 16, 16, value
);
1584 s
->nsapr
[0][cpu
] = deposit32(s
->nsapr
[0][cpu
], 8, 8, value
);
1588 g_assert_not_reached();
1592 static MemTxResult
gic_cpu_read(GICState
*s
, int cpu
, int offset
,
1593 uint64_t *data
, MemTxAttrs attrs
)
1596 case 0x00: /* Control */
1597 *data
= gic_get_cpu_control(s
, cpu
, attrs
);
1599 case 0x04: /* Priority mask */
1600 *data
= gic_get_priority_mask(s
, cpu
, attrs
);
1602 case 0x08: /* Binary Point */
1603 if (gic_cpu_ns_access(s
, cpu
, attrs
)) {
1604 if (s
->cpu_ctlr
[cpu
] & GICC_CTLR_CBPR
) {
1605 /* NS view of BPR when CBPR is 1 */
1606 *data
= MIN(s
->bpr
[cpu
] + 1, 7);
1608 /* BPR is banked. Non-secure copy stored in ABPR. */
1609 *data
= s
->abpr
[cpu
];
1612 *data
= s
->bpr
[cpu
];
1615 case 0x0c: /* Acknowledge */
1616 *data
= gic_acknowledge_irq(s
, cpu
, attrs
);
1618 case 0x14: /* Running Priority */
1619 *data
= gic_get_running_priority(s
, cpu
, attrs
);
1621 case 0x18: /* Highest Pending Interrupt */
1622 *data
= gic_get_current_pending_irq(s
, cpu
, attrs
);
1624 case 0x1c: /* Aliased Binary Point */
1625 /* GIC v2, no security: ABPR
1626 * GIC v1, no security: not implemented (RAZ/WI)
1627 * With security extensions, secure access: ABPR (alias of NS BPR)
1628 * With security extensions, nonsecure access: RAZ/WI
1630 if (!gic_has_groups(s
) || (gic_cpu_ns_access(s
, cpu
, attrs
))) {
1633 *data
= s
->abpr
[cpu
];
1636 case 0xd0: case 0xd4: case 0xd8: case 0xdc:
1638 int regno
= (offset
- 0xd0) / 4;
1639 int nr_aprs
= gic_is_vcpu(cpu
) ? GIC_VIRT_NR_APRS
: GIC_NR_APRS
;
1641 if (regno
>= nr_aprs
|| s
->revision
!= 2) {
1643 } else if (gic_is_vcpu(cpu
)) {
1644 *data
= s
->h_apr
[gic_get_vcpu_real_id(cpu
)];
1645 } else if (gic_cpu_ns_access(s
, cpu
, attrs
)) {
1646 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */
1647 *data
= gic_apr_ns_view(s
, regno
, cpu
);
1649 *data
= s
->apr
[regno
][cpu
];
1653 case 0xe0: case 0xe4: case 0xe8: case 0xec:
1655 int regno
= (offset
- 0xe0) / 4;
1657 if (regno
>= GIC_NR_APRS
|| s
->revision
!= 2 || !gic_has_groups(s
) ||
1658 gic_cpu_ns_access(s
, cpu
, attrs
) || gic_is_vcpu(cpu
)) {
1661 *data
= s
->nsapr
[regno
][cpu
];
1666 qemu_log_mask(LOG_GUEST_ERROR
,
1667 "gic_cpu_read: Bad offset %x\n", (int)offset
);
1672 trace_gic_cpu_read(gic_is_vcpu(cpu
) ? "vcpu" : "cpu",
1673 gic_get_vcpu_real_id(cpu
), offset
, *data
);
1677 static MemTxResult
gic_cpu_write(GICState
*s
, int cpu
, int offset
,
1678 uint32_t value
, MemTxAttrs attrs
)
1680 trace_gic_cpu_write(gic_is_vcpu(cpu
) ? "vcpu" : "cpu",
1681 gic_get_vcpu_real_id(cpu
), offset
, value
);
1684 case 0x00: /* Control */
1685 gic_set_cpu_control(s
, cpu
, value
, attrs
);
1687 case 0x04: /* Priority mask */
1688 gic_set_priority_mask(s
, cpu
, value
, attrs
);
1690 case 0x08: /* Binary Point */
1691 if (gic_cpu_ns_access(s
, cpu
, attrs
)) {
1692 if (s
->cpu_ctlr
[cpu
] & GICC_CTLR_CBPR
) {
1693 /* WI when CBPR is 1 */
1696 s
->abpr
[cpu
] = MAX(value
& 0x7, GIC_MIN_ABPR
);
1699 int min_bpr
= gic_is_vcpu(cpu
) ? GIC_VIRT_MIN_BPR
: GIC_MIN_BPR
;
1700 s
->bpr
[cpu
] = MAX(value
& 0x7, min_bpr
);
1703 case 0x10: /* End Of Interrupt */
1704 gic_complete_irq(s
, cpu
, value
& 0x3ff, attrs
);
1706 case 0x1c: /* Aliased Binary Point */
1707 if (!gic_has_groups(s
) || (gic_cpu_ns_access(s
, cpu
, attrs
))) {
1708 /* unimplemented, or NS access: RAZ/WI */
1711 s
->abpr
[cpu
] = MAX(value
& 0x7, GIC_MIN_ABPR
);
1714 case 0xd0: case 0xd4: case 0xd8: case 0xdc:
1716 int regno
= (offset
- 0xd0) / 4;
1717 int nr_aprs
= gic_is_vcpu(cpu
) ? GIC_VIRT_NR_APRS
: GIC_NR_APRS
;
1719 if (regno
>= nr_aprs
|| s
->revision
!= 2) {
1722 if (gic_is_vcpu(cpu
)) {
1723 s
->h_apr
[gic_get_vcpu_real_id(cpu
)] = value
;
1724 } else if (gic_cpu_ns_access(s
, cpu
, attrs
)) {
1725 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */
1726 gic_apr_write_ns_view(s
, regno
, cpu
, value
);
1728 s
->apr
[regno
][cpu
] = value
;
1732 case 0xe0: case 0xe4: case 0xe8: case 0xec:
1734 int regno
= (offset
- 0xe0) / 4;
1736 if (regno
>= GIC_NR_APRS
|| s
->revision
!= 2) {
1739 if (gic_is_vcpu(cpu
)) {
1742 if (!gic_has_groups(s
) || (gic_cpu_ns_access(s
, cpu
, attrs
))) {
1745 s
->nsapr
[regno
][cpu
] = value
;
1750 gic_deactivate_irq(s
, cpu
, value
& 0x3ff, attrs
);
1753 qemu_log_mask(LOG_GUEST_ERROR
,
1754 "gic_cpu_write: Bad offset %x\n", (int)offset
);
1758 if (gic_is_vcpu(cpu
)) {
1767 /* Wrappers to read/write the GIC CPU interface for the current CPU */
1768 static MemTxResult
gic_thiscpu_read(void *opaque
, hwaddr addr
, uint64_t *data
,
1769 unsigned size
, MemTxAttrs attrs
)
1771 GICState
*s
= (GICState
*)opaque
;
1772 return gic_cpu_read(s
, gic_get_current_cpu(s
), addr
, data
, attrs
);
1775 static MemTxResult
gic_thiscpu_write(void *opaque
, hwaddr addr
,
1776 uint64_t value
, unsigned size
,
1779 GICState
*s
= (GICState
*)opaque
;
1780 return gic_cpu_write(s
, gic_get_current_cpu(s
), addr
, value
, attrs
);
1783 /* Wrappers to read/write the GIC CPU interface for a specific CPU.
1784 * These just decode the opaque pointer into GICState* + cpu id.
1786 static MemTxResult
gic_do_cpu_read(void *opaque
, hwaddr addr
, uint64_t *data
,
1787 unsigned size
, MemTxAttrs attrs
)
1789 GICState
**backref
= (GICState
**)opaque
;
1790 GICState
*s
= *backref
;
1791 int id
= (backref
- s
->backref
);
1792 return gic_cpu_read(s
, id
, addr
, data
, attrs
);
1795 static MemTxResult
gic_do_cpu_write(void *opaque
, hwaddr addr
,
1796 uint64_t value
, unsigned size
,
1799 GICState
**backref
= (GICState
**)opaque
;
1800 GICState
*s
= *backref
;
1801 int id
= (backref
- s
->backref
);
1802 return gic_cpu_write(s
, id
, addr
, value
, attrs
);
1805 static MemTxResult
gic_thisvcpu_read(void *opaque
, hwaddr addr
, uint64_t *data
,
1806 unsigned size
, MemTxAttrs attrs
)
1808 GICState
*s
= (GICState
*)opaque
;
1810 return gic_cpu_read(s
, gic_get_current_vcpu(s
), addr
, data
, attrs
);
1813 static MemTxResult
gic_thisvcpu_write(void *opaque
, hwaddr addr
,
1814 uint64_t value
, unsigned size
,
1817 GICState
*s
= (GICState
*)opaque
;
1819 return gic_cpu_write(s
, gic_get_current_vcpu(s
), addr
, value
, attrs
);
1822 static uint32_t gic_compute_eisr(GICState
*s
, int cpu
, int lr_start
)
1827 for (lr_idx
= lr_start
; lr_idx
< s
->num_lrs
; lr_idx
++) {
1828 uint32_t *entry
= &s
->h_lr
[lr_idx
][cpu
];
1829 ret
= deposit32(ret
, lr_idx
- lr_start
, 1,
1830 gic_lr_entry_is_eoi(*entry
));
1836 static uint32_t gic_compute_elrsr(GICState
*s
, int cpu
, int lr_start
)
1841 for (lr_idx
= lr_start
; lr_idx
< s
->num_lrs
; lr_idx
++) {
1842 uint32_t *entry
= &s
->h_lr
[lr_idx
][cpu
];
1843 ret
= deposit32(ret
, lr_idx
- lr_start
, 1,
1844 gic_lr_entry_is_free(*entry
));
1850 static void gic_vmcr_write(GICState
*s
, uint32_t value
, MemTxAttrs attrs
)
1852 int vcpu
= gic_get_current_vcpu(s
);
1858 ctlr
= FIELD_EX32(value
, GICH_VMCR
, VMCCtlr
);
1859 abpr
= FIELD_EX32(value
, GICH_VMCR
, VMABP
);
1860 bpr
= FIELD_EX32(value
, GICH_VMCR
, VMBP
);
1861 prio_mask
= FIELD_EX32(value
, GICH_VMCR
, VMPriMask
) << 3;
1863 gic_set_cpu_control(s
, vcpu
, ctlr
, attrs
);
1864 s
->abpr
[vcpu
] = MAX(abpr
, GIC_VIRT_MIN_ABPR
);
1865 s
->bpr
[vcpu
] = MAX(bpr
, GIC_VIRT_MIN_BPR
);
1866 gic_set_priority_mask(s
, vcpu
, prio_mask
, attrs
);
1869 static MemTxResult
gic_hyp_read(void *opaque
, int cpu
, hwaddr addr
,
1870 uint64_t *data
, MemTxAttrs attrs
)
1872 GICState
*s
= ARM_GIC(opaque
);
1873 int vcpu
= cpu
+ GIC_NCPU
;
1876 case A_GICH_HCR
: /* Hypervisor Control */
1877 *data
= s
->h_hcr
[cpu
];
1880 case A_GICH_VTR
: /* VGIC Type */
1881 *data
= FIELD_DP32(0, GICH_VTR
, ListRegs
, s
->num_lrs
- 1);
1882 *data
= FIELD_DP32(*data
, GICH_VTR
, PREbits
,
1883 GIC_VIRT_MAX_GROUP_PRIO_BITS
- 1);
1884 *data
= FIELD_DP32(*data
, GICH_VTR
, PRIbits
,
1885 (7 - GIC_VIRT_MIN_BPR
) - 1);
1888 case A_GICH_VMCR
: /* Virtual Machine Control */
1889 *data
= FIELD_DP32(0, GICH_VMCR
, VMCCtlr
,
1890 extract32(s
->cpu_ctlr
[vcpu
], 0, 10));
1891 *data
= FIELD_DP32(*data
, GICH_VMCR
, VMABP
, s
->abpr
[vcpu
]);
1892 *data
= FIELD_DP32(*data
, GICH_VMCR
, VMBP
, s
->bpr
[vcpu
]);
1893 *data
= FIELD_DP32(*data
, GICH_VMCR
, VMPriMask
,
1894 extract32(s
->priority_mask
[vcpu
], 3, 5));
1897 case A_GICH_MISR
: /* Maintenance Interrupt Status */
1898 *data
= s
->h_misr
[cpu
];
1901 case A_GICH_EISR0
: /* End of Interrupt Status 0 and 1 */
1903 *data
= gic_compute_eisr(s
, cpu
, (addr
- A_GICH_EISR0
) * 8);
1906 case A_GICH_ELRSR0
: /* Empty List Status 0 and 1 */
1908 *data
= gic_compute_elrsr(s
, cpu
, (addr
- A_GICH_ELRSR0
) * 8);
1911 case A_GICH_APR
: /* Active Priorities */
1912 *data
= s
->h_apr
[cpu
];
1915 case A_GICH_LR0
... A_GICH_LR63
: /* List Registers */
1917 int lr_idx
= (addr
- A_GICH_LR0
) / 4;
1919 if (lr_idx
> s
->num_lrs
) {
1922 *data
= s
->h_lr
[lr_idx
][cpu
];
1928 qemu_log_mask(LOG_GUEST_ERROR
,
1929 "gic_hyp_read: Bad offset %" HWADDR_PRIx
"\n", addr
);
1933 trace_gic_hyp_read(addr
, *data
);
1937 static MemTxResult
gic_hyp_write(void *opaque
, int cpu
, hwaddr addr
,
1938 uint64_t value
, MemTxAttrs attrs
)
1940 GICState
*s
= ARM_GIC(opaque
);
1941 int vcpu
= cpu
+ GIC_NCPU
;
1943 trace_gic_hyp_write(addr
, value
);
1946 case A_GICH_HCR
: /* Hypervisor Control */
1947 s
->h_hcr
[cpu
] = value
& GICH_HCR_MASK
;
1950 case A_GICH_VMCR
: /* Virtual Machine Control */
1951 gic_vmcr_write(s
, value
, attrs
);
1954 case A_GICH_APR
: /* Active Priorities */
1955 s
->h_apr
[cpu
] = value
;
1956 s
->running_priority
[vcpu
] = gic_get_prio_from_apr_bits(s
, vcpu
);
1959 case A_GICH_LR0
... A_GICH_LR63
: /* List Registers */
1961 int lr_idx
= (addr
- A_GICH_LR0
) / 4;
1963 if (lr_idx
> s
->num_lrs
) {
1967 s
->h_lr
[lr_idx
][cpu
] = value
& GICH_LR_MASK
;
1968 trace_gic_lr_entry(cpu
, lr_idx
, s
->h_lr
[lr_idx
][cpu
]);
1973 qemu_log_mask(LOG_GUEST_ERROR
,
1974 "gic_hyp_write: Bad offset %" HWADDR_PRIx
"\n", addr
);
1982 static MemTxResult
gic_thiscpu_hyp_read(void *opaque
, hwaddr addr
, uint64_t *data
,
1983 unsigned size
, MemTxAttrs attrs
)
1985 GICState
*s
= (GICState
*)opaque
;
1987 return gic_hyp_read(s
, gic_get_current_cpu(s
), addr
, data
, attrs
);
1990 static MemTxResult
gic_thiscpu_hyp_write(void *opaque
, hwaddr addr
,
1991 uint64_t value
, unsigned size
,
1994 GICState
*s
= (GICState
*)opaque
;
1996 return gic_hyp_write(s
, gic_get_current_cpu(s
), addr
, value
, attrs
);
1999 static MemTxResult
gic_do_hyp_read(void *opaque
, hwaddr addr
, uint64_t *data
,
2000 unsigned size
, MemTxAttrs attrs
)
2002 GICState
**backref
= (GICState
**)opaque
;
2003 GICState
*s
= *backref
;
2004 int id
= (backref
- s
->backref
);
2006 return gic_hyp_read(s
, id
, addr
, data
, attrs
);
2009 static MemTxResult
gic_do_hyp_write(void *opaque
, hwaddr addr
,
2010 uint64_t value
, unsigned size
,
2013 GICState
**backref
= (GICState
**)opaque
;
2014 GICState
*s
= *backref
;
2015 int id
= (backref
- s
->backref
);
2017 return gic_hyp_write(s
, id
+ GIC_NCPU
, addr
, value
, attrs
);
2021 static const MemoryRegionOps gic_ops
[2] = {
2023 .read_with_attrs
= gic_dist_read
,
2024 .write_with_attrs
= gic_dist_write
,
2025 .endianness
= DEVICE_NATIVE_ENDIAN
,
2028 .read_with_attrs
= gic_thiscpu_read
,
2029 .write_with_attrs
= gic_thiscpu_write
,
2030 .endianness
= DEVICE_NATIVE_ENDIAN
,
2034 static const MemoryRegionOps gic_cpu_ops
= {
2035 .read_with_attrs
= gic_do_cpu_read
,
2036 .write_with_attrs
= gic_do_cpu_write
,
2037 .endianness
= DEVICE_NATIVE_ENDIAN
,
2040 static const MemoryRegionOps gic_virt_ops
[2] = {
2042 .read_with_attrs
= gic_thiscpu_hyp_read
,
2043 .write_with_attrs
= gic_thiscpu_hyp_write
,
2044 .endianness
= DEVICE_NATIVE_ENDIAN
,
2047 .read_with_attrs
= gic_thisvcpu_read
,
2048 .write_with_attrs
= gic_thisvcpu_write
,
2049 .endianness
= DEVICE_NATIVE_ENDIAN
,
2053 static const MemoryRegionOps gic_viface_ops
= {
2054 .read_with_attrs
= gic_do_hyp_read
,
2055 .write_with_attrs
= gic_do_hyp_write
,
2056 .endianness
= DEVICE_NATIVE_ENDIAN
,
2059 static void arm_gic_realize(DeviceState
*dev
, Error
**errp
)
2061 /* Device instance realize function for the GIC sysbus device */
2063 GICState
*s
= ARM_GIC(dev
);
2064 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
2065 ARMGICClass
*agc
= ARM_GIC_GET_CLASS(s
);
2066 Error
*local_err
= NULL
;
2068 agc
->parent_realize(dev
, &local_err
);
2070 error_propagate(errp
, local_err
);
2074 if (kvm_enabled() && !kvm_arm_supports_user_irq()) {
2075 error_setg(errp
, "KVM with user space irqchip only works when the "
2076 "host kernel supports KVM_CAP_ARM_USER_IRQ");
2080 if (s
->n_prio_bits
> GIC_MAX_PRIORITY_BITS
||
2081 (s
->virt_extn
? s
->n_prio_bits
< GIC_VIRT_MAX_GROUP_PRIO_BITS
:
2082 s
->n_prio_bits
< GIC_MIN_PRIORITY_BITS
)) {
2083 error_setg(errp
, "num-priority-bits cannot be greater than %d"
2084 " or less than %d", GIC_MAX_PRIORITY_BITS
,
2085 s
->virt_extn
? GIC_VIRT_MAX_GROUP_PRIO_BITS
:
2086 GIC_MIN_PRIORITY_BITS
);
2090 /* This creates distributor, main CPU interface (s->cpuiomem[0]) and if
2091 * enabled, virtualization extensions related interfaces (main virtual
2092 * interface (s->vifaceiomem[0]) and virtual CPU interface).
2094 gic_init_irqs_and_mmio(s
, gic_set_irq
, gic_ops
, gic_virt_ops
);
2096 /* Extra core-specific regions for the CPU interfaces. This is
2097 * necessary for "franken-GIC" implementations, for example on
2099 * NB that the memory region size of 0x100 applies for the 11MPCore
2100 * and also cores following the GIC v1 spec (ie A9).
2101 * GIC v2 defines a larger memory region (0x1000) so this will need
2102 * to be extended when we implement A15.
2104 for (i
= 0; i
< s
->num_cpu
; i
++) {
2106 memory_region_init_io(&s
->cpuiomem
[i
+1], OBJECT(s
), &gic_cpu_ops
,
2107 &s
->backref
[i
], "gic_cpu", 0x100);
2108 sysbus_init_mmio(sbd
, &s
->cpuiomem
[i
+1]);
2111 /* Extra core-specific regions for virtual interfaces. This is required by
2112 * the GICv2 specification.
2115 for (i
= 0; i
< s
->num_cpu
; i
++) {
2116 memory_region_init_io(&s
->vifaceiomem
[i
+ 1], OBJECT(s
),
2117 &gic_viface_ops
, &s
->backref
[i
],
2118 "gic_viface", 0x200);
2119 sysbus_init_mmio(sbd
, &s
->vifaceiomem
[i
+ 1]);
2125 static void arm_gic_class_init(ObjectClass
*klass
, void *data
)
2127 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2128 ARMGICClass
*agc
= ARM_GIC_CLASS(klass
);
2130 device_class_set_parent_realize(dc
, arm_gic_realize
, &agc
->parent_realize
);
2133 static const TypeInfo arm_gic_info
= {
2134 .name
= TYPE_ARM_GIC
,
2135 .parent
= TYPE_ARM_GIC_COMMON
,
2136 .instance_size
= sizeof(GICState
),
2137 .class_init
= arm_gic_class_init
,
2138 .class_size
= sizeof(ARMGICClass
),
2141 static void arm_gic_register_types(void)
2143 type_register_static(&arm_gic_info
);
2146 type_init(arm_gic_register_types
)