hw/arm/xlnx-zynqmp.c

   1 /*
   2  * Xilinx Zynq MPSoC emulation
   3  *
   4  * Copyright (C) 2015 Xilinx Inc
   5  * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  15  * for more details.
  16  */
  17
  18 #include "qemu/osdep.h"
  19 #include "qapi/error.h"
  20 #include "qemu-common.h"
  21 #include "cpu.h"
  22 #include "hw/arm/xlnx-zynqmp.h"
  23 #include "hw/intc/arm_gic_common.h"
  24 #include "exec/address-spaces.h"
  25 #include "sysemu/kvm.h"
  26 #include "kvm_arm.h"
  27
  28 #define GIC_NUM_SPI_INTR 160
  29
  30 #define ARM_PHYS_TIMER_PPI  30
  31 #define ARM_VIRT_TIMER_PPI  27
  32
  33 #define GEM_REVISION        0x40070106
  34
  35 #define GIC_BASE_ADDR       0xf9000000
  36 #define GIC_DIST_ADDR       0xf9010000
  37 #define GIC_CPU_ADDR        0xf9020000
  38
  39 #define SATA_INTR           133
  40 #define SATA_ADDR           0xFD0C0000
  41 #define SATA_NUM_PORTS      2
  42
  43 #define QSPI_ADDR           0xff0f0000
  44 #define LQSPI_ADDR          0xc0000000
  45 #define QSPI_IRQ            15
  46
  47 #define DP_ADDR             0xfd4a0000
  48 #define DP_IRQ              113
  49
  50 #define DPDMA_ADDR          0xfd4c0000
  51 #define DPDMA_IRQ           116
  52
  53 #define IPI_ADDR            0xFF300000
  54 #define IPI_IRQ             64
  55
  56 #define SDHCI_CAPABILITIES  0x280737ec6481 /* Datasheet: UG1085 (v1.7) */
  57
  58 static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
  59     0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
  60 };
  61
  62 static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = {
  63     57, 59, 61, 63,
  64 };
  65
  66 static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = {
  67     0xFF000000, 0xFF010000,
  68 };
  69
  70 static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
  71     21, 22,
  72 };
  73
  74 static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = {
  75     0xFF160000, 0xFF170000,
  76 };
  77
  78 static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = {
  79     48, 49,
  80 };
  81
  82 static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = {
  83     0xFF040000, 0xFF050000,
  84 };
  85
  86 static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = {
  87     19, 20,
  88 };
  89
  90 typedef struct XlnxZynqMPGICRegion {
  91     int region_index;
  92     uint32_t address;
  93 } XlnxZynqMPGICRegion;
  94
  95 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = {
  96     { .region_index = 0, .address = GIC_DIST_ADDR, },
  97     { .region_index = 1, .address = GIC_CPU_ADDR,  },
  98 };
  99
 100 static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
 101 {
 102     return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index;
 103 }
 104
 105 static void xlnx_zynqmp_create_rpu(XlnxZynqMPState *s, const char *boot_cpu,
 106                                    Error **errp)
 107 {
 108     Error *err = NULL;
 109     int i;
 110     int num_rpus = MIN(smp_cpus - XLNX_ZYNQMP_NUM_APU_CPUS, XLNX_ZYNQMP_NUM_RPU_CPUS);
 111
 112     for (i = 0; i < num_rpus; i++) {
 113         char *name;
 114
 115         object_initialize(&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]),
 116                           "cortex-r5-" TYPE_ARM_CPU);
 117         object_property_add_child(OBJECT(s), "rpu-cpu[*]",
 118                                   OBJECT(&s->rpu_cpu[i]), &error_abort);
 119
 120         name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i]));
 121         if (strcmp(name, boot_cpu)) {
 122             /* Secondary CPUs start in PSCI powered-down state */
 123             object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true,
 124                                      "start-powered-off", &error_abort);
 125         } else {
 126             s->boot_cpu_ptr = &s->rpu_cpu[i];
 127         }
 128         g_free(name);
 129
 130         object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "reset-hivecs",
 131                                  &error_abort);
 132         object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "realized",
 133                                  &err);
 134         if (err) {
 135             error_propagate(errp, err);
 136             return;
 137         }
 138     }
 139 }
 140
 141 static void xlnx_zynqmp_init(Object *obj)
 142 {
 143     XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
 144     int i;
 145     int num_apus = MIN(smp_cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
 146
 147     for (i = 0; i < num_apus; i++) {
 148         object_initialize(&s->apu_cpu[i], sizeof(s->apu_cpu[i]),
 149                           "cortex-a53-" TYPE_ARM_CPU);
 150         object_property_add_child(obj, "apu-cpu[*]", OBJECT(&s->apu_cpu[i]),
 151                                   &error_abort);
 152     }
 153
 154     object_initialize(&s->gic, sizeof(s->gic), gic_class_name());
 155     qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());
 156
 157     for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
 158         object_initialize(&s->gem[i], sizeof(s->gem[i]), TYPE_CADENCE_GEM);
 159         qdev_set_parent_bus(DEVICE(&s->gem[i]), sysbus_get_default());
 160     }
 161
 162     for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
 163         object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_CADENCE_UART);
 164         qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
 165     }
 166
 167     object_initialize(&s->sata, sizeof(s->sata), TYPE_SYSBUS_AHCI);
 168     qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default());
 169
 170     for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
 171         object_initialize(&s->sdhci[i], sizeof(s->sdhci[i]),
 172                           TYPE_SYSBUS_SDHCI);
 173         qdev_set_parent_bus(DEVICE(&s->sdhci[i]),
 174                             sysbus_get_default());
 175     }
 176
 177     for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
 178         object_initialize(&s->spi[i], sizeof(s->spi[i]),
 179                           TYPE_XILINX_SPIPS);
 180         qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
 181     }
 182
 183     object_initialize(&s->qspi, sizeof(s->qspi), TYPE_XLNX_ZYNQMP_QSPIPS);
 184     qdev_set_parent_bus(DEVICE(&s->qspi), sysbus_get_default());
 185
 186     object_initialize(&s->dp, sizeof(s->dp), TYPE_XLNX_DP);
 187     qdev_set_parent_bus(DEVICE(&s->dp), sysbus_get_default());
 188
 189     object_initialize(&s->dpdma, sizeof(s->dpdma), TYPE_XLNX_DPDMA);
 190     qdev_set_parent_bus(DEVICE(&s->dpdma), sysbus_get_default());
 191
 192     object_initialize(&s->ipi, sizeof(s->ipi), TYPE_XLNX_ZYNQMP_IPI);
 193     qdev_set_parent_bus(DEVICE(&s->ipi), sysbus_get_default());
 194 }
 195
 196 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
 197 {
 198     XlnxZynqMPState *s = XLNX_ZYNQMP(dev);
 199     MemoryRegion *system_memory = get_system_memory();
 200     uint8_t i;
 201     uint64_t ram_size;
 202     int num_apus = MIN(smp_cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
 203     const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]";
 204     ram_addr_t ddr_low_size, ddr_high_size;
 205     qemu_irq gic_spi[GIC_NUM_SPI_INTR];
 206     Error *err = NULL;
 207
 208     ram_size = memory_region_size(s->ddr_ram);
 209
 210     /* Create the DDR Memory Regions. User friendly checks should happen at
 211      * the board level
 212      */
 213     if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) {
 214         /* The RAM size is above the maximum available for the low DDR.
 215          * Create the high DDR memory region as well.
 216          */
 217         assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE);
 218         ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
 219         ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
 220
 221         memory_region_init_alias(&s->ddr_ram_high, NULL,
 222                                  "ddr-ram-high", s->ddr_ram,
 223                                   ddr_low_size, ddr_high_size);
 224         memory_region_add_subregion(get_system_memory(),
 225                                     XLNX_ZYNQMP_HIGH_RAM_START,
 226                                     &s->ddr_ram_high);
 227     } else {
 228         /* RAM must be non-zero */
 229         assert(ram_size);
 230         ddr_low_size = ram_size;
 231     }
 232
 233     memory_region_init_alias(&s->ddr_ram_low, NULL,
 234                              "ddr-ram-low", s->ddr_ram,
 235                               0, ddr_low_size);
 236     memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low);
 237
 238     /* Create the four OCM banks */
 239     for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) {
 240         char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i);
 241
 242         memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name,
 243                                XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal);
 244         memory_region_add_subregion(get_system_memory(),
 245                                     XLNX_ZYNQMP_OCM_RAM_0_ADDRESS +
 246                                         i * XLNX_ZYNQMP_OCM_RAM_SIZE,
 247                                     &s->ocm_ram[i]);
 248
 249         g_free(ocm_name);
 250     }
 251
 252     qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
 253     qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
 254     qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", num_apus);
 255
 256     /* Realize APUs before realizing the GIC. KVM requires this.  */
 257     for (i = 0; i < num_apus; i++) {
 258         char *name;
 259
 260         object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC,
 261                                 "psci-conduit", &error_abort);
 262
 263         name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i]));
 264         if (strcmp(name, boot_cpu)) {
 265             /* Secondary CPUs start in PSCI powered-down state */
 266             object_property_set_bool(OBJECT(&s->apu_cpu[i]), true,
 267                                      "start-powered-off", &error_abort);
 268         } else {
 269             s->boot_cpu_ptr = &s->apu_cpu[i];
 270         }
 271         g_free(name);
 272
 273         object_property_set_bool(OBJECT(&s->apu_cpu[i]),
 274                                  s->secure, "has_el3", NULL);
 275         object_property_set_bool(OBJECT(&s->apu_cpu[i]),
 276                                  s->virt, "has_el2", NULL);
 277         object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR,
 278                                 "reset-cbar", &error_abort);
 279         object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized",
 280                                  &err);
 281         if (err) {
 282             error_propagate(errp, err);
 283             return;
 284         }
 285     }
 286
 287     object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
 288     if (err) {
 289         error_propagate(errp, err);
 290         return;
 291     }
 292
 293     assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS);
 294     for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) {
 295         SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic);
 296         const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i];
 297         MemoryRegion *mr = sysbus_mmio_get_region(gic, r->region_index);
 298         uint32_t addr = r->address;
 299         int j;
 300
 301         sysbus_mmio_map(gic, r->region_index, addr);
 302
 303         for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) {
 304             MemoryRegion *alias = &s->gic_mr[i][j];
 305
 306             addr += XLNX_ZYNQMP_GIC_REGION_SIZE;
 307             memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr,
 308                                      0, XLNX_ZYNQMP_GIC_REGION_SIZE);
 309             memory_region_add_subregion(system_memory, addr, alias);
 310         }
 311     }
 312
 313     for (i = 0; i < num_apus; i++) {
 314         qemu_irq irq;
 315
 316         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
 317                            qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
 318                                             ARM_CPU_IRQ));
 319         irq = qdev_get_gpio_in(DEVICE(&s->gic),
 320                                arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI));
 321         qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 0, irq);
 322         irq = qdev_get_gpio_in(DEVICE(&s->gic),
 323                                arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI));
 324         qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 1, irq);
 325     }
 326
 327     if (s->has_rpu) {
 328         info_report("The 'has_rpu' property is no longer required, to use the "
 329                     "RPUs just use -smp 6.");
 330     }
 331
 332     xlnx_zynqmp_create_rpu(s, boot_cpu, &err);
 333     if (err) {
 334         error_propagate(errp, err);
 335         return;
 336     }
 337
 338     if (!s->boot_cpu_ptr) {
 339         error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu);
 340         return;
 341     }
 342
 343     for (i = 0; i < GIC_NUM_SPI_INTR; i++) {
 344         gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i);
 345     }
 346
 347     for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
 348         NICInfo *nd = &nd_table[i];
 349
 350         if (nd->used) {
 351             qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
 352             qdev_set_nic_properties(DEVICE(&s->gem[i]), nd);
 353         }
 354         object_property_set_int(OBJECT(&s->gem[i]), GEM_REVISION, "revision",
 355                                 &error_abort);
 356         object_property_set_int(OBJECT(&s->gem[i]), 2, "num-priority-queues",
 357                                 &error_abort);
 358         object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err);
 359         if (err) {
 360             error_propagate(errp, err);
 361             return;
 362         }
 363         sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]);
 364         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0,
 365                            gic_spi[gem_intr[i]]);
 366     }
 367
 368     for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
 369         qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hds[i]);
 370         object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
 371         if (err) {
 372             error_propagate(errp, err);
 373             return;
 374         }
 375         sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]);
 376         sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
 377                            gic_spi[uart_intr[i]]);
 378     }
 379
 380     object_property_set_int(OBJECT(&s->sata), SATA_NUM_PORTS, "num-ports",
 381                             &error_abort);
 382     object_property_set_bool(OBJECT(&s->sata), true, "realized", &err);
 383     if (err) {
 384         error_propagate(errp, err);
 385         return;
 386     }
 387
 388     sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR);
 389     sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]);
 390
 391     for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
 392         char *bus_name = g_strdup_printf("sd-bus%d", i);
 393         SysBusDevice *sbd = SYS_BUS_DEVICE(&s->sdhci[i]);
 394         Object *sdhci = OBJECT(&s->sdhci[i]);
 395
 396         /* Compatible with:
 397          * - SD Host Controller Specification Version 3.00
 398          * - SDIO Specification Version 3.0
 399          * - eMMC Specification Version 4.51
 400          */
 401         object_property_set_uint(sdhci, 3, "sd-spec-version", &err);
 402         object_property_set_uint(sdhci, SDHCI_CAPABILITIES, "capareg", &err);
 403         object_property_set_uint(sdhci, UHS_I, "uhs", &err);
 404         object_property_set_bool(sdhci, true, "realized", &err);
 405         if (err) {
 406             error_propagate(errp, err);
 407             return;
 408         }
 409         sysbus_mmio_map(sbd, 0, sdhci_addr[i]);
 410         sysbus_connect_irq(sbd, 0, gic_spi[sdhci_intr[i]]);
 411
 412         /* Alias controller SD bus to the SoC itself */
 413         object_property_add_alias(OBJECT(s), bus_name, sdhci, "sd-bus",
 414                                   &error_abort);
 415         g_free(bus_name);
 416     }
 417
 418     for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
 419         gchar *bus_name;
 420
 421         object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
 422
 423         sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
 424         sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
 425                            gic_spi[spi_intr[i]]);
 426
 427         /* Alias controller SPI bus to the SoC itself */
 428         bus_name = g_strdup_printf("spi%d", i);
 429         object_property_add_alias(OBJECT(s), bus_name,
 430                                   OBJECT(&s->spi[i]), "spi0",
 431                                   &error_abort);
 432         g_free(bus_name);
 433     }
 434
 435     object_property_set_bool(OBJECT(&s->qspi), true, "realized", &err);
 436     sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 0, QSPI_ADDR);
 437     sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 1, LQSPI_ADDR);
 438     sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi), 0, gic_spi[QSPI_IRQ]);
 439
 440     for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_BUS; i++) {
 441         gchar *bus_name;
 442         gchar *target_bus;
 443
 444         /* Alias controller SPI bus to the SoC itself */
 445         bus_name = g_strdup_printf("qspi%d", i);
 446         target_bus = g_strdup_printf("spi%d", i);
 447         object_property_add_alias(OBJECT(s), bus_name,
 448                                   OBJECT(&s->qspi), target_bus,
 449                                   &error_abort);
 450         g_free(bus_name);
 451         g_free(target_bus);
 452     }
 453
 454     object_property_set_bool(OBJECT(&s->dp), true, "realized", &err);
 455     if (err) {
 456         error_propagate(errp, err);
 457         return;
 458     }
 459     sysbus_mmio_map(SYS_BUS_DEVICE(&s->dp), 0, DP_ADDR);
 460     sysbus_connect_irq(SYS_BUS_DEVICE(&s->dp), 0, gic_spi[DP_IRQ]);
 461
 462     object_property_set_bool(OBJECT(&s->dpdma), true, "realized", &err);
 463     if (err) {
 464         error_propagate(errp, err);
 465         return;
 466     }
 467     object_property_set_link(OBJECT(&s->dp), OBJECT(&s->dpdma), "dpdma",
 468                              &error_abort);
 469     sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR);
 470     sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]);
 471
 472     object_property_set_bool(OBJECT(&s->ipi), true, "realized", &err);
 473     if (err) {
 474         error_propagate(errp, err);
 475         return;
 476     }
 477     sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi), 0, IPI_ADDR);
 478     sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi), 0, gic_spi[IPI_IRQ]);
 479 }
 480
 481 static Property xlnx_zynqmp_props[] = {
 482     DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu),
 483     DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false),
 484     DEFINE_PROP_BOOL("virtualization", XlnxZynqMPState, virt, false),
 485     DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false),
 486     DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION,
 487                      MemoryRegion *),
 488     DEFINE_PROP_END_OF_LIST()
 489 };
 490
 491 static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data)
 492 {
 493     DeviceClass *dc = DEVICE_CLASS(oc);
 494
 495     dc->props = xlnx_zynqmp_props;
 496     dc->realize = xlnx_zynqmp_realize;
 497     /* Reason: Uses serial_hds in realize function, thus can't be used twice */
 498     dc->user_creatable = false;
 499 }
 500
 501 static const TypeInfo xlnx_zynqmp_type_info = {
 502     .name = TYPE_XLNX_ZYNQMP,
 503     .parent = TYPE_DEVICE,
 504     .instance_size = sizeof(XlnxZynqMPState),
 505     .instance_init = xlnx_zynqmp_init,
 506     .class_init = xlnx_zynqmp_class_init,
 507 };
 508
 509 static void xlnx_zynqmp_register_types(void)
 510 {
 511     type_register_static(&xlnx_zynqmp_type_info);
 512 }
 513
 514 type_init(xlnx_zynqmp_register_types)