2 * ARM mach-virt emulation
4 * Copyright (c) 2013 Linaro Limited
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
18 * Emulate a virtual board which works by passing Linux all the information
19 * it needs about what devices are present via the device tree.
20 * There are some restrictions about what we can do here:
21 * + we can only present devices whose Linux drivers will work based
22 * purely on the device tree with no platform data at all
23 * + we want to present a very stripped-down minimalist platform,
24 * both because this reduces the security attack surface from the guest
25 * and also because it reduces our exposure to being broken when
26 * the kernel updates its device tree bindings and requires further
27 * information in a device binding that we aren't providing.
28 * This is essentially the same approach kvmtool uses.
31 #include "qemu/osdep.h"
32 #include "qemu-common.h"
33 #include "qemu/units.h"
34 #include "qemu/option.h"
35 #include "monitor/qdev.h"
36 #include "qapi/error.h"
37 #include "hw/sysbus.h"
38 #include "hw/boards.h"
39 #include "hw/arm/boot.h"
40 #include "hw/arm/primecell.h"
41 #include "hw/arm/virt.h"
42 #include "hw/block/flash.h"
43 #include "hw/vfio/vfio-calxeda-xgmac.h"
44 #include "hw/vfio/vfio-amd-xgbe.h"
45 #include "hw/display/ramfb.h"
47 #include "sysemu/device_tree.h"
48 #include "sysemu/numa.h"
49 #include "sysemu/runstate.h"
50 #include "sysemu/sysemu.h"
51 #include "sysemu/tpm.h"
52 #include "sysemu/kvm.h"
53 #include "hw/loader.h"
54 #include "exec/address-spaces.h"
55 #include "qemu/bitops.h"
56 #include "qemu/error-report.h"
57 #include "qemu/module.h"
58 #include "hw/pci-host/gpex.h"
59 #include "hw/virtio/virtio-pci.h"
60 #include "hw/arm/sysbus-fdt.h"
61 #include "hw/platform-bus.h"
62 #include "hw/qdev-properties.h"
63 #include "hw/arm/fdt.h"
64 #include "hw/intc/arm_gic.h"
65 #include "hw/intc/arm_gicv3_common.h"
68 #include "hw/firmware/smbios.h"
69 #include "qapi/visitor.h"
70 #include "qapi/qapi-visit-common.h"
71 #include "standard-headers/linux/input.h"
72 #include "hw/arm/smmuv3.h"
73 #include "hw/acpi/acpi.h"
74 #include "target/arm/internals.h"
75 #include "hw/mem/pc-dimm.h"
76 #include "hw/mem/nvdimm.h"
77 #include "hw/acpi/generic_event_device.h"
78 #include "hw/virtio/virtio-iommu.h"
79 #include "hw/char/pl011.h"
81 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
82 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
85 MachineClass *mc = MACHINE_CLASS(oc); \
86 virt_machine_##major##_##minor##_options(mc); \
87 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \
92 static const TypeInfo machvirt_##major##_##minor##_info = { \
93 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \
94 .parent = TYPE_VIRT_MACHINE, \
95 .class_init = virt_##major##_##minor##_class_init, \
97 static void machvirt_machine_##major##_##minor##_init(void) \
99 type_register_static(&machvirt_##major##_##minor##_info); \
101 type_init(machvirt_machine_##major##_##minor##_init);
103 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
104 DEFINE_VIRT_MACHINE_LATEST(major, minor, true)
105 #define DEFINE_VIRT_MACHINE(major, minor) \
106 DEFINE_VIRT_MACHINE_LATEST(major, minor, false)
109 /* Number of external interrupt lines to configure the GIC with */
112 #define PLATFORM_BUS_NUM_IRQS 64
114 /* Legacy RAM limit in GB (< version 4.0) */
115 #define LEGACY_RAMLIMIT_GB 255
116 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB)
118 /* Addresses and sizes of our components.
119 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
120 * 128MB..256MB is used for miscellaneous device I/O.
121 * 256MB..1GB is reserved for possible future PCI support (ie where the
122 * PCI memory window will go if we add a PCI host controller).
123 * 1GB and up is RAM (which may happily spill over into the
124 * high memory region beyond 4GB).
125 * This represents a compromise between how much RAM can be given to
126 * a 32 bit VM and leaving space for expansion and in particular for PCI.
127 * Note that devices should generally be placed at multiples of 0x10000,
128 * to accommodate guests using 64K pages.
130 static const MemMapEntry base_memmap
[] = {
131 /* Space up to 0x8000000 is reserved for a boot ROM */
132 [VIRT_FLASH
] = { 0, 0x08000000 },
133 [VIRT_CPUPERIPHS
] = { 0x08000000, 0x00020000 },
134 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
135 [VIRT_GIC_DIST
] = { 0x08000000, 0x00010000 },
136 [VIRT_GIC_CPU
] = { 0x08010000, 0x00010000 },
137 [VIRT_GIC_V2M
] = { 0x08020000, 0x00001000 },
138 [VIRT_GIC_HYP
] = { 0x08030000, 0x00010000 },
139 [VIRT_GIC_VCPU
] = { 0x08040000, 0x00010000 },
140 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */
141 [VIRT_GIC_ITS
] = { 0x08080000, 0x00020000 },
142 /* This redistributor space allows up to 2*64kB*123 CPUs */
143 [VIRT_GIC_REDIST
] = { 0x080A0000, 0x00F60000 },
144 [VIRT_UART
] = { 0x09000000, 0x00001000 },
145 [VIRT_RTC
] = { 0x09010000, 0x00001000 },
146 [VIRT_FW_CFG
] = { 0x09020000, 0x00000018 },
147 [VIRT_GPIO
] = { 0x09030000, 0x00001000 },
148 [VIRT_SECURE_UART
] = { 0x09040000, 0x00001000 },
149 [VIRT_SMMU
] = { 0x09050000, 0x00020000 },
150 [VIRT_PCDIMM_ACPI
] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN
},
151 [VIRT_ACPI_GED
] = { 0x09080000, ACPI_GED_EVT_SEL_LEN
},
152 [VIRT_MMIO
] = { 0x0a000000, 0x00000200 },
153 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
154 [VIRT_PLATFORM_BUS
] = { 0x0c000000, 0x02000000 },
155 [VIRT_SECURE_MEM
] = { 0x0e000000, 0x01000000 },
156 [VIRT_PCIE_MMIO
] = { 0x10000000, 0x2eff0000 },
157 [VIRT_PCIE_PIO
] = { 0x3eff0000, 0x00010000 },
158 [VIRT_PCIE_ECAM
] = { 0x3f000000, 0x01000000 },
159 /* Actual RAM size depends on initial RAM and device memory settings */
160 [VIRT_MEM
] = { GiB
, LEGACY_RAMLIMIT_BYTES
},
164 * Highmem IO Regions: This memory map is floating, located after the RAM.
165 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the
166 * top of the RAM, so that its base get the same alignment as the size,
167 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is
168 * less than 256GiB of RAM, the floating area starts at the 256GiB mark.
169 * Note the extended_memmap is sized so that it eventually also includes the
170 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last
171 * index of base_memmap).
173 static MemMapEntry extended_memmap
[] = {
174 /* Additional 64 MB redist region (can contain up to 512 redistributors) */
175 [VIRT_HIGH_GIC_REDIST2
] = { 0x0, 64 * MiB
},
176 [VIRT_HIGH_PCIE_ECAM
] = { 0x0, 256 * MiB
},
177 /* Second PCIe window */
178 [VIRT_HIGH_PCIE_MMIO
] = { 0x0, 512 * GiB
},
181 static const int a15irqmap
[] = {
184 [VIRT_PCIE
] = 3, /* ... to 6 */
186 [VIRT_SECURE_UART
] = 8,
188 [VIRT_MMIO
] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
189 [VIRT_GIC_V2M
] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
190 [VIRT_SMMU
] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */
191 [VIRT_PLATFORM_BUS
] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
194 static const char *valid_cpus
[] = {
195 ARM_CPU_TYPE_NAME("cortex-a7"),
196 ARM_CPU_TYPE_NAME("cortex-a15"),
197 ARM_CPU_TYPE_NAME("cortex-a53"),
198 ARM_CPU_TYPE_NAME("cortex-a57"),
199 ARM_CPU_TYPE_NAME("cortex-a72"),
200 ARM_CPU_TYPE_NAME("host"),
201 ARM_CPU_TYPE_NAME("max"),
204 static bool cpu_type_valid(const char *cpu
)
208 for (i
= 0; i
< ARRAY_SIZE(valid_cpus
); i
++) {
209 if (strcmp(cpu
, valid_cpus
[i
]) == 0) {
216 static void create_fdt(VirtMachineState
*vms
)
218 MachineState
*ms
= MACHINE(vms
);
219 int nb_numa_nodes
= ms
->numa_state
->num_nodes
;
220 void *fdt
= create_device_tree(&vms
->fdt_size
);
223 error_report("create_device_tree() failed");
230 qemu_fdt_setprop_string(fdt
, "/", "compatible", "linux,dummy-virt");
231 qemu_fdt_setprop_cell(fdt
, "/", "#address-cells", 0x2);
232 qemu_fdt_setprop_cell(fdt
, "/", "#size-cells", 0x2);
234 /* /chosen must exist for load_dtb to fill in necessary properties later */
235 qemu_fdt_add_subnode(fdt
, "/chosen");
238 qemu_fdt_add_subnode(fdt
, "/secure-chosen");
241 /* Clock node, for the benefit of the UART. The kernel device tree
242 * binding documentation claims the PL011 node clock properties are
243 * optional but in practice if you omit them the kernel refuses to
244 * probe for the device.
246 vms
->clock_phandle
= qemu_fdt_alloc_phandle(fdt
);
247 qemu_fdt_add_subnode(fdt
, "/apb-pclk");
248 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "compatible", "fixed-clock");
249 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "#clock-cells", 0x0);
250 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "clock-frequency", 24000000);
251 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "clock-output-names",
253 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "phandle", vms
->clock_phandle
);
255 if (nb_numa_nodes
> 0 && ms
->numa_state
->have_numa_distance
) {
256 int size
= nb_numa_nodes
* nb_numa_nodes
* 3 * sizeof(uint32_t);
257 uint32_t *matrix
= g_malloc0(size
);
260 for (i
= 0; i
< nb_numa_nodes
; i
++) {
261 for (j
= 0; j
< nb_numa_nodes
; j
++) {
262 idx
= (i
* nb_numa_nodes
+ j
) * 3;
263 matrix
[idx
+ 0] = cpu_to_be32(i
);
264 matrix
[idx
+ 1] = cpu_to_be32(j
);
266 cpu_to_be32(ms
->numa_state
->nodes
[i
].distance
[j
]);
270 qemu_fdt_add_subnode(fdt
, "/distance-map");
271 qemu_fdt_setprop_string(fdt
, "/distance-map", "compatible",
272 "numa-distance-map-v1");
273 qemu_fdt_setprop(fdt
, "/distance-map", "distance-matrix",
279 static void fdt_add_timer_nodes(const VirtMachineState
*vms
)
281 /* On real hardware these interrupts are level-triggered.
282 * On KVM they were edge-triggered before host kernel version 4.4,
283 * and level-triggered afterwards.
284 * On emulated QEMU they are level-triggered.
286 * Getting the DTB info about them wrong is awkward for some
288 * pre-4.8 ignore the DT and leave the interrupt configured
289 * with whatever the GIC reset value (or the bootloader) left it at
290 * 4.8 before rc6 honour the incorrect data by programming it back
291 * into the GIC, causing problems
292 * 4.8rc6 and later ignore the DT and always write "level triggered"
295 * For backwards-compatibility, virt-2.8 and earlier will continue
296 * to say these are edge-triggered, but later machines will report
297 * the correct information.
300 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
301 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
303 if (vmc
->claim_edge_triggered_timers
) {
304 irqflags
= GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
;
307 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
308 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
309 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
310 (1 << vms
->smp_cpus
) - 1);
313 qemu_fdt_add_subnode(vms
->fdt
, "/timer");
315 armcpu
= ARM_CPU(qemu_get_cpu(0));
316 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
317 const char compat
[] = "arm,armv8-timer\0arm,armv7-timer";
318 qemu_fdt_setprop(vms
->fdt
, "/timer", "compatible",
319 compat
, sizeof(compat
));
321 qemu_fdt_setprop_string(vms
->fdt
, "/timer", "compatible",
324 qemu_fdt_setprop(vms
->fdt
, "/timer", "always-on", NULL
, 0);
325 qemu_fdt_setprop_cells(vms
->fdt
, "/timer", "interrupts",
326 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_S_EL1_IRQ
, irqflags
,
327 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_NS_EL1_IRQ
, irqflags
,
328 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_VIRT_IRQ
, irqflags
,
329 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_NS_EL2_IRQ
, irqflags
);
332 static void fdt_add_cpu_nodes(const VirtMachineState
*vms
)
336 const MachineState
*ms
= MACHINE(vms
);
339 * From Documentation/devicetree/bindings/arm/cpus.txt
340 * On ARM v8 64-bit systems value should be set to 2,
341 * that corresponds to the MPIDR_EL1 register size.
342 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
343 * in the system, #address-cells can be set to 1, since
344 * MPIDR_EL1[63:32] bits are not used for CPUs
347 * Here we actually don't know whether our system is 32- or 64-bit one.
348 * The simplest way to go is to examine affinity IDs of all our CPUs. If
349 * at least one of them has Aff3 populated, we set #address-cells to 2.
351 for (cpu
= 0; cpu
< vms
->smp_cpus
; cpu
++) {
352 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
354 if (armcpu
->mp_affinity
& ARM_AFF3_MASK
) {
360 qemu_fdt_add_subnode(vms
->fdt
, "/cpus");
361 qemu_fdt_setprop_cell(vms
->fdt
, "/cpus", "#address-cells", addr_cells
);
362 qemu_fdt_setprop_cell(vms
->fdt
, "/cpus", "#size-cells", 0x0);
364 for (cpu
= vms
->smp_cpus
- 1; cpu
>= 0; cpu
--) {
365 char *nodename
= g_strdup_printf("/cpus/cpu@%d", cpu
);
366 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
367 CPUState
*cs
= CPU(armcpu
);
369 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
370 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "device_type", "cpu");
371 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible",
372 armcpu
->dtb_compatible
);
374 if (vms
->psci_conduit
!= QEMU_PSCI_CONDUIT_DISABLED
375 && vms
->smp_cpus
> 1) {
376 qemu_fdt_setprop_string(vms
->fdt
, nodename
,
377 "enable-method", "psci");
380 if (addr_cells
== 2) {
381 qemu_fdt_setprop_u64(vms
->fdt
, nodename
, "reg",
382 armcpu
->mp_affinity
);
384 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "reg",
385 armcpu
->mp_affinity
);
388 if (ms
->possible_cpus
->cpus
[cs
->cpu_index
].props
.has_node_id
) {
389 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "numa-node-id",
390 ms
->possible_cpus
->cpus
[cs
->cpu_index
].props
.node_id
);
397 static void fdt_add_its_gic_node(VirtMachineState
*vms
)
401 vms
->msi_phandle
= qemu_fdt_alloc_phandle(vms
->fdt
);
402 nodename
= g_strdup_printf("/intc/its@%" PRIx64
,
403 vms
->memmap
[VIRT_GIC_ITS
].base
);
404 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
405 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible",
407 qemu_fdt_setprop(vms
->fdt
, nodename
, "msi-controller", NULL
, 0);
408 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
409 2, vms
->memmap
[VIRT_GIC_ITS
].base
,
410 2, vms
->memmap
[VIRT_GIC_ITS
].size
);
411 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "phandle", vms
->msi_phandle
);
415 static void fdt_add_v2m_gic_node(VirtMachineState
*vms
)
419 nodename
= g_strdup_printf("/intc/v2m@%" PRIx64
,
420 vms
->memmap
[VIRT_GIC_V2M
].base
);
421 vms
->msi_phandle
= qemu_fdt_alloc_phandle(vms
->fdt
);
422 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
423 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible",
424 "arm,gic-v2m-frame");
425 qemu_fdt_setprop(vms
->fdt
, nodename
, "msi-controller", NULL
, 0);
426 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
427 2, vms
->memmap
[VIRT_GIC_V2M
].base
,
428 2, vms
->memmap
[VIRT_GIC_V2M
].size
);
429 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "phandle", vms
->msi_phandle
);
433 static void fdt_add_gic_node(VirtMachineState
*vms
)
437 vms
->gic_phandle
= qemu_fdt_alloc_phandle(vms
->fdt
);
438 qemu_fdt_setprop_cell(vms
->fdt
, "/", "interrupt-parent", vms
->gic_phandle
);
440 nodename
= g_strdup_printf("/intc@%" PRIx64
,
441 vms
->memmap
[VIRT_GIC_DIST
].base
);
442 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
443 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#interrupt-cells", 3);
444 qemu_fdt_setprop(vms
->fdt
, nodename
, "interrupt-controller", NULL
, 0);
445 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#address-cells", 0x2);
446 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#size-cells", 0x2);
447 qemu_fdt_setprop(vms
->fdt
, nodename
, "ranges", NULL
, 0);
448 if (vms
->gic_version
== VIRT_GIC_VERSION_3
) {
449 int nb_redist_regions
= virt_gicv3_redist_region_count(vms
);
451 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible",
454 qemu_fdt_setprop_cell(vms
->fdt
, nodename
,
455 "#redistributor-regions", nb_redist_regions
);
457 if (nb_redist_regions
== 1) {
458 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
459 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
460 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
461 2, vms
->memmap
[VIRT_GIC_REDIST
].base
,
462 2, vms
->memmap
[VIRT_GIC_REDIST
].size
);
464 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
465 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
466 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
467 2, vms
->memmap
[VIRT_GIC_REDIST
].base
,
468 2, vms
->memmap
[VIRT_GIC_REDIST
].size
,
469 2, vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].base
,
470 2, vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].size
);
474 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupts",
475 GIC_FDT_IRQ_TYPE_PPI
, ARCH_GIC_MAINT_IRQ
,
476 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
479 /* 'cortex-a15-gic' means 'GIC v2' */
480 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible",
481 "arm,cortex-a15-gic");
483 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
484 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
485 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
486 2, vms
->memmap
[VIRT_GIC_CPU
].base
,
487 2, vms
->memmap
[VIRT_GIC_CPU
].size
);
489 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
490 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
491 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
492 2, vms
->memmap
[VIRT_GIC_CPU
].base
,
493 2, vms
->memmap
[VIRT_GIC_CPU
].size
,
494 2, vms
->memmap
[VIRT_GIC_HYP
].base
,
495 2, vms
->memmap
[VIRT_GIC_HYP
].size
,
496 2, vms
->memmap
[VIRT_GIC_VCPU
].base
,
497 2, vms
->memmap
[VIRT_GIC_VCPU
].size
);
498 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupts",
499 GIC_FDT_IRQ_TYPE_PPI
, ARCH_GIC_MAINT_IRQ
,
500 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
504 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "phandle", vms
->gic_phandle
);
508 static void fdt_add_pmu_nodes(const VirtMachineState
*vms
)
512 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
515 armcpu
= ARM_CPU(cpu
);
516 if (!arm_feature(&armcpu
->env
, ARM_FEATURE_PMU
)) {
520 if (kvm_irqchip_in_kernel()) {
521 kvm_arm_pmu_set_irq(cpu
, PPI(VIRTUAL_PMU_IRQ
));
523 kvm_arm_pmu_init(cpu
);
527 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
528 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
529 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
530 (1 << vms
->smp_cpus
) - 1);
533 armcpu
= ARM_CPU(qemu_get_cpu(0));
534 qemu_fdt_add_subnode(vms
->fdt
, "/pmu");
535 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
536 const char compat
[] = "arm,armv8-pmuv3";
537 qemu_fdt_setprop(vms
->fdt
, "/pmu", "compatible",
538 compat
, sizeof(compat
));
539 qemu_fdt_setprop_cells(vms
->fdt
, "/pmu", "interrupts",
540 GIC_FDT_IRQ_TYPE_PPI
, VIRTUAL_PMU_IRQ
, irqflags
);
544 static inline DeviceState
*create_acpi_ged(VirtMachineState
*vms
)
547 MachineState
*ms
= MACHINE(vms
);
548 int irq
= vms
->irqmap
[VIRT_ACPI_GED
];
549 uint32_t event
= ACPI_GED_PWR_DOWN_EVT
;
552 event
|= ACPI_GED_MEM_HOTPLUG_EVT
;
555 dev
= qdev_create(NULL
, TYPE_ACPI_GED
);
556 qdev_prop_set_uint32(dev
, "ged-event", event
);
558 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_ACPI_GED
].base
);
559 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 1, vms
->memmap
[VIRT_PCDIMM_ACPI
].base
);
560 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0, qdev_get_gpio_in(vms
->gic
, irq
));
562 qdev_init_nofail(dev
);
567 static void create_its(VirtMachineState
*vms
)
569 const char *itsclass
= its_class_name();
573 /* Do nothing if not supported */
577 dev
= qdev_create(NULL
, itsclass
);
579 object_property_set_link(OBJECT(dev
), OBJECT(vms
->gic
), "parent-gicv3",
581 qdev_init_nofail(dev
);
582 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_GIC_ITS
].base
);
584 fdt_add_its_gic_node(vms
);
587 static void create_v2m(VirtMachineState
*vms
)
590 int irq
= vms
->irqmap
[VIRT_GIC_V2M
];
593 dev
= qdev_create(NULL
, "arm-gicv2m");
594 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_GIC_V2M
].base
);
595 qdev_prop_set_uint32(dev
, "base-spi", irq
);
596 qdev_prop_set_uint32(dev
, "num-spi", NUM_GICV2M_SPIS
);
597 qdev_init_nofail(dev
);
599 for (i
= 0; i
< NUM_GICV2M_SPIS
; i
++) {
600 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
601 qdev_get_gpio_in(vms
->gic
, irq
+ i
));
604 fdt_add_v2m_gic_node(vms
);
607 static void create_gic(VirtMachineState
*vms
)
609 MachineState
*ms
= MACHINE(vms
);
610 /* We create a standalone GIC */
611 SysBusDevice
*gicbusdev
;
613 int type
= vms
->gic_version
, i
;
614 unsigned int smp_cpus
= ms
->smp
.cpus
;
615 uint32_t nb_redist_regions
= 0;
617 gictype
= (type
== 3) ? gicv3_class_name() : gic_class_name();
619 vms
->gic
= qdev_create(NULL
, gictype
);
620 qdev_prop_set_uint32(vms
->gic
, "revision", type
);
621 qdev_prop_set_uint32(vms
->gic
, "num-cpu", smp_cpus
);
622 /* Note that the num-irq property counts both internal and external
623 * interrupts; there are always 32 of the former (mandated by GIC spec).
625 qdev_prop_set_uint32(vms
->gic
, "num-irq", NUM_IRQS
+ 32);
626 if (!kvm_irqchip_in_kernel()) {
627 qdev_prop_set_bit(vms
->gic
, "has-security-extensions", vms
->secure
);
631 uint32_t redist0_capacity
=
632 vms
->memmap
[VIRT_GIC_REDIST
].size
/ GICV3_REDIST_SIZE
;
633 uint32_t redist0_count
= MIN(smp_cpus
, redist0_capacity
);
635 nb_redist_regions
= virt_gicv3_redist_region_count(vms
);
637 qdev_prop_set_uint32(vms
->gic
, "len-redist-region-count",
639 qdev_prop_set_uint32(vms
->gic
, "redist-region-count[0]", redist0_count
);
641 if (nb_redist_regions
== 2) {
642 uint32_t redist1_capacity
=
643 vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].size
/ GICV3_REDIST_SIZE
;
645 qdev_prop_set_uint32(vms
->gic
, "redist-region-count[1]",
646 MIN(smp_cpus
- redist0_count
, redist1_capacity
));
649 if (!kvm_irqchip_in_kernel()) {
650 qdev_prop_set_bit(vms
->gic
, "has-virtualization-extensions",
654 qdev_init_nofail(vms
->gic
);
655 gicbusdev
= SYS_BUS_DEVICE(vms
->gic
);
656 sysbus_mmio_map(gicbusdev
, 0, vms
->memmap
[VIRT_GIC_DIST
].base
);
658 sysbus_mmio_map(gicbusdev
, 1, vms
->memmap
[VIRT_GIC_REDIST
].base
);
659 if (nb_redist_regions
== 2) {
660 sysbus_mmio_map(gicbusdev
, 2,
661 vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].base
);
664 sysbus_mmio_map(gicbusdev
, 1, vms
->memmap
[VIRT_GIC_CPU
].base
);
666 sysbus_mmio_map(gicbusdev
, 2, vms
->memmap
[VIRT_GIC_HYP
].base
);
667 sysbus_mmio_map(gicbusdev
, 3, vms
->memmap
[VIRT_GIC_VCPU
].base
);
671 /* Wire the outputs from each CPU's generic timer and the GICv3
672 * maintenance interrupt signal to the appropriate GIC PPI inputs,
673 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
675 for (i
= 0; i
< smp_cpus
; i
++) {
676 DeviceState
*cpudev
= DEVICE(qemu_get_cpu(i
));
677 int ppibase
= NUM_IRQS
+ i
* GIC_INTERNAL
+ GIC_NR_SGIS
;
679 /* Mapping from the output timer irq lines from the CPU to the
680 * GIC PPI inputs we use for the virt board.
682 const int timer_irq
[] = {
683 [GTIMER_PHYS
] = ARCH_TIMER_NS_EL1_IRQ
,
684 [GTIMER_VIRT
] = ARCH_TIMER_VIRT_IRQ
,
685 [GTIMER_HYP
] = ARCH_TIMER_NS_EL2_IRQ
,
686 [GTIMER_SEC
] = ARCH_TIMER_S_EL1_IRQ
,
689 for (irq
= 0; irq
< ARRAY_SIZE(timer_irq
); irq
++) {
690 qdev_connect_gpio_out(cpudev
, irq
,
691 qdev_get_gpio_in(vms
->gic
,
692 ppibase
+ timer_irq
[irq
]));
696 qemu_irq irq
= qdev_get_gpio_in(vms
->gic
,
697 ppibase
+ ARCH_GIC_MAINT_IRQ
);
698 qdev_connect_gpio_out_named(cpudev
, "gicv3-maintenance-interrupt",
700 } else if (vms
->virt
) {
701 qemu_irq irq
= qdev_get_gpio_in(vms
->gic
,
702 ppibase
+ ARCH_GIC_MAINT_IRQ
);
703 sysbus_connect_irq(gicbusdev
, i
+ 4 * smp_cpus
, irq
);
706 qdev_connect_gpio_out_named(cpudev
, "pmu-interrupt", 0,
707 qdev_get_gpio_in(vms
->gic
, ppibase
710 sysbus_connect_irq(gicbusdev
, i
, qdev_get_gpio_in(cpudev
, ARM_CPU_IRQ
));
711 sysbus_connect_irq(gicbusdev
, i
+ smp_cpus
,
712 qdev_get_gpio_in(cpudev
, ARM_CPU_FIQ
));
713 sysbus_connect_irq(gicbusdev
, i
+ 2 * smp_cpus
,
714 qdev_get_gpio_in(cpudev
, ARM_CPU_VIRQ
));
715 sysbus_connect_irq(gicbusdev
, i
+ 3 * smp_cpus
,
716 qdev_get_gpio_in(cpudev
, ARM_CPU_VFIQ
));
719 fdt_add_gic_node(vms
);
721 if (type
== 3 && vms
->its
) {
723 } else if (type
== 2) {
728 static void create_uart(const VirtMachineState
*vms
, int uart
,
729 MemoryRegion
*mem
, Chardev
*chr
)
732 hwaddr base
= vms
->memmap
[uart
].base
;
733 hwaddr size
= vms
->memmap
[uart
].size
;
734 int irq
= vms
->irqmap
[uart
];
735 const char compat
[] = "arm,pl011\0arm,primecell";
736 const char clocknames
[] = "uartclk\0apb_pclk";
737 DeviceState
*dev
= qdev_create(NULL
, TYPE_PL011
);
738 SysBusDevice
*s
= SYS_BUS_DEVICE(dev
);
740 qdev_prop_set_chr(dev
, "chardev", chr
);
741 qdev_init_nofail(dev
);
742 memory_region_add_subregion(mem
, base
,
743 sysbus_mmio_get_region(s
, 0));
744 sysbus_connect_irq(s
, 0, qdev_get_gpio_in(vms
->gic
, irq
));
746 nodename
= g_strdup_printf("/pl011@%" PRIx64
, base
);
747 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
748 /* Note that we can't use setprop_string because of the embedded NUL */
749 qemu_fdt_setprop(vms
->fdt
, nodename
, "compatible",
750 compat
, sizeof(compat
));
751 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
753 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupts",
754 GIC_FDT_IRQ_TYPE_SPI
, irq
,
755 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
756 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "clocks",
757 vms
->clock_phandle
, vms
->clock_phandle
);
758 qemu_fdt_setprop(vms
->fdt
, nodename
, "clock-names",
759 clocknames
, sizeof(clocknames
));
761 if (uart
== VIRT_UART
) {
762 qemu_fdt_setprop_string(vms
->fdt
, "/chosen", "stdout-path", nodename
);
764 /* Mark as not usable by the normal world */
765 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "status", "disabled");
766 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "secure-status", "okay");
768 qemu_fdt_setprop_string(vms
->fdt
, "/secure-chosen", "stdout-path",
775 static void create_rtc(const VirtMachineState
*vms
)
778 hwaddr base
= vms
->memmap
[VIRT_RTC
].base
;
779 hwaddr size
= vms
->memmap
[VIRT_RTC
].size
;
780 int irq
= vms
->irqmap
[VIRT_RTC
];
781 const char compat
[] = "arm,pl031\0arm,primecell";
783 sysbus_create_simple("pl031", base
, qdev_get_gpio_in(vms
->gic
, irq
));
785 nodename
= g_strdup_printf("/pl031@%" PRIx64
, base
);
786 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
787 qemu_fdt_setprop(vms
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
788 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
790 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupts",
791 GIC_FDT_IRQ_TYPE_SPI
, irq
,
792 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
793 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "clocks", vms
->clock_phandle
);
794 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "clock-names", "apb_pclk");
798 static DeviceState
*gpio_key_dev
;
799 static void virt_powerdown_req(Notifier
*n
, void *opaque
)
801 VirtMachineState
*s
= container_of(n
, VirtMachineState
, powerdown_notifier
);
804 acpi_send_event(s
->acpi_dev
, ACPI_POWER_DOWN_STATUS
);
806 /* use gpio Pin 3 for power button event */
807 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev
, 0), 1);
811 static void create_gpio(const VirtMachineState
*vms
)
814 DeviceState
*pl061_dev
;
815 hwaddr base
= vms
->memmap
[VIRT_GPIO
].base
;
816 hwaddr size
= vms
->memmap
[VIRT_GPIO
].size
;
817 int irq
= vms
->irqmap
[VIRT_GPIO
];
818 const char compat
[] = "arm,pl061\0arm,primecell";
820 pl061_dev
= sysbus_create_simple("pl061", base
,
821 qdev_get_gpio_in(vms
->gic
, irq
));
823 uint32_t phandle
= qemu_fdt_alloc_phandle(vms
->fdt
);
824 nodename
= g_strdup_printf("/pl061@%" PRIx64
, base
);
825 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
826 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
828 qemu_fdt_setprop(vms
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
829 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#gpio-cells", 2);
830 qemu_fdt_setprop(vms
->fdt
, nodename
, "gpio-controller", NULL
, 0);
831 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupts",
832 GIC_FDT_IRQ_TYPE_SPI
, irq
,
833 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
834 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "clocks", vms
->clock_phandle
);
835 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "clock-names", "apb_pclk");
836 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "phandle", phandle
);
838 gpio_key_dev
= sysbus_create_simple("gpio-key", -1,
839 qdev_get_gpio_in(pl061_dev
, 3));
840 qemu_fdt_add_subnode(vms
->fdt
, "/gpio-keys");
841 qemu_fdt_setprop_string(vms
->fdt
, "/gpio-keys", "compatible", "gpio-keys");
842 qemu_fdt_setprop_cell(vms
->fdt
, "/gpio-keys", "#size-cells", 0);
843 qemu_fdt_setprop_cell(vms
->fdt
, "/gpio-keys", "#address-cells", 1);
845 qemu_fdt_add_subnode(vms
->fdt
, "/gpio-keys/poweroff");
846 qemu_fdt_setprop_string(vms
->fdt
, "/gpio-keys/poweroff",
847 "label", "GPIO Key Poweroff");
848 qemu_fdt_setprop_cell(vms
->fdt
, "/gpio-keys/poweroff", "linux,code",
850 qemu_fdt_setprop_cells(vms
->fdt
, "/gpio-keys/poweroff",
851 "gpios", phandle
, 3, 0);
855 static void create_virtio_devices(const VirtMachineState
*vms
)
858 hwaddr size
= vms
->memmap
[VIRT_MMIO
].size
;
860 /* We create the transports in forwards order. Since qbus_realize()
861 * prepends (not appends) new child buses, the incrementing loop below will
862 * create a list of virtio-mmio buses with decreasing base addresses.
864 * When a -device option is processed from the command line,
865 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards
866 * order. The upshot is that -device options in increasing command line
867 * order are mapped to virtio-mmio buses with decreasing base addresses.
869 * When this code was originally written, that arrangement ensured that the
870 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to
871 * the first -device on the command line. (The end-to-end order is a
872 * function of this loop, qbus_realize(), qbus_find_recursive(), and the
873 * guest kernel's name-to-address assignment strategy.)
875 * Meanwhile, the kernel's traversal seems to have been reversed; see eg.
876 * the message, if not necessarily the code, of commit 70161ff336.
877 * Therefore the loop now establishes the inverse of the original intent.
879 * Unfortunately, we can't counteract the kernel change by reversing the
880 * loop; it would break existing command lines.
882 * In any case, the kernel makes no guarantee about the stability of
883 * enumeration order of virtio devices (as demonstrated by it changing
884 * between kernel versions). For reliable and stable identification
885 * of disks users must use UUIDs or similar mechanisms.
887 for (i
= 0; i
< NUM_VIRTIO_TRANSPORTS
; i
++) {
888 int irq
= vms
->irqmap
[VIRT_MMIO
] + i
;
889 hwaddr base
= vms
->memmap
[VIRT_MMIO
].base
+ i
* size
;
891 sysbus_create_simple("virtio-mmio", base
,
892 qdev_get_gpio_in(vms
->gic
, irq
));
895 /* We add dtb nodes in reverse order so that they appear in the finished
896 * device tree lowest address first.
898 * Note that this mapping is independent of the loop above. The previous
899 * loop influences virtio device to virtio transport assignment, whereas
900 * this loop controls how virtio transports are laid out in the dtb.
902 for (i
= NUM_VIRTIO_TRANSPORTS
- 1; i
>= 0; i
--) {
904 int irq
= vms
->irqmap
[VIRT_MMIO
] + i
;
905 hwaddr base
= vms
->memmap
[VIRT_MMIO
].base
+ i
* size
;
907 nodename
= g_strdup_printf("/virtio_mmio@%" PRIx64
, base
);
908 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
909 qemu_fdt_setprop_string(vms
->fdt
, nodename
,
910 "compatible", "virtio,mmio");
911 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
913 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupts",
914 GIC_FDT_IRQ_TYPE_SPI
, irq
,
915 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
);
916 qemu_fdt_setprop(vms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
921 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
923 static PFlashCFI01
*virt_flash_create1(VirtMachineState
*vms
,
925 const char *alias_prop_name
)
928 * Create a single flash device. We use the same parameters as
929 * the flash devices on the Versatile Express board.
931 DeviceState
*dev
= qdev_create(NULL
, TYPE_PFLASH_CFI01
);
933 qdev_prop_set_uint64(dev
, "sector-length", VIRT_FLASH_SECTOR_SIZE
);
934 qdev_prop_set_uint8(dev
, "width", 4);
935 qdev_prop_set_uint8(dev
, "device-width", 2);
936 qdev_prop_set_bit(dev
, "big-endian", false);
937 qdev_prop_set_uint16(dev
, "id0", 0x89);
938 qdev_prop_set_uint16(dev
, "id1", 0x18);
939 qdev_prop_set_uint16(dev
, "id2", 0x00);
940 qdev_prop_set_uint16(dev
, "id3", 0x00);
941 qdev_prop_set_string(dev
, "name", name
);
942 object_property_add_child(OBJECT(vms
), name
, OBJECT(dev
),
944 object_property_add_alias(OBJECT(vms
), alias_prop_name
,
945 OBJECT(dev
), "drive", &error_abort
);
946 return PFLASH_CFI01(dev
);
949 static void virt_flash_create(VirtMachineState
*vms
)
951 vms
->flash
[0] = virt_flash_create1(vms
, "virt.flash0", "pflash0");
952 vms
->flash
[1] = virt_flash_create1(vms
, "virt.flash1", "pflash1");
955 static void virt_flash_map1(PFlashCFI01
*flash
,
956 hwaddr base
, hwaddr size
,
957 MemoryRegion
*sysmem
)
959 DeviceState
*dev
= DEVICE(flash
);
961 assert(size
% VIRT_FLASH_SECTOR_SIZE
== 0);
962 assert(size
/ VIRT_FLASH_SECTOR_SIZE
<= UINT32_MAX
);
963 qdev_prop_set_uint32(dev
, "num-blocks", size
/ VIRT_FLASH_SECTOR_SIZE
);
964 qdev_init_nofail(dev
);
966 memory_region_add_subregion(sysmem
, base
,
967 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
),
971 static void virt_flash_map(VirtMachineState
*vms
,
972 MemoryRegion
*sysmem
,
973 MemoryRegion
*secure_sysmem
)
976 * Map two flash devices to fill the VIRT_FLASH space in the memmap.
977 * sysmem is the system memory space. secure_sysmem is the secure view
978 * of the system, and the first flash device should be made visible only
979 * there. The second flash device is visible to both secure and nonsecure.
980 * If sysmem == secure_sysmem this means there is no separate Secure
981 * address space and both flash devices are generally visible.
983 hwaddr flashsize
= vms
->memmap
[VIRT_FLASH
].size
/ 2;
984 hwaddr flashbase
= vms
->memmap
[VIRT_FLASH
].base
;
986 virt_flash_map1(vms
->flash
[0], flashbase
, flashsize
,
988 virt_flash_map1(vms
->flash
[1], flashbase
+ flashsize
, flashsize
,
992 static void virt_flash_fdt(VirtMachineState
*vms
,
993 MemoryRegion
*sysmem
,
994 MemoryRegion
*secure_sysmem
)
996 hwaddr flashsize
= vms
->memmap
[VIRT_FLASH
].size
/ 2;
997 hwaddr flashbase
= vms
->memmap
[VIRT_FLASH
].base
;
1000 if (sysmem
== secure_sysmem
) {
1001 /* Report both flash devices as a single node in the DT */
1002 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
1003 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
1004 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible", "cfi-flash");
1005 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
1006 2, flashbase
, 2, flashsize
,
1007 2, flashbase
+ flashsize
, 2, flashsize
);
1008 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "bank-width", 4);
1012 * Report the devices as separate nodes so we can mark one as
1013 * only visible to the secure world.
1015 nodename
= g_strdup_printf("/secflash@%" PRIx64
, flashbase
);
1016 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
1017 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible", "cfi-flash");
1018 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
1019 2, flashbase
, 2, flashsize
);
1020 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "bank-width", 4);
1021 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "status", "disabled");
1022 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "secure-status", "okay");
1025 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
1026 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
1027 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible", "cfi-flash");
1028 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
1029 2, flashbase
+ flashsize
, 2, flashsize
);
1030 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "bank-width", 4);
1035 static bool virt_firmware_init(VirtMachineState
*vms
,
1036 MemoryRegion
*sysmem
,
1037 MemoryRegion
*secure_sysmem
)
1040 BlockBackend
*pflash_blk0
;
1042 /* Map legacy -drive if=pflash to machine properties */
1043 for (i
= 0; i
< ARRAY_SIZE(vms
->flash
); i
++) {
1044 pflash_cfi01_legacy_drive(vms
->flash
[i
],
1045 drive_get(IF_PFLASH
, 0, i
));
1048 virt_flash_map(vms
, sysmem
, secure_sysmem
);
1050 pflash_blk0
= pflash_cfi01_get_blk(vms
->flash
[0]);
1058 error_report("The contents of the first flash device may be "
1059 "specified with -bios or with -drive if=pflash... "
1060 "but you cannot use both options at once");
1064 /* Fall back to -bios */
1066 fname
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
1068 error_report("Could not find ROM image '%s'", bios_name
);
1071 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(vms
->flash
[0]), 0);
1072 image_size
= load_image_mr(fname
, mr
);
1074 if (image_size
< 0) {
1075 error_report("Could not load ROM image '%s'", bios_name
);
1080 return pflash_blk0
|| bios_name
;
1083 static FWCfgState
*create_fw_cfg(const VirtMachineState
*vms
, AddressSpace
*as
)
1085 MachineState
*ms
= MACHINE(vms
);
1086 hwaddr base
= vms
->memmap
[VIRT_FW_CFG
].base
;
1087 hwaddr size
= vms
->memmap
[VIRT_FW_CFG
].size
;
1091 fw_cfg
= fw_cfg_init_mem_wide(base
+ 8, base
, 8, base
+ 16, as
);
1092 fw_cfg_add_i16(fw_cfg
, FW_CFG_NB_CPUS
, (uint16_t)ms
->smp
.cpus
);
1094 nodename
= g_strdup_printf("/fw-cfg@%" PRIx64
, base
);
1095 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
1096 qemu_fdt_setprop_string(vms
->fdt
, nodename
,
1097 "compatible", "qemu,fw-cfg-mmio");
1098 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
1100 qemu_fdt_setprop(vms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1105 static void create_pcie_irq_map(const VirtMachineState
*vms
,
1106 uint32_t gic_phandle
,
1107 int first_irq
, const char *nodename
)
1110 uint32_t full_irq_map
[4 * 4 * 10] = { 0 };
1111 uint32_t *irq_map
= full_irq_map
;
1113 for (devfn
= 0; devfn
<= 0x18; devfn
+= 0x8) {
1114 for (pin
= 0; pin
< 4; pin
++) {
1115 int irq_type
= GIC_FDT_IRQ_TYPE_SPI
;
1116 int irq_nr
= first_irq
+ ((pin
+ PCI_SLOT(devfn
)) % PCI_NUM_PINS
);
1117 int irq_level
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
1121 devfn
<< 8, 0, 0, /* devfn */
1122 pin
+ 1, /* PCI pin */
1123 gic_phandle
, 0, 0, irq_type
, irq_nr
, irq_level
}; /* GIC irq */
1125 /* Convert map to big endian */
1126 for (i
= 0; i
< 10; i
++) {
1127 irq_map
[i
] = cpu_to_be32(map
[i
]);
1133 qemu_fdt_setprop(vms
->fdt
, nodename
, "interrupt-map",
1134 full_irq_map
, sizeof(full_irq_map
));
1136 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupt-map-mask",
1137 0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */
1141 static void create_smmu(const VirtMachineState
*vms
,
1145 const char compat
[] = "arm,smmu-v3";
1146 int irq
= vms
->irqmap
[VIRT_SMMU
];
1148 hwaddr base
= vms
->memmap
[VIRT_SMMU
].base
;
1149 hwaddr size
= vms
->memmap
[VIRT_SMMU
].size
;
1150 const char irq_names
[] = "eventq\0priq\0cmdq-sync\0gerror";
1153 if (vms
->iommu
!= VIRT_IOMMU_SMMUV3
|| !vms
->iommu_phandle
) {
1157 dev
= qdev_create(NULL
, "arm-smmuv3");
1159 object_property_set_link(OBJECT(dev
), OBJECT(bus
), "primary-bus",
1161 qdev_init_nofail(dev
);
1162 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, base
);
1163 for (i
= 0; i
< NUM_SMMU_IRQS
; i
++) {
1164 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
1165 qdev_get_gpio_in(vms
->gic
, irq
+ i
));
1168 node
= g_strdup_printf("/smmuv3@%" PRIx64
, base
);
1169 qemu_fdt_add_subnode(vms
->fdt
, node
);
1170 qemu_fdt_setprop(vms
->fdt
, node
, "compatible", compat
, sizeof(compat
));
1171 qemu_fdt_setprop_sized_cells(vms
->fdt
, node
, "reg", 2, base
, 2, size
);
1173 qemu_fdt_setprop_cells(vms
->fdt
, node
, "interrupts",
1174 GIC_FDT_IRQ_TYPE_SPI
, irq
, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1175 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1176 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1177 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
);
1179 qemu_fdt_setprop(vms
->fdt
, node
, "interrupt-names", irq_names
,
1182 qemu_fdt_setprop_cell(vms
->fdt
, node
, "clocks", vms
->clock_phandle
);
1183 qemu_fdt_setprop_string(vms
->fdt
, node
, "clock-names", "apb_pclk");
1184 qemu_fdt_setprop(vms
->fdt
, node
, "dma-coherent", NULL
, 0);
1186 qemu_fdt_setprop_cell(vms
->fdt
, node
, "#iommu-cells", 1);
1188 qemu_fdt_setprop_cell(vms
->fdt
, node
, "phandle", vms
->iommu_phandle
);
1192 static void create_virtio_iommu_dt_bindings(VirtMachineState
*vms
)
1194 const char compat
[] = "virtio,pci-iommu";
1195 uint16_t bdf
= vms
->virtio_iommu_bdf
;
1198 vms
->iommu_phandle
= qemu_fdt_alloc_phandle(vms
->fdt
);
1200 node
= g_strdup_printf("%s/virtio_iommu@%d", vms
->pciehb_nodename
, bdf
);
1201 qemu_fdt_add_subnode(vms
->fdt
, node
);
1202 qemu_fdt_setprop(vms
->fdt
, node
, "compatible", compat
, sizeof(compat
));
1203 qemu_fdt_setprop_sized_cells(vms
->fdt
, node
, "reg",
1204 1, bdf
<< 8, 1, 0, 1, 0,
1207 qemu_fdt_setprop_cell(vms
->fdt
, node
, "#iommu-cells", 1);
1208 qemu_fdt_setprop_cell(vms
->fdt
, node
, "phandle", vms
->iommu_phandle
);
1211 qemu_fdt_setprop_cells(vms
->fdt
, vms
->pciehb_nodename
, "iommu-map",
1212 0x0, vms
->iommu_phandle
, 0x0, bdf
,
1213 bdf
+ 1, vms
->iommu_phandle
, bdf
+ 1, 0xffff - bdf
);
1216 static void create_pcie(VirtMachineState
*vms
)
1218 hwaddr base_mmio
= vms
->memmap
[VIRT_PCIE_MMIO
].base
;
1219 hwaddr size_mmio
= vms
->memmap
[VIRT_PCIE_MMIO
].size
;
1220 hwaddr base_mmio_high
= vms
->memmap
[VIRT_HIGH_PCIE_MMIO
].base
;
1221 hwaddr size_mmio_high
= vms
->memmap
[VIRT_HIGH_PCIE_MMIO
].size
;
1222 hwaddr base_pio
= vms
->memmap
[VIRT_PCIE_PIO
].base
;
1223 hwaddr size_pio
= vms
->memmap
[VIRT_PCIE_PIO
].size
;
1224 hwaddr base_ecam
, size_ecam
;
1225 hwaddr base
= base_mmio
;
1227 int irq
= vms
->irqmap
[VIRT_PCIE
];
1228 MemoryRegion
*mmio_alias
;
1229 MemoryRegion
*mmio_reg
;
1230 MemoryRegion
*ecam_alias
;
1231 MemoryRegion
*ecam_reg
;
1237 dev
= qdev_create(NULL
, TYPE_GPEX_HOST
);
1238 qdev_init_nofail(dev
);
1240 ecam_id
= VIRT_ECAM_ID(vms
->highmem_ecam
);
1241 base_ecam
= vms
->memmap
[ecam_id
].base
;
1242 size_ecam
= vms
->memmap
[ecam_id
].size
;
1243 nr_pcie_buses
= size_ecam
/ PCIE_MMCFG_SIZE_MIN
;
1244 /* Map only the first size_ecam bytes of ECAM space */
1245 ecam_alias
= g_new0(MemoryRegion
, 1);
1246 ecam_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0);
1247 memory_region_init_alias(ecam_alias
, OBJECT(dev
), "pcie-ecam",
1248 ecam_reg
, 0, size_ecam
);
1249 memory_region_add_subregion(get_system_memory(), base_ecam
, ecam_alias
);
1251 /* Map the MMIO window into system address space so as to expose
1252 * the section of PCI MMIO space which starts at the same base address
1253 * (ie 1:1 mapping for that part of PCI MMIO space visible through
1256 mmio_alias
= g_new0(MemoryRegion
, 1);
1257 mmio_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 1);
1258 memory_region_init_alias(mmio_alias
, OBJECT(dev
), "pcie-mmio",
1259 mmio_reg
, base_mmio
, size_mmio
);
1260 memory_region_add_subregion(get_system_memory(), base_mmio
, mmio_alias
);
1263 /* Map high MMIO space */
1264 MemoryRegion
*high_mmio_alias
= g_new0(MemoryRegion
, 1);
1266 memory_region_init_alias(high_mmio_alias
, OBJECT(dev
), "pcie-mmio-high",
1267 mmio_reg
, base_mmio_high
, size_mmio_high
);
1268 memory_region_add_subregion(get_system_memory(), base_mmio_high
,
1272 /* Map IO port space */
1273 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 2, base_pio
);
1275 for (i
= 0; i
< GPEX_NUM_IRQS
; i
++) {
1276 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
1277 qdev_get_gpio_in(vms
->gic
, irq
+ i
));
1278 gpex_set_irq_num(GPEX_HOST(dev
), i
, irq
+ i
);
1281 pci
= PCI_HOST_BRIDGE(dev
);
1283 for (i
= 0; i
< nb_nics
; i
++) {
1284 NICInfo
*nd
= &nd_table
[i
];
1287 nd
->model
= g_strdup("virtio");
1290 pci_nic_init_nofail(nd
, pci
->bus
, nd
->model
, NULL
);
1294 nodename
= vms
->pciehb_nodename
= g_strdup_printf("/pcie@%" PRIx64
, base
);
1295 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
1296 qemu_fdt_setprop_string(vms
->fdt
, nodename
,
1297 "compatible", "pci-host-ecam-generic");
1298 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "device_type", "pci");
1299 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#address-cells", 3);
1300 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#size-cells", 2);
1301 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "linux,pci-domain", 0);
1302 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "bus-range", 0,
1304 qemu_fdt_setprop(vms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1306 if (vms
->msi_phandle
) {
1307 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "msi-parent",
1311 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
1312 2, base_ecam
, 2, size_ecam
);
1315 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "ranges",
1316 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
1317 2, base_pio
, 2, size_pio
,
1318 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
1319 2, base_mmio
, 2, size_mmio
,
1320 1, FDT_PCI_RANGE_MMIO_64BIT
,
1322 2, base_mmio_high
, 2, size_mmio_high
);
1324 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "ranges",
1325 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
1326 2, base_pio
, 2, size_pio
,
1327 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
1328 2, base_mmio
, 2, size_mmio
);
1331 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#interrupt-cells", 1);
1332 create_pcie_irq_map(vms
, vms
->gic_phandle
, irq
, nodename
);
1335 vms
->iommu_phandle
= qemu_fdt_alloc_phandle(vms
->fdt
);
1337 switch (vms
->iommu
) {
1338 case VIRT_IOMMU_SMMUV3
:
1339 create_smmu(vms
, pci
->bus
);
1340 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "iommu-map",
1341 0x0, vms
->iommu_phandle
, 0x0, 0x10000);
1344 g_assert_not_reached();
1349 static void create_platform_bus(VirtMachineState
*vms
)
1354 MemoryRegion
*sysmem
= get_system_memory();
1356 dev
= qdev_create(NULL
, TYPE_PLATFORM_BUS_DEVICE
);
1357 dev
->id
= TYPE_PLATFORM_BUS_DEVICE
;
1358 qdev_prop_set_uint32(dev
, "num_irqs", PLATFORM_BUS_NUM_IRQS
);
1359 qdev_prop_set_uint32(dev
, "mmio_size", vms
->memmap
[VIRT_PLATFORM_BUS
].size
);
1360 qdev_init_nofail(dev
);
1361 vms
->platform_bus_dev
= dev
;
1363 s
= SYS_BUS_DEVICE(dev
);
1364 for (i
= 0; i
< PLATFORM_BUS_NUM_IRQS
; i
++) {
1365 int irq
= vms
->irqmap
[VIRT_PLATFORM_BUS
] + i
;
1366 sysbus_connect_irq(s
, i
, qdev_get_gpio_in(vms
->gic
, irq
));
1369 memory_region_add_subregion(sysmem
,
1370 vms
->memmap
[VIRT_PLATFORM_BUS
].base
,
1371 sysbus_mmio_get_region(s
, 0));
1374 static void create_secure_ram(VirtMachineState
*vms
,
1375 MemoryRegion
*secure_sysmem
)
1377 MemoryRegion
*secram
= g_new(MemoryRegion
, 1);
1379 hwaddr base
= vms
->memmap
[VIRT_SECURE_MEM
].base
;
1380 hwaddr size
= vms
->memmap
[VIRT_SECURE_MEM
].size
;
1382 memory_region_init_ram(secram
, NULL
, "virt.secure-ram", size
,
1384 memory_region_add_subregion(secure_sysmem
, base
, secram
);
1386 nodename
= g_strdup_printf("/secram@%" PRIx64
, base
);
1387 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
1388 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "device_type", "memory");
1389 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg", 2, base
, 2, size
);
1390 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "status", "disabled");
1391 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "secure-status", "okay");
1396 static void *machvirt_dtb(const struct arm_boot_info
*binfo
, int *fdt_size
)
1398 const VirtMachineState
*board
= container_of(binfo
, VirtMachineState
,
1401 *fdt_size
= board
->fdt_size
;
1405 static void virt_build_smbios(VirtMachineState
*vms
)
1407 MachineClass
*mc
= MACHINE_GET_CLASS(vms
);
1408 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
1409 uint8_t *smbios_tables
, *smbios_anchor
;
1410 size_t smbios_tables_len
, smbios_anchor_len
;
1411 const char *product
= "QEMU Virtual Machine";
1413 if (kvm_enabled()) {
1414 product
= "KVM Virtual Machine";
1417 smbios_set_defaults("QEMU", product
,
1418 vmc
->smbios_old_sys_ver
? "1.0" : mc
->name
, false,
1419 true, SMBIOS_ENTRY_POINT_30
);
1421 smbios_get_tables(MACHINE(vms
), NULL
, 0, &smbios_tables
, &smbios_tables_len
,
1422 &smbios_anchor
, &smbios_anchor_len
);
1424 if (smbios_anchor
) {
1425 fw_cfg_add_file(vms
->fw_cfg
, "etc/smbios/smbios-tables",
1426 smbios_tables
, smbios_tables_len
);
1427 fw_cfg_add_file(vms
->fw_cfg
, "etc/smbios/smbios-anchor",
1428 smbios_anchor
, smbios_anchor_len
);
1433 void virt_machine_done(Notifier
*notifier
, void *data
)
1435 VirtMachineState
*vms
= container_of(notifier
, VirtMachineState
,
1437 MachineState
*ms
= MACHINE(vms
);
1438 ARMCPU
*cpu
= ARM_CPU(first_cpu
);
1439 struct arm_boot_info
*info
= &vms
->bootinfo
;
1440 AddressSpace
*as
= arm_boot_address_space(cpu
, info
);
1443 * If the user provided a dtb, we assume the dynamic sysbus nodes
1444 * already are integrated there. This corresponds to a use case where
1445 * the dynamic sysbus nodes are complex and their generation is not yet
1446 * supported. In that case the user can take charge of the guest dt
1447 * while qemu takes charge of the qom stuff.
1449 if (info
->dtb_filename
== NULL
) {
1450 platform_bus_add_all_fdt_nodes(vms
->fdt
, "/intc",
1451 vms
->memmap
[VIRT_PLATFORM_BUS
].base
,
1452 vms
->memmap
[VIRT_PLATFORM_BUS
].size
,
1453 vms
->irqmap
[VIRT_PLATFORM_BUS
]);
1455 if (arm_load_dtb(info
->dtb_start
, info
, info
->dtb_limit
, as
, ms
) < 0) {
1459 virt_acpi_setup(vms
);
1460 virt_build_smbios(vms
);
1463 static uint64_t virt_cpu_mp_affinity(VirtMachineState
*vms
, int idx
)
1465 uint8_t clustersz
= ARM_DEFAULT_CPUS_PER_CLUSTER
;
1466 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
1468 if (!vmc
->disallow_affinity_adjustment
) {
1469 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the
1470 * GIC's target-list limitations. 32-bit KVM hosts currently
1471 * always create clusters of 4 CPUs, but that is expected to
1472 * change when they gain support for gicv3. When KVM is enabled
1473 * it will override the changes we make here, therefore our
1474 * purposes are to make TCG consistent (with 64-bit KVM hosts)
1475 * and to improve SGI efficiency.
1477 if (vms
->gic_version
== VIRT_GIC_VERSION_3
) {
1478 clustersz
= GICV3_TARGETLIST_BITS
;
1480 clustersz
= GIC_TARGETLIST_BITS
;
1483 return arm_cpu_mp_affinity(idx
, clustersz
);
1486 static void virt_set_memmap(VirtMachineState
*vms
)
1488 MachineState
*ms
= MACHINE(vms
);
1489 hwaddr base
, device_memory_base
, device_memory_size
;
1492 vms
->memmap
= extended_memmap
;
1494 for (i
= 0; i
< ARRAY_SIZE(base_memmap
); i
++) {
1495 vms
->memmap
[i
] = base_memmap
[i
];
1498 if (ms
->ram_slots
> ACPI_MAX_RAM_SLOTS
) {
1499 error_report("unsupported number of memory slots: %"PRIu64
,
1505 * We compute the base of the high IO region depending on the
1506 * amount of initial and device memory. The device memory start/size
1507 * is aligned on 1GiB. We never put the high IO region below 256GiB
1508 * so that if maxram_size is < 255GiB we keep the legacy memory map.
1509 * The device region size assumes 1GiB page max alignment per slot.
1511 device_memory_base
=
1512 ROUND_UP(vms
->memmap
[VIRT_MEM
].base
+ ms
->ram_size
, GiB
);
1513 device_memory_size
= ms
->maxram_size
- ms
->ram_size
+ ms
->ram_slots
* GiB
;
1515 /* Base address of the high IO region */
1516 base
= device_memory_base
+ ROUND_UP(device_memory_size
, GiB
);
1517 if (base
< device_memory_base
) {
1518 error_report("maxmem/slots too huge");
1521 if (base
< vms
->memmap
[VIRT_MEM
].base
+ LEGACY_RAMLIMIT_BYTES
) {
1522 base
= vms
->memmap
[VIRT_MEM
].base
+ LEGACY_RAMLIMIT_BYTES
;
1525 for (i
= VIRT_LOWMEMMAP_LAST
; i
< ARRAY_SIZE(extended_memmap
); i
++) {
1526 hwaddr size
= extended_memmap
[i
].size
;
1528 base
= ROUND_UP(base
, size
);
1529 vms
->memmap
[i
].base
= base
;
1530 vms
->memmap
[i
].size
= size
;
1533 vms
->highest_gpa
= base
- 1;
1534 if (device_memory_size
> 0) {
1535 ms
->device_memory
= g_malloc0(sizeof(*ms
->device_memory
));
1536 ms
->device_memory
->base
= device_memory_base
;
1537 memory_region_init(&ms
->device_memory
->mr
, OBJECT(vms
),
1538 "device-memory", device_memory_size
);
1543 * finalize_gic_version - Determines the final gic_version
1544 * according to the gic-version property
1546 * Default GIC type is v2
1548 static void finalize_gic_version(VirtMachineState
*vms
)
1550 unsigned int max_cpus
= MACHINE(vms
)->smp
.max_cpus
;
1552 if (kvm_enabled()) {
1555 if (!kvm_irqchip_in_kernel()) {
1556 switch (vms
->gic_version
) {
1557 case VIRT_GIC_VERSION_HOST
:
1559 "gic-version=host not relevant with kernel-irqchip=off "
1560 "as only userspace GICv2 is supported. Using v2 ...");
1562 case VIRT_GIC_VERSION_MAX
:
1563 case VIRT_GIC_VERSION_NOSEL
:
1564 vms
->gic_version
= VIRT_GIC_VERSION_2
;
1566 case VIRT_GIC_VERSION_2
:
1568 case VIRT_GIC_VERSION_3
:
1570 "gic-version=3 is not supported with kernel-irqchip=off");
1575 probe_bitmap
= kvm_arm_vgic_probe();
1576 if (!probe_bitmap
) {
1577 error_report("Unable to determine GIC version supported by host");
1581 switch (vms
->gic_version
) {
1582 case VIRT_GIC_VERSION_HOST
:
1583 case VIRT_GIC_VERSION_MAX
:
1584 if (probe_bitmap
& KVM_ARM_VGIC_V3
) {
1585 vms
->gic_version
= VIRT_GIC_VERSION_3
;
1587 vms
->gic_version
= VIRT_GIC_VERSION_2
;
1590 case VIRT_GIC_VERSION_NOSEL
:
1591 if ((probe_bitmap
& KVM_ARM_VGIC_V2
) && max_cpus
<= GIC_NCPU
) {
1592 vms
->gic_version
= VIRT_GIC_VERSION_2
;
1593 } else if (probe_bitmap
& KVM_ARM_VGIC_V3
) {
1595 * in case the host does not support v2 in-kernel emulation or
1596 * the end-user requested more than 8 VCPUs we now default
1597 * to v3. In any case defaulting to v2 would be broken.
1599 vms
->gic_version
= VIRT_GIC_VERSION_3
;
1600 } else if (max_cpus
> GIC_NCPU
) {
1601 error_report("host only supports in-kernel GICv2 emulation "
1602 "but more than 8 vcpus are requested");
1606 case VIRT_GIC_VERSION_2
:
1607 case VIRT_GIC_VERSION_3
:
1611 /* Check chosen version is effectively supported by the host */
1612 if (vms
->gic_version
== VIRT_GIC_VERSION_2
&&
1613 !(probe_bitmap
& KVM_ARM_VGIC_V2
)) {
1614 error_report("host does not support in-kernel GICv2 emulation");
1616 } else if (vms
->gic_version
== VIRT_GIC_VERSION_3
&&
1617 !(probe_bitmap
& KVM_ARM_VGIC_V3
)) {
1618 error_report("host does not support in-kernel GICv3 emulation");
1625 switch (vms
->gic_version
) {
1626 case VIRT_GIC_VERSION_NOSEL
:
1627 vms
->gic_version
= VIRT_GIC_VERSION_2
;
1629 case VIRT_GIC_VERSION_MAX
:
1630 vms
->gic_version
= VIRT_GIC_VERSION_3
;
1632 case VIRT_GIC_VERSION_HOST
:
1633 error_report("gic-version=host requires KVM");
1635 case VIRT_GIC_VERSION_2
:
1636 case VIRT_GIC_VERSION_3
:
1641 static void machvirt_init(MachineState
*machine
)
1643 VirtMachineState
*vms
= VIRT_MACHINE(machine
);
1644 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(machine
);
1645 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
1646 const CPUArchIdList
*possible_cpus
;
1647 MemoryRegion
*sysmem
= get_system_memory();
1648 MemoryRegion
*secure_sysmem
= NULL
;
1649 int n
, virt_max_cpus
;
1650 bool firmware_loaded
;
1651 bool aarch64
= true;
1652 bool has_ged
= !vmc
->no_ged
;
1653 unsigned int smp_cpus
= machine
->smp
.cpus
;
1654 unsigned int max_cpus
= machine
->smp
.max_cpus
;
1657 * In accelerated mode, the memory map is computed earlier in kvm_type()
1658 * to create a VM with the right number of IPA bits.
1661 virt_set_memmap(vms
);
1664 /* We can probe only here because during property set
1665 * KVM is not available yet
1667 finalize_gic_version(vms
);
1669 if (!cpu_type_valid(machine
->cpu_type
)) {
1670 error_report("mach-virt: CPU type %s not supported", machine
->cpu_type
);
1675 if (kvm_enabled()) {
1676 error_report("mach-virt: KVM does not support Security extensions");
1681 * The Secure view of the world is the same as the NonSecure,
1682 * but with a few extra devices. Create it as a container region
1683 * containing the system memory at low priority; any secure-only
1684 * devices go in at higher priority and take precedence.
1686 secure_sysmem
= g_new(MemoryRegion
, 1);
1687 memory_region_init(secure_sysmem
, OBJECT(machine
), "secure-memory",
1689 memory_region_add_subregion_overlap(secure_sysmem
, 0, sysmem
, -1);
1692 firmware_loaded
= virt_firmware_init(vms
, sysmem
,
1693 secure_sysmem
?: sysmem
);
1695 /* If we have an EL3 boot ROM then the assumption is that it will
1696 * implement PSCI itself, so disable QEMU's internal implementation
1697 * so it doesn't get in the way. Instead of starting secondary
1698 * CPUs in PSCI powerdown state we will start them all running and
1699 * let the boot ROM sort them out.
1700 * The usual case is that we do use QEMU's PSCI implementation;
1701 * if the guest has EL2 then we will use SMC as the conduit,
1702 * and otherwise we will use HVC (for backwards compatibility and
1703 * because if we're using KVM then we must use HVC).
1705 if (vms
->secure
&& firmware_loaded
) {
1706 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_DISABLED
;
1707 } else if (vms
->virt
) {
1708 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_SMC
;
1710 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_HVC
;
1713 /* The maximum number of CPUs depends on the GIC version, or on how
1714 * many redistributors we can fit into the memory map.
1716 if (vms
->gic_version
== VIRT_GIC_VERSION_3
) {
1718 vms
->memmap
[VIRT_GIC_REDIST
].size
/ GICV3_REDIST_SIZE
;
1720 vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].size
/ GICV3_REDIST_SIZE
;
1722 virt_max_cpus
= GIC_NCPU
;
1725 if (max_cpus
> virt_max_cpus
) {
1726 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
1727 "supported by machine 'mach-virt' (%d)",
1728 max_cpus
, virt_max_cpus
);
1732 vms
->smp_cpus
= smp_cpus
;
1734 if (vms
->virt
&& kvm_enabled()) {
1735 error_report("mach-virt: KVM does not support providing "
1736 "Virtualization extensions to the guest CPU");
1742 possible_cpus
= mc
->possible_cpu_arch_ids(machine
);
1743 for (n
= 0; n
< possible_cpus
->len
; n
++) {
1747 if (n
>= smp_cpus
) {
1751 cpuobj
= object_new(possible_cpus
->cpus
[n
].type
);
1752 object_property_set_int(cpuobj
, possible_cpus
->cpus
[n
].arch_id
,
1753 "mp-affinity", NULL
);
1758 numa_cpu_pre_plug(&possible_cpus
->cpus
[cs
->cpu_index
], DEVICE(cpuobj
),
1761 aarch64
&= object_property_get_bool(cpuobj
, "aarch64", NULL
);
1764 object_property_set_bool(cpuobj
, false, "has_el3", NULL
);
1767 if (!vms
->virt
&& object_property_find(cpuobj
, "has_el2", NULL
)) {
1768 object_property_set_bool(cpuobj
, false, "has_el2", NULL
);
1771 if (vms
->psci_conduit
!= QEMU_PSCI_CONDUIT_DISABLED
) {
1772 object_property_set_int(cpuobj
, vms
->psci_conduit
,
1773 "psci-conduit", NULL
);
1775 /* Secondary CPUs start in PSCI powered-down state */
1777 object_property_set_bool(cpuobj
, true,
1778 "start-powered-off", NULL
);
1782 if (vmc
->kvm_no_adjvtime
&&
1783 object_property_find(cpuobj
, "kvm-no-adjvtime", NULL
)) {
1784 object_property_set_bool(cpuobj
, true, "kvm-no-adjvtime", NULL
);
1787 if (vmc
->no_pmu
&& object_property_find(cpuobj
, "pmu", NULL
)) {
1788 object_property_set_bool(cpuobj
, false, "pmu", NULL
);
1791 if (object_property_find(cpuobj
, "reset-cbar", NULL
)) {
1792 object_property_set_int(cpuobj
, vms
->memmap
[VIRT_CPUPERIPHS
].base
,
1793 "reset-cbar", &error_abort
);
1796 object_property_set_link(cpuobj
, OBJECT(sysmem
), "memory",
1799 object_property_set_link(cpuobj
, OBJECT(secure_sysmem
),
1800 "secure-memory", &error_abort
);
1803 object_property_set_bool(cpuobj
, true, "realized", &error_fatal
);
1804 object_unref(cpuobj
);
1806 fdt_add_timer_nodes(vms
);
1807 fdt_add_cpu_nodes(vms
);
1809 if (!kvm_enabled()) {
1810 ARMCPU
*cpu
= ARM_CPU(first_cpu
);
1811 bool aarch64
= object_property_get_bool(OBJECT(cpu
), "aarch64", NULL
);
1813 if (aarch64
&& vms
->highmem
) {
1814 int requested_pa_size
, pamax
= arm_pamax(cpu
);
1816 requested_pa_size
= 64 - clz64(vms
->highest_gpa
);
1817 if (pamax
< requested_pa_size
) {
1818 error_report("VCPU supports less PA bits (%d) than requested "
1819 "by the memory map (%d)", pamax
, requested_pa_size
);
1825 memory_region_add_subregion(sysmem
, vms
->memmap
[VIRT_MEM
].base
,
1827 if (machine
->device_memory
) {
1828 memory_region_add_subregion(sysmem
, machine
->device_memory
->base
,
1829 &machine
->device_memory
->mr
);
1832 virt_flash_fdt(vms
, sysmem
, secure_sysmem
?: sysmem
);
1836 fdt_add_pmu_nodes(vms
);
1838 create_uart(vms
, VIRT_UART
, sysmem
, serial_hd(0));
1841 create_secure_ram(vms
, secure_sysmem
);
1842 create_uart(vms
, VIRT_SECURE_UART
, secure_sysmem
, serial_hd(1));
1845 vms
->highmem_ecam
&= vms
->highmem
&& (!firmware_loaded
|| aarch64
);
1851 if (has_ged
&& aarch64
&& firmware_loaded
&& virt_is_acpi_enabled(vms
)) {
1852 vms
->acpi_dev
= create_acpi_ged(vms
);
1857 /* connect powerdown request */
1858 vms
->powerdown_notifier
.notify
= virt_powerdown_req
;
1859 qemu_register_powerdown_notifier(&vms
->powerdown_notifier
);
1861 /* Create mmio transports, so the user can create virtio backends
1862 * (which will be automatically plugged in to the transports). If
1863 * no backend is created the transport will just sit harmlessly idle.
1865 create_virtio_devices(vms
);
1867 vms
->fw_cfg
= create_fw_cfg(vms
, &address_space_memory
);
1868 rom_set_fw(vms
->fw_cfg
);
1870 create_platform_bus(vms
);
1872 vms
->bootinfo
.ram_size
= machine
->ram_size
;
1873 vms
->bootinfo
.nb_cpus
= smp_cpus
;
1874 vms
->bootinfo
.board_id
= -1;
1875 vms
->bootinfo
.loader_start
= vms
->memmap
[VIRT_MEM
].base
;
1876 vms
->bootinfo
.get_dtb
= machvirt_dtb
;
1877 vms
->bootinfo
.skip_dtb_autoload
= true;
1878 vms
->bootinfo
.firmware_loaded
= firmware_loaded
;
1879 arm_load_kernel(ARM_CPU(first_cpu
), machine
, &vms
->bootinfo
);
1881 vms
->machine_done
.notify
= virt_machine_done
;
1882 qemu_add_machine_init_done_notifier(&vms
->machine_done
);
1885 static bool virt_get_secure(Object
*obj
, Error
**errp
)
1887 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1892 static void virt_set_secure(Object
*obj
, bool value
, Error
**errp
)
1894 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1896 vms
->secure
= value
;
1899 static bool virt_get_virt(Object
*obj
, Error
**errp
)
1901 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1906 static void virt_set_virt(Object
*obj
, bool value
, Error
**errp
)
1908 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1913 static bool virt_get_highmem(Object
*obj
, Error
**errp
)
1915 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1917 return vms
->highmem
;
1920 static void virt_set_highmem(Object
*obj
, bool value
, Error
**errp
)
1922 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1924 vms
->highmem
= value
;
1927 static bool virt_get_its(Object
*obj
, Error
**errp
)
1929 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1934 static void virt_set_its(Object
*obj
, bool value
, Error
**errp
)
1936 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1941 bool virt_is_acpi_enabled(VirtMachineState
*vms
)
1943 if (vms
->acpi
== ON_OFF_AUTO_OFF
) {
1949 static void virt_get_acpi(Object
*obj
, Visitor
*v
, const char *name
,
1950 void *opaque
, Error
**errp
)
1952 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1953 OnOffAuto acpi
= vms
->acpi
;
1955 visit_type_OnOffAuto(v
, name
, &acpi
, errp
);
1958 static void virt_set_acpi(Object
*obj
, Visitor
*v
, const char *name
,
1959 void *opaque
, Error
**errp
)
1961 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1963 visit_type_OnOffAuto(v
, name
, &vms
->acpi
, errp
);
1966 static char *virt_get_gic_version(Object
*obj
, Error
**errp
)
1968 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1969 const char *val
= vms
->gic_version
== VIRT_GIC_VERSION_3
? "3" : "2";
1971 return g_strdup(val
);
1974 static void virt_set_gic_version(Object
*obj
, const char *value
, Error
**errp
)
1976 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1978 if (!strcmp(value
, "3")) {
1979 vms
->gic_version
= VIRT_GIC_VERSION_3
;
1980 } else if (!strcmp(value
, "2")) {
1981 vms
->gic_version
= VIRT_GIC_VERSION_2
;
1982 } else if (!strcmp(value
, "host")) {
1983 vms
->gic_version
= VIRT_GIC_VERSION_HOST
; /* Will probe later */
1984 } else if (!strcmp(value
, "max")) {
1985 vms
->gic_version
= VIRT_GIC_VERSION_MAX
; /* Will probe later */
1987 error_setg(errp
, "Invalid gic-version value");
1988 error_append_hint(errp
, "Valid values are 3, 2, host, max.\n");
1992 static char *virt_get_iommu(Object
*obj
, Error
**errp
)
1994 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1996 switch (vms
->iommu
) {
1997 case VIRT_IOMMU_NONE
:
1998 return g_strdup("none");
1999 case VIRT_IOMMU_SMMUV3
:
2000 return g_strdup("smmuv3");
2002 g_assert_not_reached();
2006 static void virt_set_iommu(Object
*obj
, const char *value
, Error
**errp
)
2008 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2010 if (!strcmp(value
, "smmuv3")) {
2011 vms
->iommu
= VIRT_IOMMU_SMMUV3
;
2012 } else if (!strcmp(value
, "none")) {
2013 vms
->iommu
= VIRT_IOMMU_NONE
;
2015 error_setg(errp
, "Invalid iommu value");
2016 error_append_hint(errp
, "Valid values are none, smmuv3.\n");
2020 static CpuInstanceProperties
2021 virt_cpu_index_to_props(MachineState
*ms
, unsigned cpu_index
)
2023 MachineClass
*mc
= MACHINE_GET_CLASS(ms
);
2024 const CPUArchIdList
*possible_cpus
= mc
->possible_cpu_arch_ids(ms
);
2026 assert(cpu_index
< possible_cpus
->len
);
2027 return possible_cpus
->cpus
[cpu_index
].props
;
2030 static int64_t virt_get_default_cpu_node_id(const MachineState
*ms
, int idx
)
2032 return idx
% ms
->numa_state
->num_nodes
;
2035 static const CPUArchIdList
*virt_possible_cpu_arch_ids(MachineState
*ms
)
2038 unsigned int max_cpus
= ms
->smp
.max_cpus
;
2039 VirtMachineState
*vms
= VIRT_MACHINE(ms
);
2041 if (ms
->possible_cpus
) {
2042 assert(ms
->possible_cpus
->len
== max_cpus
);
2043 return ms
->possible_cpus
;
2046 ms
->possible_cpus
= g_malloc0(sizeof(CPUArchIdList
) +
2047 sizeof(CPUArchId
) * max_cpus
);
2048 ms
->possible_cpus
->len
= max_cpus
;
2049 for (n
= 0; n
< ms
->possible_cpus
->len
; n
++) {
2050 ms
->possible_cpus
->cpus
[n
].type
= ms
->cpu_type
;
2051 ms
->possible_cpus
->cpus
[n
].arch_id
=
2052 virt_cpu_mp_affinity(vms
, n
);
2053 ms
->possible_cpus
->cpus
[n
].props
.has_thread_id
= true;
2054 ms
->possible_cpus
->cpus
[n
].props
.thread_id
= n
;
2056 return ms
->possible_cpus
;
2059 static void virt_memory_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
2062 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2063 const bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
2066 error_setg(errp
, "nvdimm is not yet supported");
2070 if (!vms
->acpi_dev
) {
2072 "memory hotplug is not enabled: missing acpi-ged device");
2076 pc_dimm_pre_plug(PC_DIMM(dev
), MACHINE(hotplug_dev
), NULL
, errp
);
2079 static void virt_memory_plug(HotplugHandler
*hotplug_dev
,
2080 DeviceState
*dev
, Error
**errp
)
2082 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2083 Error
*local_err
= NULL
;
2085 pc_dimm_plug(PC_DIMM(dev
), MACHINE(vms
), &local_err
);
2090 hotplug_handler_plug(HOTPLUG_HANDLER(vms
->acpi_dev
),
2094 error_propagate(errp
, local_err
);
2097 static void virt_machine_device_pre_plug_cb(HotplugHandler
*hotplug_dev
,
2098 DeviceState
*dev
, Error
**errp
)
2100 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2101 virt_memory_pre_plug(hotplug_dev
, dev
, errp
);
2105 static void virt_machine_device_plug_cb(HotplugHandler
*hotplug_dev
,
2106 DeviceState
*dev
, Error
**errp
)
2108 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2110 if (vms
->platform_bus_dev
) {
2111 if (object_dynamic_cast(OBJECT(dev
), TYPE_SYS_BUS_DEVICE
)) {
2112 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms
->platform_bus_dev
),
2113 SYS_BUS_DEVICE(dev
));
2116 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2117 virt_memory_plug(hotplug_dev
, dev
, errp
);
2119 if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_IOMMU_PCI
)) {
2120 PCIDevice
*pdev
= PCI_DEVICE(dev
);
2122 vms
->iommu
= VIRT_IOMMU_VIRTIO
;
2123 vms
->virtio_iommu_bdf
= pci_get_bdf(pdev
);
2124 create_virtio_iommu_dt_bindings(vms
);
2128 static void virt_machine_device_unplug_request_cb(HotplugHandler
*hotplug_dev
,
2129 DeviceState
*dev
, Error
**errp
)
2131 error_setg(errp
, "device unplug request for unsupported device"
2132 " type: %s", object_get_typename(OBJECT(dev
)));
2135 static HotplugHandler
*virt_machine_get_hotplug_handler(MachineState
*machine
,
2138 if (object_dynamic_cast(OBJECT(dev
), TYPE_SYS_BUS_DEVICE
) ||
2139 (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
))) {
2140 return HOTPLUG_HANDLER(machine
);
2142 if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_IOMMU_PCI
)) {
2143 VirtMachineState
*vms
= VIRT_MACHINE(machine
);
2145 if (!vms
->bootinfo
.firmware_loaded
|| !virt_is_acpi_enabled(vms
)) {
2146 return HOTPLUG_HANDLER(machine
);
2153 * for arm64 kvm_type [7-0] encodes the requested number of bits
2154 * in the IPA address space
2156 static int virt_kvm_type(MachineState
*ms
, const char *type_str
)
2158 VirtMachineState
*vms
= VIRT_MACHINE(ms
);
2159 int max_vm_pa_size
= kvm_arm_get_max_vm_ipa_size(ms
);
2160 int requested_pa_size
;
2162 /* we freeze the memory map to compute the highest gpa */
2163 virt_set_memmap(vms
);
2165 requested_pa_size
= 64 - clz64(vms
->highest_gpa
);
2167 if (requested_pa_size
> max_vm_pa_size
) {
2168 error_report("-m and ,maxmem option values "
2169 "require an IPA range (%d bits) larger than "
2170 "the one supported by the host (%d bits)",
2171 requested_pa_size
, max_vm_pa_size
);
2175 * By default we return 0 which corresponds to an implicit legacy
2176 * 40b IPA setting. Otherwise we return the actual requested PA
2179 return requested_pa_size
> 40 ? requested_pa_size
: 0;
2182 static void virt_machine_class_init(ObjectClass
*oc
, void *data
)
2184 MachineClass
*mc
= MACHINE_CLASS(oc
);
2185 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(oc
);
2187 mc
->init
= machvirt_init
;
2188 /* Start with max_cpus set to 512, which is the maximum supported by KVM.
2189 * The value may be reduced later when we have more information about the
2190 * configuration of the particular instance.
2193 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_CALXEDA_XGMAC
);
2194 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_AMD_XGBE
);
2195 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_RAMFB_DEVICE
);
2196 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_PLATFORM
);
2197 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_TPM_TIS_SYSBUS
);
2198 mc
->block_default_type
= IF_VIRTIO
;
2200 mc
->pci_allow_0_address
= true;
2201 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */
2202 mc
->minimum_page_bits
= 12;
2203 mc
->possible_cpu_arch_ids
= virt_possible_cpu_arch_ids
;
2204 mc
->cpu_index_to_instance_props
= virt_cpu_index_to_props
;
2205 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-a15");
2206 mc
->get_default_cpu_node_id
= virt_get_default_cpu_node_id
;
2207 mc
->kvm_type
= virt_kvm_type
;
2208 assert(!mc
->get_hotplug_handler
);
2209 mc
->get_hotplug_handler
= virt_machine_get_hotplug_handler
;
2210 hc
->pre_plug
= virt_machine_device_pre_plug_cb
;
2211 hc
->plug
= virt_machine_device_plug_cb
;
2212 hc
->unplug_request
= virt_machine_device_unplug_request_cb
;
2213 mc
->numa_mem_supported
= true;
2214 mc
->auto_enable_numa_with_memhp
= true;
2215 mc
->default_ram_id
= "mach-virt.ram";
2217 object_class_property_add(oc
, "acpi", "OnOffAuto",
2218 virt_get_acpi
, virt_set_acpi
,
2219 NULL
, NULL
, &error_abort
);
2220 object_class_property_set_description(oc
, "acpi",
2221 "Enable ACPI", &error_abort
);
2224 static void virt_instance_init(Object
*obj
)
2226 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2227 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
2229 /* EL3 is disabled by default on virt: this makes us consistent
2230 * between KVM and TCG for this board, and it also allows us to
2231 * boot UEFI blobs which assume no TrustZone support.
2233 vms
->secure
= false;
2234 object_property_add_bool(obj
, "secure", virt_get_secure
,
2235 virt_set_secure
, NULL
);
2236 object_property_set_description(obj
, "secure",
2237 "Set on/off to enable/disable the ARM "
2238 "Security Extensions (TrustZone)",
2241 /* EL2 is also disabled by default, for similar reasons */
2243 object_property_add_bool(obj
, "virtualization", virt_get_virt
,
2244 virt_set_virt
, NULL
);
2245 object_property_set_description(obj
, "virtualization",
2246 "Set on/off to enable/disable emulating a "
2247 "guest CPU which implements the ARM "
2248 "Virtualization Extensions",
2251 /* High memory is enabled by default */
2252 vms
->highmem
= true;
2253 object_property_add_bool(obj
, "highmem", virt_get_highmem
,
2254 virt_set_highmem
, NULL
);
2255 object_property_set_description(obj
, "highmem",
2256 "Set on/off to enable/disable using "
2257 "physical address space above 32 bits",
2259 vms
->gic_version
= VIRT_GIC_VERSION_NOSEL
;
2260 object_property_add_str(obj
, "gic-version", virt_get_gic_version
,
2261 virt_set_gic_version
, NULL
);
2262 object_property_set_description(obj
, "gic-version",
2264 "Valid values are 2, 3, host and max",
2267 vms
->highmem_ecam
= !vmc
->no_highmem_ecam
;
2272 /* Default allows ITS instantiation */
2274 object_property_add_bool(obj
, "its", virt_get_its
,
2275 virt_set_its
, NULL
);
2276 object_property_set_description(obj
, "its",
2277 "Set on/off to enable/disable "
2278 "ITS instantiation",
2282 /* Default disallows iommu instantiation */
2283 vms
->iommu
= VIRT_IOMMU_NONE
;
2284 object_property_add_str(obj
, "iommu", virt_get_iommu
, virt_set_iommu
, NULL
);
2285 object_property_set_description(obj
, "iommu",
2286 "Set the IOMMU type. "
2287 "Valid values are none and smmuv3",
2290 vms
->irqmap
= a15irqmap
;
2292 virt_flash_create(vms
);
2295 static const TypeInfo virt_machine_info
= {
2296 .name
= TYPE_VIRT_MACHINE
,
2297 .parent
= TYPE_MACHINE
,
2299 .instance_size
= sizeof(VirtMachineState
),
2300 .class_size
= sizeof(VirtMachineClass
),
2301 .class_init
= virt_machine_class_init
,
2302 .instance_init
= virt_instance_init
,
2303 .interfaces
= (InterfaceInfo
[]) {
2304 { TYPE_HOTPLUG_HANDLER
},
2309 static void machvirt_machine_init(void)
2311 type_register_static(&virt_machine_info
);
2313 type_init(machvirt_machine_init
);
2315 static void virt_machine_5_0_options(MachineClass
*mc
)
2317 static GlobalProperty compat
[] = {
2318 { TYPE_TPM_TIS_SYSBUS
, "ppi", "false" },
2321 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
2323 DEFINE_VIRT_MACHINE_AS_LATEST(5, 0)
2325 static void virt_machine_4_2_options(MachineClass
*mc
)
2327 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2329 virt_machine_5_0_options(mc
);
2330 compat_props_add(mc
->compat_props
, hw_compat_4_2
, hw_compat_4_2_len
);
2331 vmc
->kvm_no_adjvtime
= true;
2333 DEFINE_VIRT_MACHINE(4, 2)
2335 static void virt_machine_4_1_options(MachineClass
*mc
)
2337 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2339 virt_machine_4_2_options(mc
);
2340 compat_props_add(mc
->compat_props
, hw_compat_4_1
, hw_compat_4_1_len
);
2342 mc
->auto_enable_numa_with_memhp
= false;
2344 DEFINE_VIRT_MACHINE(4, 1)
2346 static void virt_machine_4_0_options(MachineClass
*mc
)
2348 virt_machine_4_1_options(mc
);
2349 compat_props_add(mc
->compat_props
, hw_compat_4_0
, hw_compat_4_0_len
);
2351 DEFINE_VIRT_MACHINE(4, 0)
2353 static void virt_machine_3_1_options(MachineClass
*mc
)
2355 virt_machine_4_0_options(mc
);
2356 compat_props_add(mc
->compat_props
, hw_compat_3_1
, hw_compat_3_1_len
);
2358 DEFINE_VIRT_MACHINE(3, 1)
2360 static void virt_machine_3_0_options(MachineClass
*mc
)
2362 virt_machine_3_1_options(mc
);
2363 compat_props_add(mc
->compat_props
, hw_compat_3_0
, hw_compat_3_0_len
);
2365 DEFINE_VIRT_MACHINE(3, 0)
2367 static void virt_machine_2_12_options(MachineClass
*mc
)
2369 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2371 virt_machine_3_0_options(mc
);
2372 compat_props_add(mc
->compat_props
, hw_compat_2_12
, hw_compat_2_12_len
);
2373 vmc
->no_highmem_ecam
= true;
2376 DEFINE_VIRT_MACHINE(2, 12)
2378 static void virt_machine_2_11_options(MachineClass
*mc
)
2380 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2382 virt_machine_2_12_options(mc
);
2383 compat_props_add(mc
->compat_props
, hw_compat_2_11
, hw_compat_2_11_len
);
2384 vmc
->smbios_old_sys_ver
= true;
2386 DEFINE_VIRT_MACHINE(2, 11)
2388 static void virt_machine_2_10_options(MachineClass
*mc
)
2390 virt_machine_2_11_options(mc
);
2391 compat_props_add(mc
->compat_props
, hw_compat_2_10
, hw_compat_2_10_len
);
2392 /* before 2.11 we never faulted accesses to bad addresses */
2393 mc
->ignore_memory_transaction_failures
= true;
2395 DEFINE_VIRT_MACHINE(2, 10)
2397 static void virt_machine_2_9_options(MachineClass
*mc
)
2399 virt_machine_2_10_options(mc
);
2400 compat_props_add(mc
->compat_props
, hw_compat_2_9
, hw_compat_2_9_len
);
2402 DEFINE_VIRT_MACHINE(2, 9)
2404 static void virt_machine_2_8_options(MachineClass
*mc
)
2406 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2408 virt_machine_2_9_options(mc
);
2409 compat_props_add(mc
->compat_props
, hw_compat_2_8
, hw_compat_2_8_len
);
2410 /* For 2.8 and earlier we falsely claimed in the DT that
2411 * our timers were edge-triggered, not level-triggered.
2413 vmc
->claim_edge_triggered_timers
= true;
2415 DEFINE_VIRT_MACHINE(2, 8)
2417 static void virt_machine_2_7_options(MachineClass
*mc
)
2419 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2421 virt_machine_2_8_options(mc
);
2422 compat_props_add(mc
->compat_props
, hw_compat_2_7
, hw_compat_2_7_len
);
2423 /* ITS was introduced with 2.8 */
2425 /* Stick with 1K pages for migration compatibility */
2426 mc
->minimum_page_bits
= 0;
2428 DEFINE_VIRT_MACHINE(2, 7)
2430 static void virt_machine_2_6_options(MachineClass
*mc
)
2432 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2434 virt_machine_2_7_options(mc
);
2435 compat_props_add(mc
->compat_props
, hw_compat_2_6
, hw_compat_2_6_len
);
2436 vmc
->disallow_affinity_adjustment
= true;
2437 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */
2440 DEFINE_VIRT_MACHINE(2, 6)