hw/ppc/virtex_ml507.c

   1 /*
   2  * Model of Xilinx Virtex5 ML507 PPC-440 refdesign.
   3  *
   4  * Copyright (c) 2010 Edgar E. Iglesias.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qemu-common.h"
  27 #include "qemu/datadir.h"
  28 #include "qemu/units.h"
  29 #include "cpu.h"
  30 #include "hw/sysbus.h"
  31 #include "hw/char/serial.h"
  32 #include "hw/block/flash.h"
  33 #include "sysemu/sysemu.h"
  34 #include "sysemu/reset.h"
  35 #include "hw/boards.h"
  36 #include "sysemu/device_tree.h"
  37 #include "hw/loader.h"
  38 #include "elf.h"
  39 #include "qapi/error.h"
  40 #include "qemu/error-report.h"
  41 #include "qemu/option.h"
  42
  43 #include "hw/intc/ppc-uic.h"
  44 #include "hw/ppc/ppc.h"
  45 #include "hw/ppc/ppc4xx.h"
  46 #include "hw/qdev-properties.h"
  47 #include "ppc405.h"
  48
  49 #define EPAPR_MAGIC    (0x45504150)
  50 #define FLASH_SIZE     (16 * MiB)
  51
  52 #define INTC_BASEADDR       0x81800000
  53 #define UART16550_BASEADDR  0x83e01003
  54 #define TIMER_BASEADDR      0x83c00000
  55 #define PFLASH_BASEADDR     0xfc000000
  56
  57 #define TIMER_IRQ           3
  58 #define UART16550_IRQ       9
  59
  60 static struct boot_info
  61 {
  62     uint32_t bootstrap_pc;
  63     uint32_t cmdline;
  64     uint32_t fdt;
  65     uint32_t ima_size;
  66     void *vfdt;
  67 } boot_info;
  68
  69 /* Create reset TLB entries for BookE, spanning the 32bit addr space.  */
  70 static void mmubooke_create_initial_mapping(CPUPPCState *env,
  71                                      target_ulong va,
  72                                      hwaddr pa)
  73 {
  74     ppcemb_tlb_t *tlb = &env->tlb.tlbe[0];
  75
  76     tlb->attr = 0;
  77     tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
  78     tlb->size = 1U << 31; /* up to 0x80000000  */
  79     tlb->EPN = va & TARGET_PAGE_MASK;
  80     tlb->RPN = pa & TARGET_PAGE_MASK;
  81     tlb->PID = 0;
  82
  83     tlb = &env->tlb.tlbe[1];
  84     tlb->attr = 0;
  85     tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
  86     tlb->size = 1U << 31; /* up to 0xffffffff  */
  87     tlb->EPN = 0x80000000 & TARGET_PAGE_MASK;
  88     tlb->RPN = 0x80000000 & TARGET_PAGE_MASK;
  89     tlb->PID = 0;
  90 }
  91
  92 static PowerPCCPU *ppc440_init_xilinx(const char *cpu_type, uint32_t sysclk)
  93 {
  94     PowerPCCPU *cpu;
  95     CPUPPCState *env;
  96     DeviceState *uicdev;
  97     SysBusDevice *uicsbd;
  98
  99     cpu = POWERPC_CPU(cpu_create(cpu_type));
 100     env = &cpu->env;
 101
 102     ppc_booke_timers_init(cpu, sysclk, 0/* no flags */);
 103
 104     ppc_dcr_init(env, NULL, NULL);
 105
 106     /* interrupt controller */
 107     uicdev = qdev_new(TYPE_PPC_UIC);
 108     uicsbd = SYS_BUS_DEVICE(uicdev);
 109
 110     object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(cpu),
 111                              &error_fatal);
 112     sysbus_realize_and_unref(uicsbd, &error_fatal);
 113
 114     sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT,
 115                        ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]);
 116     sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT,
 117                        ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]);
 118
 119     /* This board doesn't wire anything up to the inputs of the UIC. */
 120     return cpu;
 121 }
 122
 123 static void main_cpu_reset(void *opaque)
 124 {
 125     PowerPCCPU *cpu = opaque;
 126     CPUPPCState *env = &cpu->env;
 127     struct boot_info *bi = env->load_info;
 128
 129     cpu_reset(CPU(cpu));
 130     /* Linux Kernel Parameters (passing device tree):
 131        *   r3: pointer to the fdt
 132        *   r4: 0
 133        *   r5: 0
 134        *   r6: epapr magic
 135        *   r7: size of IMA in bytes
 136        *   r8: 0
 137        *   r9: 0
 138     */
 139     env->gpr[1] = (16 * MiB) - 8;
 140     /* Provide a device-tree.  */
 141     env->gpr[3] = bi->fdt;
 142     env->nip = bi->bootstrap_pc;
 143
 144     /* Create a mapping for the kernel.  */
 145     mmubooke_create_initial_mapping(env, 0, 0);
 146     env->gpr[6] = tswap32(EPAPR_MAGIC);
 147     env->gpr[7] = bi->ima_size;
 148 }
 149
 150 #define BINARY_DEVICE_TREE_FILE "virtex-ml507.dtb"
 151 static int xilinx_load_device_tree(hwaddr addr,
 152                                       uint32_t ramsize,
 153                                       hwaddr initrd_base,
 154                                       hwaddr initrd_size,
 155                                       const char *kernel_cmdline)
 156 {
 157     char *path;
 158     int fdt_size;
 159     void *fdt = NULL;
 160     int r;
 161     const char *dtb_filename;
 162
 163     dtb_filename = current_machine->dtb;
 164     if (dtb_filename) {
 165         fdt = load_device_tree(dtb_filename, &fdt_size);
 166         if (!fdt) {
 167             error_report("Error while loading device tree file '%s'",
 168                 dtb_filename);
 169         }
 170     } else {
 171         /* Try the local "ppc.dtb" override.  */
 172         fdt = load_device_tree("ppc.dtb", &fdt_size);
 173         if (!fdt) {
 174             path = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE);
 175             if (path) {
 176                 fdt = load_device_tree(path, &fdt_size);
 177                 g_free(path);
 178             }
 179         }
 180     }
 181     if (!fdt) {
 182         return 0;
 183     }
 184
 185     r = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
 186                               initrd_base);
 187     if (r < 0) {
 188         error_report("couldn't set /chosen/linux,initrd-start");
 189     }
 190
 191     r = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
 192                               (initrd_base + initrd_size));
 193     if (r < 0) {
 194         error_report("couldn't set /chosen/linux,initrd-end");
 195     }
 196
 197     r = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", kernel_cmdline);
 198     if (r < 0)
 199         fprintf(stderr, "couldn't set /chosen/bootargs\n");
 200     cpu_physical_memory_write(addr, fdt, fdt_size);
 201     g_free(fdt);
 202     return fdt_size;
 203 }
 204
 205 static void virtex_init(MachineState *machine)
 206 {
 207     const char *kernel_filename = machine->kernel_filename;
 208     const char *kernel_cmdline = machine->kernel_cmdline;
 209     hwaddr initrd_base = 0;
 210     int initrd_size = 0;
 211     MemoryRegion *address_space_mem = get_system_memory();
 212     DeviceState *dev;
 213     PowerPCCPU *cpu;
 214     CPUPPCState *env;
 215     hwaddr ram_base = 0;
 216     DriveInfo *dinfo;
 217     qemu_irq irq[32], *cpu_irq;
 218     int kernel_size;
 219     int i;
 220
 221     /* init CPUs */
 222     cpu = ppc440_init_xilinx(machine->cpu_type, 400000000);
 223     env = &cpu->env;
 224
 225     if (env->mmu_model != POWERPC_MMU_BOOKE) {
 226         error_report("MMU model %i not supported by this machine",
 227                      env->mmu_model);
 228         exit(1);
 229     }
 230
 231     qemu_register_reset(main_cpu_reset, cpu);
 232
 233     memory_region_add_subregion(address_space_mem, ram_base, machine->ram);
 234
 235     dinfo = drive_get(IF_PFLASH, 0, 0);
 236     pflash_cfi01_register(PFLASH_BASEADDR, "virtex.flash", FLASH_SIZE,
 237                           dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
 238                           64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1);
 239
 240     cpu_irq = (qemu_irq *) &env->irq_inputs[PPC40x_INPUT_INT];
 241     dev = qdev_new("xlnx.xps-intc");
 242     qdev_prop_set_uint32(dev, "kind-of-intr", 0);
 243     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 244     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
 245     sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq[0]);
 246     for (i = 0; i < 32; i++) {
 247         irq[i] = qdev_get_gpio_in(dev, i);
 248     }
 249
 250     serial_mm_init(address_space_mem, UART16550_BASEADDR, 2, irq[UART16550_IRQ],
 251                    115200, serial_hd(0), DEVICE_LITTLE_ENDIAN);
 252
 253     /* 2 timers at irq 2 @ 62 Mhz.  */
 254     dev = qdev_new("xlnx.xps-timer");
 255     qdev_prop_set_uint32(dev, "one-timer-only", 0);
 256     qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000);
 257     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 258     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR);
 259     sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]);
 260
 261     if (kernel_filename) {
 262         uint64_t entry, high;
 263         hwaddr boot_offset;
 264
 265         /* Boots a kernel elf binary.  */
 266         kernel_size = load_elf(kernel_filename, NULL, NULL, NULL,
 267                                &entry, NULL, &high, NULL, 1, PPC_ELF_MACHINE,
 268                                0, 0);
 269         boot_info.bootstrap_pc = entry & 0x00ffffff;
 270
 271         if (kernel_size < 0) {
 272             boot_offset = 0x1200000;
 273             /* If we failed loading ELF's try a raw image.  */
 274             kernel_size = load_image_targphys(kernel_filename,
 275                                               boot_offset,
 276                                               machine->ram_size);
 277             boot_info.bootstrap_pc = boot_offset;
 278             high = boot_info.bootstrap_pc + kernel_size + 8192;
 279         }
 280
 281         boot_info.ima_size = kernel_size;
 282
 283         /* Load initrd. */
 284         if (machine->initrd_filename) {
 285             initrd_base = high = ROUND_UP(high, 4);
 286             initrd_size = load_image_targphys(machine->initrd_filename,
 287                                               high, machine->ram_size - high);
 288
 289             if (initrd_size < 0) {
 290                 error_report("couldn't load ram disk '%s'",
 291                              machine->initrd_filename);
 292                 exit(1);
 293             }
 294             high = ROUND_UP(high + initrd_size, 4);
 295         }
 296
 297         /* Provide a device-tree.  */
 298         boot_info.fdt = high + (8192 * 2);
 299         boot_info.fdt &= ~8191;
 300
 301         xilinx_load_device_tree(boot_info.fdt, machine->ram_size,
 302                                 initrd_base, initrd_size,
 303                                 kernel_cmdline);
 304     }
 305     env->load_info = &boot_info;
 306 }
 307
 308 static void virtex_machine_init(MachineClass *mc)
 309 {
 310     mc->desc = "Xilinx Virtex ML507 reference design";
 311     mc->init = virtex_init;
 312     mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("440-xilinx");
 313     mc->default_ram_id = "ram";
 314 }
 315
 316 DEFINE_MACHINE("virtex-ml507", virtex_machine_init)