include/hw/virtio/virtio-gpu.h

   1 /*
   2  * Virtio GPU Device
   3  *
   4  * Copyright Red Hat, Inc. 2013-2014
   5  *
   6  * Authors:
   7  *     Dave Airlie <airlied@redhat.com>
   8  *     Gerd Hoffmann <kraxel@redhat.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2.
  11  * See the COPYING file in the top-level directory.
  12  */
  13
  14 #ifndef HW_VIRTIO_GPU_H
  15 #define HW_VIRTIO_GPU_H
  16
  17 #include "qemu/queue.h"
  18 #include "ui/qemu-pixman.h"
  19 #include "ui/console.h"
  20 #include "hw/virtio/virtio.h"
  21 #include "qemu/log.h"
  22 #include "sysemu/vhost-user-backend.h"
  23
  24 #include "standard-headers/linux/virtio_gpu.h"
  25 #include "qom/object.h"
  26
  27 #define TYPE_VIRTIO_GPU_BASE "virtio-gpu-base"
  28 OBJECT_DECLARE_TYPE(VirtIOGPUBase, VirtIOGPUBaseClass,
  29                     VIRTIO_GPU_BASE)
  30
  31 #define TYPE_VIRTIO_GPU "virtio-gpu-device"
  32 OBJECT_DECLARE_TYPE(VirtIOGPU, VirtIOGPUClass, VIRTIO_GPU)
  33
  34 #define TYPE_VIRTIO_GPU_GL "virtio-gpu-gl-device"
  35 OBJECT_DECLARE_SIMPLE_TYPE(VirtIOGPUGL, VIRTIO_GPU_GL)
  36
  37 #define TYPE_VHOST_USER_GPU "vhost-user-gpu"
  38 OBJECT_DECLARE_SIMPLE_TYPE(VhostUserGPU, VHOST_USER_GPU)
  39
  40 #define VIRTIO_ID_GPU 16
  41
  42 struct virtio_gpu_simple_resource {
  43     uint32_t resource_id;
  44     uint32_t width;
  45     uint32_t height;
  46     uint32_t format;
  47     uint64_t *addrs;
  48     struct iovec *iov;
  49     unsigned int iov_cnt;
  50     uint32_t scanout_bitmask;
  51     pixman_image_t *image;
  52     uint64_t hostmem;
  53
  54     uint64_t blob_size;
  55     void *blob;
  56     int dmabuf_fd;
  57     uint8_t *remapped;
  58
  59     QTAILQ_ENTRY(virtio_gpu_simple_resource) next;
  60 };
  61
  62 struct virtio_gpu_framebuffer {
  63     pixman_format_code_t format;
  64     uint32_t bytes_pp;
  65     uint32_t width, height;
  66     uint32_t stride;
  67     uint32_t offset;
  68 };
  69
  70 struct virtio_gpu_scanout {
  71     QemuConsole *con;
  72     DisplaySurface *ds;
  73     uint32_t width, height;
  74     int x, y;
  75     int invalidate;
  76     uint32_t resource_id;
  77     struct virtio_gpu_update_cursor cursor;
  78     QEMUCursor *current_cursor;
  79 };
  80
  81 struct virtio_gpu_requested_state {
  82     uint16_t width_mm, height_mm;
  83     uint32_t width, height;
  84     int x, y;
  85 };
  86
  87 enum virtio_gpu_base_conf_flags {
  88     VIRTIO_GPU_FLAG_VIRGL_ENABLED = 1,
  89     VIRTIO_GPU_FLAG_STATS_ENABLED,
  90     VIRTIO_GPU_FLAG_EDID_ENABLED,
  91     VIRTIO_GPU_FLAG_DMABUF_ENABLED,
  92 };
  93
  94 #define virtio_gpu_virgl_enabled(_cfg) \
  95     (_cfg.flags & (1 << VIRTIO_GPU_FLAG_VIRGL_ENABLED))
  96 #define virtio_gpu_stats_enabled(_cfg) \
  97     (_cfg.flags & (1 << VIRTIO_GPU_FLAG_STATS_ENABLED))
  98 #define virtio_gpu_edid_enabled(_cfg) \
  99     (_cfg.flags & (1 << VIRTIO_GPU_FLAG_EDID_ENABLED))
 100 #define virtio_gpu_dmabuf_enabled(_cfg) \
 101     (_cfg.flags & (1 << VIRTIO_GPU_FLAG_DMABUF_ENABLED))
 102
 103 struct virtio_gpu_base_conf {
 104     uint32_t max_outputs;
 105     uint32_t flags;
 106     uint32_t xres;
 107     uint32_t yres;
 108 };
 109
 110 struct virtio_gpu_ctrl_command {
 111     VirtQueueElement elem;
 112     VirtQueue *vq;
 113     struct virtio_gpu_ctrl_hdr cmd_hdr;
 114     uint32_t error;
 115     bool finished;
 116     QTAILQ_ENTRY(virtio_gpu_ctrl_command) next;
 117 };
 118
 119 struct VirtIOGPUBase {
 120     VirtIODevice parent_obj;
 121
 122     Error *migration_blocker;
 123
 124     struct virtio_gpu_base_conf conf;
 125     struct virtio_gpu_config virtio_config;
 126     const GraphicHwOps *hw_ops;
 127
 128     int renderer_blocked;
 129     int enable;
 130
 131     struct virtio_gpu_scanout scanout[VIRTIO_GPU_MAX_SCANOUTS];
 132
 133     int enabled_output_bitmask;
 134     struct virtio_gpu_requested_state req_state[VIRTIO_GPU_MAX_SCANOUTS];
 135 };
 136
 137 struct VirtIOGPUBaseClass {
 138     VirtioDeviceClass parent;
 139
 140     void (*gl_flushed)(VirtIOGPUBase *g);
 141 };
 142
 143 #define VIRTIO_GPU_BASE_PROPERTIES(_state, _conf)                       \
 144     DEFINE_PROP_UINT32("max_outputs", _state, _conf.max_outputs, 1),    \
 145     DEFINE_PROP_BIT("edid", _state, _conf.flags, \
 146                     VIRTIO_GPU_FLAG_EDID_ENABLED, true), \
 147     DEFINE_PROP_UINT32("xres", _state, _conf.xres, 1024), \
 148     DEFINE_PROP_UINT32("yres", _state, _conf.yres, 768)
 149
 150 struct VirtIOGPU {
 151     VirtIOGPUBase parent_obj;
 152
 153     uint64_t conf_max_hostmem;
 154
 155     VirtQueue *ctrl_vq;
 156     VirtQueue *cursor_vq;
 157
 158     QEMUBH *ctrl_bh;
 159     QEMUBH *cursor_bh;
 160
 161     QTAILQ_HEAD(, virtio_gpu_simple_resource) reslist;
 162     QTAILQ_HEAD(, virtio_gpu_ctrl_command) cmdq;
 163     QTAILQ_HEAD(, virtio_gpu_ctrl_command) fenceq;
 164
 165     uint64_t hostmem;
 166
 167     bool processing_cmdq;
 168     QEMUTimer *fence_poll;
 169     QEMUTimer *print_stats;
 170
 171     uint32_t inflight;
 172     struct {
 173         uint32_t max_inflight;
 174         uint32_t requests;
 175         uint32_t req_3d;
 176         uint32_t bytes_3d;
 177     } stats;
 178 };
 179
 180 struct VirtIOGPUClass {
 181     VirtIOGPUBaseClass parent;
 182
 183     void (*handle_ctrl)(VirtIODevice *vdev, VirtQueue *vq);
 184     void (*process_cmd)(VirtIOGPU *g, struct virtio_gpu_ctrl_command *cmd);
 185     void (*update_cursor_data)(VirtIOGPU *g,
 186                                struct virtio_gpu_scanout *s,
 187                                uint32_t resource_id);
 188 };
 189
 190 struct VirtIOGPUGL {
 191     struct VirtIOGPU parent_obj;
 192
 193     bool renderer_inited;
 194     bool renderer_reset;
 195 };
 196
 197 struct VhostUserGPU {
 198     VirtIOGPUBase parent_obj;
 199
 200     VhostUserBackend *vhost;
 201     int vhost_gpu_fd; /* closed by the chardev */
 202     CharBackend vhost_chr;
 203     QemuDmaBuf dmabuf[VIRTIO_GPU_MAX_SCANOUTS];
 204     bool backend_blocked;
 205 };
 206
 207 #define VIRTIO_GPU_FILL_CMD(out) do {                                   \
 208         size_t s;                                                       \
 209         s = iov_to_buf(cmd->elem.out_sg, cmd->elem.out_num, 0,          \
 210                        &out, sizeof(out));                              \
 211         if (s != sizeof(out)) {                                         \
 212             qemu_log_mask(LOG_GUEST_ERROR,                              \
 213                           "%s: command size incorrect %zu vs %zu\n",    \
 214                           __func__, s, sizeof(out));                    \
 215             return;                                                     \
 216         }                                                               \
 217     } while (0)
 218
 219 /* virtio-gpu-base.c */
 220 bool virtio_gpu_base_device_realize(DeviceState *qdev,
 221                                     VirtIOHandleOutput ctrl_cb,
 222                                     VirtIOHandleOutput cursor_cb,
 223                                     Error **errp);
 224 void virtio_gpu_base_reset(VirtIOGPUBase *g);
 225 void virtio_gpu_base_fill_display_info(VirtIOGPUBase *g,
 226                         struct virtio_gpu_resp_display_info *dpy_info);
 227
 228 /* virtio-gpu.c */
 229 void virtio_gpu_ctrl_response(VirtIOGPU *g,
 230                               struct virtio_gpu_ctrl_command *cmd,
 231                               struct virtio_gpu_ctrl_hdr *resp,
 232                               size_t resp_len);
 233 void virtio_gpu_ctrl_response_nodata(VirtIOGPU *g,
 234                                      struct virtio_gpu_ctrl_command *cmd,
 235                                      enum virtio_gpu_ctrl_type type);
 236 void virtio_gpu_get_display_info(VirtIOGPU *g,
 237                                  struct virtio_gpu_ctrl_command *cmd);
 238 void virtio_gpu_get_edid(VirtIOGPU *g,
 239                          struct virtio_gpu_ctrl_command *cmd);
 240 int virtio_gpu_create_mapping_iov(VirtIOGPU *g,
 241                                   struct virtio_gpu_resource_attach_backing *ab,
 242                                   struct virtio_gpu_ctrl_command *cmd,
 243                                   uint64_t **addr, struct iovec **iov,
 244                                   uint32_t *niov);
 245 void virtio_gpu_cleanup_mapping_iov(VirtIOGPU *g,
 246                                     struct iovec *iov, uint32_t count);
 247 void virtio_gpu_process_cmdq(VirtIOGPU *g);
 248 void virtio_gpu_device_realize(DeviceState *qdev, Error **errp);
 249 void virtio_gpu_reset(VirtIODevice *vdev);
 250 void virtio_gpu_simple_process_cmd(VirtIOGPU *g, struct virtio_gpu_ctrl_command *cmd);
 251 void virtio_gpu_update_cursor_data(VirtIOGPU *g,
 252                                    struct virtio_gpu_scanout *s,
 253                                    uint32_t resource_id);
 254
 255 /* virtio-gpu-udmabuf.c */
 256 bool virtio_gpu_have_udmabuf(void);
 257 void virtio_gpu_init_udmabuf(struct virtio_gpu_simple_resource *res);
 258 void virtio_gpu_fini_udmabuf(struct virtio_gpu_simple_resource *res);
 259
 260 /* virtio-gpu-3d.c */
 261 void virtio_gpu_virgl_process_cmd(VirtIOGPU *g,
 262                                   struct virtio_gpu_ctrl_command *cmd);
 263 void virtio_gpu_virgl_fence_poll(VirtIOGPU *g);
 264 void virtio_gpu_virgl_reset(VirtIOGPU *g);
 265 int virtio_gpu_virgl_init(VirtIOGPU *g);
 266 int virtio_gpu_virgl_get_num_capsets(VirtIOGPU *g);
 267
 268 #endif