Merge remote-tracking branch 'qemu-project/master'
[qemu/ar7.git] / include / hw / virtio / virtio-gpu.h
blob7a59379f5a7ad5d71b1918326aac14951b6213b0
1 /*
2 * Virtio GPU Device
4 * Copyright Red Hat, Inc. 2013-2014
6 * Authors:
7 * Dave Airlie <airlied@redhat.com>
8 * Gerd Hoffmann <kraxel@redhat.com>
10 * This work is licensed under the terms of the GNU GPL, version 2.
11 * See the COPYING file in the top-level directory.
14 #ifndef HW_VIRTIO_GPU_H
15 #define HW_VIRTIO_GPU_H
17 #include "qemu/queue.h"
18 #include "ui/qemu-pixman.h"
19 #include "ui/console.h"
20 #include "hw/virtio/virtio.h"
21 #include "qemu/log.h"
22 #include "sysemu/vhost-user-backend.h"
24 #include "standard-headers/linux/virtio_gpu.h"
25 #include "standard-headers/linux/virtio_ids.h"
26 #include "qom/object.h"
28 #define TYPE_VIRTIO_GPU_BASE "virtio-gpu-base"
29 OBJECT_DECLARE_TYPE(VirtIOGPUBase, VirtIOGPUBaseClass,
30 VIRTIO_GPU_BASE)
32 #define TYPE_VIRTIO_GPU "virtio-gpu-device"
33 OBJECT_DECLARE_TYPE(VirtIOGPU, VirtIOGPUClass, VIRTIO_GPU)
35 #define TYPE_VIRTIO_GPU_GL "virtio-gpu-gl-device"
36 OBJECT_DECLARE_SIMPLE_TYPE(VirtIOGPUGL, VIRTIO_GPU_GL)
38 #define TYPE_VHOST_USER_GPU "vhost-user-gpu"
39 OBJECT_DECLARE_SIMPLE_TYPE(VhostUserGPU, VHOST_USER_GPU)
41 #define TYPE_VIRTIO_GPU_RUTABAGA "virtio-gpu-rutabaga-device"
42 OBJECT_DECLARE_SIMPLE_TYPE(VirtIOGPURutabaga, VIRTIO_GPU_RUTABAGA)
44 struct virtio_gpu_simple_resource {
45 uint32_t resource_id;
46 uint32_t width;
47 uint32_t height;
48 uint32_t format;
49 uint64_t *addrs;
50 struct iovec *iov;
51 unsigned int iov_cnt;
52 uint32_t scanout_bitmask;
53 pixman_image_t *image;
54 #ifdef WIN32
55 HANDLE handle;
56 #endif
57 uint64_t hostmem;
59 uint64_t blob_size;
60 void *blob;
61 int dmabuf_fd;
62 uint8_t *remapped;
64 QTAILQ_ENTRY(virtio_gpu_simple_resource) next;
67 struct virtio_gpu_framebuffer {
68 pixman_format_code_t format;
69 uint32_t bytes_pp;
70 uint32_t width, height;
71 uint32_t stride;
72 uint32_t offset;
75 struct virtio_gpu_scanout {
76 QemuConsole *con;
77 DisplaySurface *ds;
78 uint32_t width, height;
79 int x, y;
80 int invalidate;
81 uint32_t resource_id;
82 struct virtio_gpu_update_cursor cursor;
83 QEMUCursor *current_cursor;
84 struct virtio_gpu_framebuffer fb;
87 struct virtio_gpu_requested_state {
88 uint16_t width_mm, height_mm;
89 uint32_t width, height;
90 uint32_t refresh_rate;
91 int x, y;
94 enum virtio_gpu_base_conf_flags {
95 VIRTIO_GPU_FLAG_VIRGL_ENABLED = 1,
96 VIRTIO_GPU_FLAG_STATS_ENABLED,
97 VIRTIO_GPU_FLAG_EDID_ENABLED,
98 VIRTIO_GPU_FLAG_DMABUF_ENABLED,
99 VIRTIO_GPU_FLAG_BLOB_ENABLED,
100 VIRTIO_GPU_FLAG_CONTEXT_INIT_ENABLED,
101 VIRTIO_GPU_FLAG_RUTABAGA_ENABLED,
104 #define virtio_gpu_virgl_enabled(_cfg) \
105 (_cfg.flags & (1 << VIRTIO_GPU_FLAG_VIRGL_ENABLED))
106 #define virtio_gpu_stats_enabled(_cfg) \
107 (_cfg.flags & (1 << VIRTIO_GPU_FLAG_STATS_ENABLED))
108 #define virtio_gpu_edid_enabled(_cfg) \
109 (_cfg.flags & (1 << VIRTIO_GPU_FLAG_EDID_ENABLED))
110 #define virtio_gpu_dmabuf_enabled(_cfg) \
111 (_cfg.flags & (1 << VIRTIO_GPU_FLAG_DMABUF_ENABLED))
112 #define virtio_gpu_blob_enabled(_cfg) \
113 (_cfg.flags & (1 << VIRTIO_GPU_FLAG_BLOB_ENABLED))
114 #define virtio_gpu_context_init_enabled(_cfg) \
115 (_cfg.flags & (1 << VIRTIO_GPU_FLAG_CONTEXT_INIT_ENABLED))
116 #define virtio_gpu_rutabaga_enabled(_cfg) \
117 (_cfg.flags & (1 << VIRTIO_GPU_FLAG_RUTABAGA_ENABLED))
118 #define virtio_gpu_hostmem_enabled(_cfg) \
119 (_cfg.hostmem > 0)
121 struct virtio_gpu_base_conf {
122 uint32_t max_outputs;
123 uint32_t flags;
124 uint32_t xres;
125 uint32_t yres;
126 uint64_t hostmem;
129 struct virtio_gpu_ctrl_command {
130 VirtQueueElement elem;
131 VirtQueue *vq;
132 struct virtio_gpu_ctrl_hdr cmd_hdr;
133 uint32_t error;
134 bool finished;
135 QTAILQ_ENTRY(virtio_gpu_ctrl_command) next;
138 struct VirtIOGPUBase {
139 VirtIODevice parent_obj;
141 Error *migration_blocker;
143 struct virtio_gpu_base_conf conf;
144 struct virtio_gpu_config virtio_config;
145 const GraphicHwOps *hw_ops;
147 int renderer_blocked;
148 int enable;
150 MemoryRegion hostmem;
152 struct virtio_gpu_scanout scanout[VIRTIO_GPU_MAX_SCANOUTS];
154 int enabled_output_bitmask;
155 struct virtio_gpu_requested_state req_state[VIRTIO_GPU_MAX_SCANOUTS];
158 struct VirtIOGPUBaseClass {
159 VirtioDeviceClass parent;
161 void (*gl_flushed)(VirtIOGPUBase *g);
164 #define VIRTIO_GPU_BASE_PROPERTIES(_state, _conf) \
165 DEFINE_PROP_UINT32("max_outputs", _state, _conf.max_outputs, 1), \
166 DEFINE_PROP_BIT("edid", _state, _conf.flags, \
167 VIRTIO_GPU_FLAG_EDID_ENABLED, true), \
168 DEFINE_PROP_UINT32("xres", _state, _conf.xres, 1280), \
169 DEFINE_PROP_UINT32("yres", _state, _conf.yres, 800)
171 typedef struct VGPUDMABuf {
172 QemuDmaBuf *buf;
173 uint32_t scanout_id;
174 QTAILQ_ENTRY(VGPUDMABuf) next;
175 } VGPUDMABuf;
177 struct VirtIOGPU {
178 VirtIOGPUBase parent_obj;
180 uint8_t scanout_vmstate_version;
181 uint64_t conf_max_hostmem;
183 VirtQueue *ctrl_vq;
184 VirtQueue *cursor_vq;
186 QEMUBH *ctrl_bh;
187 QEMUBH *cursor_bh;
188 QEMUBH *reset_bh;
189 QemuCond reset_cond;
190 bool reset_finished;
192 QTAILQ_HEAD(, virtio_gpu_simple_resource) reslist;
193 QTAILQ_HEAD(, virtio_gpu_ctrl_command) cmdq;
194 QTAILQ_HEAD(, virtio_gpu_ctrl_command) fenceq;
196 uint64_t hostmem;
198 bool processing_cmdq;
199 QEMUTimer *fence_poll;
200 QEMUTimer *print_stats;
202 uint32_t inflight;
203 struct {
204 uint32_t max_inflight;
205 uint32_t requests;
206 uint32_t req_3d;
207 uint32_t bytes_3d;
208 } stats;
210 struct {
211 QTAILQ_HEAD(, VGPUDMABuf) bufs;
212 VGPUDMABuf *primary[VIRTIO_GPU_MAX_SCANOUTS];
213 } dmabuf;
216 struct VirtIOGPUClass {
217 VirtIOGPUBaseClass parent;
219 void (*handle_ctrl)(VirtIODevice *vdev, VirtQueue *vq);
220 void (*process_cmd)(VirtIOGPU *g, struct virtio_gpu_ctrl_command *cmd);
221 void (*update_cursor_data)(VirtIOGPU *g,
222 struct virtio_gpu_scanout *s,
223 uint32_t resource_id);
224 void (*resource_destroy)(VirtIOGPU *g,
225 struct virtio_gpu_simple_resource *res,
226 Error **errp);
229 struct VirtIOGPUGL {
230 struct VirtIOGPU parent_obj;
232 bool renderer_inited;
233 bool renderer_reset;
236 struct VhostUserGPU {
237 VirtIOGPUBase parent_obj;
239 VhostUserBackend *vhost;
240 int vhost_gpu_fd; /* closed by the chardev */
241 CharBackend vhost_chr;
242 QemuDmaBuf *dmabuf[VIRTIO_GPU_MAX_SCANOUTS];
243 bool backend_blocked;
246 #define MAX_SLOTS 4096
248 struct MemoryRegionInfo {
249 int used;
250 MemoryRegion mr;
251 uint32_t resource_id;
254 struct rutabaga;
256 struct VirtIOGPURutabaga {
257 VirtIOGPU parent_obj;
258 struct MemoryRegionInfo memory_regions[MAX_SLOTS];
259 uint64_t capset_mask;
260 char *wayland_socket_path;
261 char *wsi;
262 bool headless;
263 uint32_t num_capsets;
264 struct rutabaga *rutabaga;
267 #define VIRTIO_GPU_FILL_CMD(out) do { \
268 size_t virtiogpufillcmd_s_ = \
269 iov_to_buf(cmd->elem.out_sg, cmd->elem.out_num, 0, \
270 &out, sizeof(out)); \
271 if (virtiogpufillcmd_s_ != sizeof(out)) { \
272 qemu_log_mask(LOG_GUEST_ERROR, \
273 "%s: command size incorrect %zu vs %zu\n", \
274 __func__, virtiogpufillcmd_s_, sizeof(out)); \
275 return; \
277 } while (0)
279 /* virtio-gpu-base.c */
280 bool virtio_gpu_base_device_realize(DeviceState *qdev,
281 VirtIOHandleOutput ctrl_cb,
282 VirtIOHandleOutput cursor_cb,
283 Error **errp);
284 void virtio_gpu_base_device_unrealize(DeviceState *qdev);
285 void virtio_gpu_base_reset(VirtIOGPUBase *g);
286 void virtio_gpu_base_fill_display_info(VirtIOGPUBase *g,
287 struct virtio_gpu_resp_display_info *dpy_info);
289 void virtio_gpu_base_generate_edid(VirtIOGPUBase *g, int scanout,
290 struct virtio_gpu_resp_edid *edid);
291 /* virtio-gpu.c */
292 struct virtio_gpu_simple_resource *
293 virtio_gpu_find_resource(VirtIOGPU *g, uint32_t resource_id);
295 void virtio_gpu_ctrl_response(VirtIOGPU *g,
296 struct virtio_gpu_ctrl_command *cmd,
297 struct virtio_gpu_ctrl_hdr *resp,
298 size_t resp_len);
299 void virtio_gpu_ctrl_response_nodata(VirtIOGPU *g,
300 struct virtio_gpu_ctrl_command *cmd,
301 enum virtio_gpu_ctrl_type type);
302 void virtio_gpu_get_display_info(VirtIOGPU *g,
303 struct virtio_gpu_ctrl_command *cmd);
304 void virtio_gpu_get_edid(VirtIOGPU *g,
305 struct virtio_gpu_ctrl_command *cmd);
306 int virtio_gpu_create_mapping_iov(VirtIOGPU *g,
307 uint32_t nr_entries, uint32_t offset,
308 struct virtio_gpu_ctrl_command *cmd,
309 uint64_t **addr, struct iovec **iov,
310 uint32_t *niov);
311 void virtio_gpu_cleanup_mapping_iov(VirtIOGPU *g,
312 struct iovec *iov, uint32_t count);
313 void virtio_gpu_cleanup_mapping(VirtIOGPU *g,
314 struct virtio_gpu_simple_resource *res);
315 void virtio_gpu_process_cmdq(VirtIOGPU *g);
316 void virtio_gpu_device_realize(DeviceState *qdev, Error **errp);
317 void virtio_gpu_reset(VirtIODevice *vdev);
318 void virtio_gpu_simple_process_cmd(VirtIOGPU *g, struct virtio_gpu_ctrl_command *cmd);
319 void virtio_gpu_update_cursor_data(VirtIOGPU *g,
320 struct virtio_gpu_scanout *s,
321 uint32_t resource_id);
323 /* virtio-gpu-udmabuf.c */
324 bool virtio_gpu_have_udmabuf(void);
325 void virtio_gpu_init_udmabuf(struct virtio_gpu_simple_resource *res);
326 void virtio_gpu_fini_udmabuf(struct virtio_gpu_simple_resource *res);
327 int virtio_gpu_update_dmabuf(VirtIOGPU *g,
328 uint32_t scanout_id,
329 struct virtio_gpu_simple_resource *res,
330 struct virtio_gpu_framebuffer *fb,
331 struct virtio_gpu_rect *r);
333 /* virtio-gpu-3d.c */
334 void virtio_gpu_virgl_process_cmd(VirtIOGPU *g,
335 struct virtio_gpu_ctrl_command *cmd);
336 void virtio_gpu_virgl_fence_poll(VirtIOGPU *g);
337 void virtio_gpu_virgl_reset_scanout(VirtIOGPU *g);
338 void virtio_gpu_virgl_reset(VirtIOGPU *g);
339 int virtio_gpu_virgl_init(VirtIOGPU *g);
340 int virtio_gpu_virgl_get_num_capsets(VirtIOGPU *g);
342 #endif