2 * QEMU PowerPC sPAPR IRQ interface
4 * Copyright (c) 2018, IBM Corporation.
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
10 #include "qemu/osdep.h"
12 #include "qemu/error-report.h"
13 #include "qapi/error.h"
15 #include "hw/ppc/spapr.h"
16 #include "hw/ppc/spapr_cpu_core.h"
17 #include "hw/ppc/spapr_xive.h"
18 #include "hw/ppc/xics.h"
19 #include "hw/ppc/xics_spapr.h"
20 #include "hw/qdev-properties.h"
21 #include "cpu-models.h"
22 #include "sysemu/kvm.h"
26 void spapr_irq_msi_init(SpaprMachineState
*spapr
, uint32_t nr_msis
)
28 spapr
->irq_map_nr
= nr_msis
;
29 spapr
->irq_map
= bitmap_new(spapr
->irq_map_nr
);
32 int spapr_irq_msi_alloc(SpaprMachineState
*spapr
, uint32_t num
, bool align
,
38 * The 'align_mask' parameter of bitmap_find_next_zero_area()
39 * should be one less than a power of 2; 0 means no
40 * alignment. Adapt the 'align' value of the former allocator
41 * to fit the requirements of bitmap_find_next_zero_area()
45 irq
= bitmap_find_next_zero_area(spapr
->irq_map
, spapr
->irq_map_nr
, 0, num
,
47 if (irq
== spapr
->irq_map_nr
) {
48 error_setg(errp
, "can't find a free %d-IRQ block", num
);
52 bitmap_set(spapr
->irq_map
, irq
, num
);
54 return irq
+ SPAPR_IRQ_MSI
;
57 void spapr_irq_msi_free(SpaprMachineState
*spapr
, int irq
, uint32_t num
)
59 bitmap_clear(spapr
->irq_map
, irq
- SPAPR_IRQ_MSI
, num
);
62 static void spapr_irq_init_kvm(SpaprMachineState
*spapr
,
63 SpaprIrq
*irq
, Error
**errp
)
65 MachineState
*machine
= MACHINE(spapr
);
66 Error
*local_err
= NULL
;
68 if (kvm_enabled() && machine_kernel_irqchip_allowed(machine
)) {
69 irq
->init_kvm(spapr
, &local_err
);
70 if (local_err
&& machine_kernel_irqchip_required(machine
)) {
71 error_prepend(&local_err
,
72 "kernel_irqchip requested but unavailable: ");
73 error_propagate(errp
, local_err
);
82 * We failed to initialize the KVM device, fallback to
85 error_prepend(&local_err
, "kernel_irqchip allowed but unavailable: ");
86 error_append_hint(&local_err
, "Falling back to kernel-irqchip=off\n");
87 warn_report_err(local_err
);
95 static void spapr_irq_init_xics(SpaprMachineState
*spapr
, Error
**errp
)
98 Error
*local_err
= NULL
;
100 obj
= object_new(TYPE_ICS_SPAPR
);
101 object_property_add_child(OBJECT(spapr
), "ics", obj
, &error_abort
);
102 object_property_add_const_link(obj
, ICS_PROP_XICS
, OBJECT(spapr
),
104 object_property_set_int(obj
, spapr
->irq
->nr_xirqs
,
105 "nr-irqs", &error_fatal
);
106 object_property_set_bool(obj
, true, "realized", &local_err
);
108 error_propagate(errp
, local_err
);
112 spapr
->ics
= ICS_SPAPR(obj
);
115 static int spapr_irq_claim_xics(SpaprMachineState
*spapr
, int irq
, bool lsi
,
118 ICSState
*ics
= spapr
->ics
;
121 assert(ics_valid_irq(ics
, irq
));
123 if (!ics_irq_free(ics
, irq
- ics
->offset
)) {
124 error_setg(errp
, "IRQ %d is not free", irq
);
128 ics_set_irq_type(ics
, irq
- ics
->offset
, lsi
);
132 static void spapr_irq_free_xics(SpaprMachineState
*spapr
, int irq
)
134 ICSState
*ics
= spapr
->ics
;
135 uint32_t srcno
= irq
- ics
->offset
;
137 assert(ics_valid_irq(ics
, irq
));
139 memset(&ics
->irqs
[srcno
], 0, sizeof(ICSIRQState
));
142 static void spapr_irq_print_info_xics(SpaprMachineState
*spapr
, Monitor
*mon
)
147 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
149 icp_pic_print_info(spapr_cpu_state(cpu
)->icp
, mon
);
152 ics_pic_print_info(spapr
->ics
, mon
);
155 static void spapr_irq_cpu_intc_create_xics(SpaprMachineState
*spapr
,
156 PowerPCCPU
*cpu
, Error
**errp
)
158 Error
*local_err
= NULL
;
160 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
162 obj
= icp_create(OBJECT(cpu
), TYPE_ICP
, XICS_FABRIC(spapr
),
165 error_propagate(errp
, local_err
);
169 spapr_cpu
->icp
= ICP(obj
);
172 static int spapr_irq_post_load_xics(SpaprMachineState
*spapr
, int version_id
)
174 if (!kvm_irqchip_in_kernel()) {
177 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
178 icp_resend(spapr_cpu_state(cpu
)->icp
);
184 static void spapr_irq_set_irq_xics(void *opaque
, int irq
, int val
)
186 SpaprMachineState
*spapr
= opaque
;
187 uint32_t srcno
= irq
- spapr
->ics
->offset
;
189 ics_set_irq(spapr
->ics
, srcno
, val
);
192 static void spapr_irq_reset_xics(SpaprMachineState
*spapr
, Error
**errp
)
194 Error
*local_err
= NULL
;
196 spapr_irq_init_kvm(spapr
, &spapr_irq_xics
, &local_err
);
198 error_propagate(errp
, local_err
);
203 static void spapr_irq_init_kvm_xics(SpaprMachineState
*spapr
, Error
**errp
)
206 xics_kvm_connect(spapr
, errp
);
210 SpaprIrq spapr_irq_xics
= {
211 .nr_xirqs
= SPAPR_NR_XIRQS
,
212 .nr_msis
= SPAPR_NR_MSIS
,
213 .ov5
= SPAPR_OV5_XIVE_LEGACY
,
215 .init
= spapr_irq_init_xics
,
216 .claim
= spapr_irq_claim_xics
,
217 .free
= spapr_irq_free_xics
,
218 .print_info
= spapr_irq_print_info_xics
,
219 .dt_populate
= spapr_dt_xics
,
220 .cpu_intc_create
= spapr_irq_cpu_intc_create_xics
,
221 .post_load
= spapr_irq_post_load_xics
,
222 .reset
= spapr_irq_reset_xics
,
223 .set_irq
= spapr_irq_set_irq_xics
,
224 .init_kvm
= spapr_irq_init_kvm_xics
,
230 static void spapr_irq_init_xive(SpaprMachineState
*spapr
, Error
**errp
)
232 uint32_t nr_servers
= spapr_max_server_number(spapr
);
236 dev
= qdev_create(NULL
, TYPE_SPAPR_XIVE
);
237 qdev_prop_set_uint32(dev
, "nr-irqs",
238 spapr
->irq
->nr_xirqs
+ SPAPR_XIRQ_BASE
);
240 * 8 XIVE END structures per CPU. One for each available priority
242 qdev_prop_set_uint32(dev
, "nr-ends", nr_servers
<< 3);
243 qdev_init_nofail(dev
);
245 spapr
->xive
= SPAPR_XIVE(dev
);
247 /* Enable the CPU IPIs */
248 for (i
= 0; i
< nr_servers
; ++i
) {
249 if (spapr_xive_irq_claim(spapr
->xive
, SPAPR_IRQ_IPI
+ i
,
255 spapr_xive_hcall_init(spapr
);
258 static int spapr_irq_claim_xive(SpaprMachineState
*spapr
, int irq
, bool lsi
,
261 return spapr_xive_irq_claim(spapr
->xive
, irq
, lsi
, errp
);
264 static void spapr_irq_free_xive(SpaprMachineState
*spapr
, int irq
)
266 spapr_xive_irq_free(spapr
->xive
, irq
);
269 static void spapr_irq_print_info_xive(SpaprMachineState
*spapr
,
275 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
277 xive_tctx_pic_print_info(spapr_cpu_state(cpu
)->tctx
, mon
);
280 spapr_xive_pic_print_info(spapr
->xive
, mon
);
283 static void spapr_irq_cpu_intc_create_xive(SpaprMachineState
*spapr
,
284 PowerPCCPU
*cpu
, Error
**errp
)
286 Error
*local_err
= NULL
;
288 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
290 obj
= xive_tctx_create(OBJECT(cpu
), XIVE_ROUTER(spapr
->xive
), &local_err
);
292 error_propagate(errp
, local_err
);
296 spapr_cpu
->tctx
= XIVE_TCTX(obj
);
299 * (TCG) Early setting the OS CAM line for hotplugged CPUs as they
300 * don't beneficiate from the reset of the XIVE IRQ backend
302 spapr_xive_set_tctx_os_cam(spapr_cpu
->tctx
);
305 static int spapr_irq_post_load_xive(SpaprMachineState
*spapr
, int version_id
)
307 return spapr_xive_post_load(spapr
->xive
, version_id
);
310 static void spapr_irq_reset_xive(SpaprMachineState
*spapr
, Error
**errp
)
313 Error
*local_err
= NULL
;
316 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
318 /* (TCG) Set the OS CAM line of the thread interrupt context. */
319 spapr_xive_set_tctx_os_cam(spapr_cpu_state(cpu
)->tctx
);
322 spapr_irq_init_kvm(spapr
, &spapr_irq_xive
, &local_err
);
324 error_propagate(errp
, local_err
);
328 /* Activate the XIVE MMIOs */
329 spapr_xive_mmio_set_enabled(spapr
->xive
, true);
332 static void spapr_irq_set_irq_xive(void *opaque
, int irq
, int val
)
334 SpaprMachineState
*spapr
= opaque
;
336 if (kvm_irqchip_in_kernel()) {
337 kvmppc_xive_source_set_irq(&spapr
->xive
->source
, irq
, val
);
339 xive_source_set_irq(&spapr
->xive
->source
, irq
, val
);
343 static void spapr_irq_init_kvm_xive(SpaprMachineState
*spapr
, Error
**errp
)
346 kvmppc_xive_connect(spapr
->xive
, errp
);
350 SpaprIrq spapr_irq_xive
= {
351 .nr_xirqs
= SPAPR_NR_XIRQS
,
352 .nr_msis
= SPAPR_NR_MSIS
,
353 .ov5
= SPAPR_OV5_XIVE_EXPLOIT
,
355 .init
= spapr_irq_init_xive
,
356 .claim
= spapr_irq_claim_xive
,
357 .free
= spapr_irq_free_xive
,
358 .print_info
= spapr_irq_print_info_xive
,
359 .dt_populate
= spapr_dt_xive
,
360 .cpu_intc_create
= spapr_irq_cpu_intc_create_xive
,
361 .post_load
= spapr_irq_post_load_xive
,
362 .reset
= spapr_irq_reset_xive
,
363 .set_irq
= spapr_irq_set_irq_xive
,
364 .init_kvm
= spapr_irq_init_kvm_xive
,
368 * Dual XIVE and XICS IRQ backend.
370 * Both interrupt mode, XIVE and XICS, objects are created but the
371 * machine starts in legacy interrupt mode (XICS). It can be changed
372 * by the CAS negotiation process and, in that case, the new mode is
373 * activated after an extra machine reset.
377 * Returns the sPAPR IRQ backend negotiated by CAS. XICS is the
380 static SpaprIrq
*spapr_irq_current(SpaprMachineState
*spapr
)
382 return spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
) ?
383 &spapr_irq_xive
: &spapr_irq_xics
;
386 static void spapr_irq_init_dual(SpaprMachineState
*spapr
, Error
**errp
)
388 Error
*local_err
= NULL
;
390 spapr_irq_xics
.init(spapr
, &local_err
);
392 error_propagate(errp
, local_err
);
396 spapr_irq_xive
.init(spapr
, &local_err
);
398 error_propagate(errp
, local_err
);
403 static int spapr_irq_claim_dual(SpaprMachineState
*spapr
, int irq
, bool lsi
,
406 Error
*local_err
= NULL
;
409 ret
= spapr_irq_xics
.claim(spapr
, irq
, lsi
, &local_err
);
411 error_propagate(errp
, local_err
);
415 ret
= spapr_irq_xive
.claim(spapr
, irq
, lsi
, &local_err
);
417 error_propagate(errp
, local_err
);
424 static void spapr_irq_free_dual(SpaprMachineState
*spapr
, int irq
)
426 spapr_irq_xics
.free(spapr
, irq
);
427 spapr_irq_xive
.free(spapr
, irq
);
430 static void spapr_irq_print_info_dual(SpaprMachineState
*spapr
, Monitor
*mon
)
432 spapr_irq_current(spapr
)->print_info(spapr
, mon
);
435 static void spapr_irq_dt_populate_dual(SpaprMachineState
*spapr
,
436 uint32_t nr_servers
, void *fdt
,
439 spapr_irq_current(spapr
)->dt_populate(spapr
, nr_servers
, fdt
, phandle
);
442 static void spapr_irq_cpu_intc_create_dual(SpaprMachineState
*spapr
,
443 PowerPCCPU
*cpu
, Error
**errp
)
445 Error
*local_err
= NULL
;
447 spapr_irq_xive
.cpu_intc_create(spapr
, cpu
, &local_err
);
449 error_propagate(errp
, local_err
);
453 spapr_irq_xics
.cpu_intc_create(spapr
, cpu
, errp
);
456 static int spapr_irq_post_load_dual(SpaprMachineState
*spapr
, int version_id
)
459 * Force a reset of the XIVE backend after migration. The machine
460 * defaults to XICS at startup.
462 if (spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
463 if (kvm_irqchip_in_kernel()) {
464 xics_kvm_disconnect(spapr
, &error_fatal
);
466 spapr_irq_xive
.reset(spapr
, &error_fatal
);
469 return spapr_irq_current(spapr
)->post_load(spapr
, version_id
);
472 static void spapr_irq_reset_dual(SpaprMachineState
*spapr
, Error
**errp
)
474 Error
*local_err
= NULL
;
477 * Deactivate the XIVE MMIOs. The XIVE backend will reenable them
480 spapr_xive_mmio_set_enabled(spapr
->xive
, false);
482 /* Destroy all KVM devices */
483 if (kvm_irqchip_in_kernel()) {
484 xics_kvm_disconnect(spapr
, &local_err
);
486 error_propagate(errp
, local_err
);
487 error_prepend(errp
, "KVM XICS disconnect failed: ");
490 kvmppc_xive_disconnect(spapr
->xive
, &local_err
);
492 error_propagate(errp
, local_err
);
493 error_prepend(errp
, "KVM XIVE disconnect failed: ");
498 spapr_irq_current(spapr
)->reset(spapr
, errp
);
501 static void spapr_irq_set_irq_dual(void *opaque
, int irq
, int val
)
503 SpaprMachineState
*spapr
= opaque
;
505 spapr_irq_current(spapr
)->set_irq(spapr
, irq
, val
);
509 * Define values in sync with the XIVE and XICS backend
511 SpaprIrq spapr_irq_dual
= {
512 .nr_xirqs
= SPAPR_NR_XIRQS
,
513 .nr_msis
= SPAPR_NR_MSIS
,
514 .ov5
= SPAPR_OV5_XIVE_BOTH
,
516 .init
= spapr_irq_init_dual
,
517 .claim
= spapr_irq_claim_dual
,
518 .free
= spapr_irq_free_dual
,
519 .print_info
= spapr_irq_print_info_dual
,
520 .dt_populate
= spapr_irq_dt_populate_dual
,
521 .cpu_intc_create
= spapr_irq_cpu_intc_create_dual
,
522 .post_load
= spapr_irq_post_load_dual
,
523 .reset
= spapr_irq_reset_dual
,
524 .set_irq
= spapr_irq_set_irq_dual
,
525 .init_kvm
= NULL
, /* should not be used */
529 static void spapr_irq_check(SpaprMachineState
*spapr
, Error
**errp
)
531 MachineState
*machine
= MACHINE(spapr
);
534 * Sanity checks on non-P9 machines. On these, XIVE is not
535 * advertised, see spapr_dt_ov5_platform_support()
537 if (!ppc_type_check_compat(machine
->cpu_type
, CPU_POWERPC_LOGICAL_3_00
,
538 0, spapr
->max_compat_pvr
)) {
540 * If the 'dual' interrupt mode is selected, force XICS as CAS
541 * negotiation is useless.
543 if (spapr
->irq
== &spapr_irq_dual
) {
544 spapr
->irq
= &spapr_irq_xics
;
549 * Non-P9 machines using only XIVE is a bogus setup. We have two
550 * scenarios to take into account because of the compat mode:
552 * 1. POWER7/8 machines should fail to init later on when creating
553 * the XIVE interrupt presenters because a POWER9 exception
556 * 2. POWER9 machines using the POWER8 compat mode won't fail and
557 * will let the OS boot with a partial XIVE setup : DT
558 * properties but no hcalls.
560 * To cover both and not confuse the OS, add an early failure in
563 if (spapr
->irq
== &spapr_irq_xive
) {
564 error_setg(errp
, "XIVE-only machines require a POWER9 CPU");
570 * On a POWER9 host, some older KVM XICS devices cannot be destroyed and
571 * re-created. Detect that early to avoid QEMU to exit later when the
575 spapr
->irq
== &spapr_irq_dual
&&
576 machine_kernel_irqchip_required(machine
) &&
577 xics_kvm_has_broken_disconnect(spapr
)) {
578 error_setg(errp
, "KVM is too old to support ic-mode=dual,kernel-irqchip=on");
584 * sPAPR IRQ frontend routines for devices
586 void spapr_irq_init(SpaprMachineState
*spapr
, Error
**errp
)
588 MachineState
*machine
= MACHINE(spapr
);
589 Error
*local_err
= NULL
;
591 if (machine_kernel_irqchip_split(machine
)) {
592 error_setg(errp
, "kernel_irqchip split mode not supported on pseries");
596 if (!kvm_enabled() && machine_kernel_irqchip_required(machine
)) {
598 "kernel_irqchip requested but only available with KVM");
602 spapr_irq_check(spapr
, &local_err
);
604 error_propagate(errp
, local_err
);
608 /* Initialize the MSI IRQ allocator. */
609 if (!SPAPR_MACHINE_GET_CLASS(spapr
)->legacy_irq_allocation
) {
610 spapr_irq_msi_init(spapr
, spapr
->irq
->nr_msis
);
613 spapr
->irq
->init(spapr
, errp
);
615 spapr
->qirqs
= qemu_allocate_irqs(spapr
->irq
->set_irq
, spapr
,
616 spapr
->irq
->nr_xirqs
+ SPAPR_XIRQ_BASE
);
619 int spapr_irq_claim(SpaprMachineState
*spapr
, int irq
, bool lsi
, Error
**errp
)
621 assert(irq
>= SPAPR_XIRQ_BASE
);
622 assert(irq
< (spapr
->irq
->nr_xirqs
+ SPAPR_XIRQ_BASE
));
624 return spapr
->irq
->claim(spapr
, irq
, lsi
, errp
);
627 void spapr_irq_free(SpaprMachineState
*spapr
, int irq
, int num
)
631 assert(irq
>= SPAPR_XIRQ_BASE
);
632 assert((irq
+ num
) <= (spapr
->irq
->nr_xirqs
+ SPAPR_XIRQ_BASE
));
634 for (i
= irq
; i
< (irq
+ num
); i
++) {
635 spapr
->irq
->free(spapr
, i
);
639 qemu_irq
spapr_qirq(SpaprMachineState
*spapr
, int irq
)
642 * This interface is basically for VIO and PHB devices to find the
643 * right qemu_irq to manipulate, so we only allow access to the
644 * external irqs for now. Currently anything which needs to
645 * access the IPIs most naturally gets there via the guest side
646 * interfaces, we can change this if we need to in future.
648 assert(irq
>= SPAPR_XIRQ_BASE
);
649 assert(irq
< (spapr
->irq
->nr_xirqs
+ SPAPR_XIRQ_BASE
));
652 assert(ics_valid_irq(spapr
->ics
, irq
));
655 assert(irq
< spapr
->xive
->nr_irqs
);
656 assert(xive_eas_is_valid(&spapr
->xive
->eat
[irq
]));
659 return spapr
->qirqs
[irq
];
662 int spapr_irq_post_load(SpaprMachineState
*spapr
, int version_id
)
664 return spapr
->irq
->post_load(spapr
, version_id
);
667 void spapr_irq_reset(SpaprMachineState
*spapr
, Error
**errp
)
669 assert(!spapr
->irq_map
|| bitmap_empty(spapr
->irq_map
, spapr
->irq_map_nr
));
671 if (spapr
->irq
->reset
) {
672 spapr
->irq
->reset(spapr
, errp
);
676 int spapr_irq_get_phandle(SpaprMachineState
*spapr
, void *fdt
, Error
**errp
)
678 const char *nodename
= "interrupt-controller";
681 offset
= fdt_subnode_offset(fdt
, 0, nodename
);
683 error_setg(errp
, "Can't find node \"%s\": %s",
684 nodename
, fdt_strerror(offset
));
688 phandle
= fdt_get_phandle(fdt
, offset
);
690 error_setg(errp
, "Can't get phandle of node \"%s\"", nodename
);
698 * XICS legacy routines - to deprecate one day
701 static int ics_find_free_block(ICSState
*ics
, int num
, int alignnum
)
705 for (first
= 0; first
< ics
->nr_irqs
; first
+= alignnum
) {
706 if (num
> (ics
->nr_irqs
- first
)) {
709 for (i
= first
; i
< first
+ num
; ++i
) {
710 if (!ics_irq_free(ics
, i
)) {
714 if (i
== (first
+ num
)) {
722 int spapr_irq_find(SpaprMachineState
*spapr
, int num
, bool align
, Error
**errp
)
724 ICSState
*ics
= spapr
->ics
;
730 * MSIMesage::data is used for storing VIRQ so
731 * it has to be aligned to num to support multiple
732 * MSI vectors. MSI-X is not affected by this.
733 * The hint is used for the first IRQ, the rest should
734 * be allocated continuously.
737 assert((num
== 1) || (num
== 2) || (num
== 4) ||
738 (num
== 8) || (num
== 16) || (num
== 32));
739 first
= ics_find_free_block(ics
, num
, num
);
741 first
= ics_find_free_block(ics
, num
, 1);
745 error_setg(errp
, "can't find a free %d-IRQ block", num
);
749 return first
+ ics
->offset
;
752 #define SPAPR_IRQ_XICS_LEGACY_NR_XIRQS 0x400
754 SpaprIrq spapr_irq_xics_legacy
= {
755 .nr_xirqs
= SPAPR_IRQ_XICS_LEGACY_NR_XIRQS
,
756 .nr_msis
= SPAPR_IRQ_XICS_LEGACY_NR_XIRQS
,
757 .ov5
= SPAPR_OV5_XIVE_LEGACY
,
759 .init
= spapr_irq_init_xics
,
760 .claim
= spapr_irq_claim_xics
,
761 .free
= spapr_irq_free_xics
,
762 .print_info
= spapr_irq_print_info_xics
,
763 .dt_populate
= spapr_dt_xics
,
764 .cpu_intc_create
= spapr_irq_cpu_intc_create_xics
,
765 .post_load
= spapr_irq_post_load_xics
,
766 .reset
= spapr_irq_reset_xics
,
767 .set_irq
= spapr_irq_set_irq_xics
,
768 .init_kvm
= spapr_irq_init_kvm_xics
,