hw/arm/integratorcp.c

   1 /*
   2  * ARM Integrator CP System emulation.
   3  *
   4  * Copyright (c) 2005-2007 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL
   8  */
   9
  10 #include "qemu/osdep.h"
  11 #include "qapi/error.h"
  12 #include "hw/sysbus.h"
  13 #include "hw/devices.h"
  14 #include "hw/boards.h"
  15 #include "hw/arm/arm.h"
  16 #include "hw/misc/arm_integrator_debug.h"
  17 #include "net/net.h"
  18 #include "exec/address-spaces.h"
  19 #include "sysemu/sysemu.h"
  20 #include "qemu/error-report.h"
  21
  22 #define TYPE_INTEGRATOR_CM "integrator_core"
  23 #define INTEGRATOR_CM(obj) \
  24     OBJECT_CHECK(IntegratorCMState, (obj), TYPE_INTEGRATOR_CM)
  25
  26 typedef struct IntegratorCMState {
  27     /*< private >*/
  28     SysBusDevice parent_obj;
  29     /*< public >*/
  30
  31     MemoryRegion iomem;
  32     uint32_t memsz;
  33     MemoryRegion flash;
  34     uint32_t cm_osc;
  35     uint32_t cm_ctrl;
  36     uint32_t cm_lock;
  37     uint32_t cm_auxosc;
  38     uint32_t cm_sdram;
  39     uint32_t cm_init;
  40     uint32_t cm_flags;
  41     uint32_t cm_nvflags;
  42     uint32_t cm_refcnt_offset;
  43     uint32_t int_level;
  44     uint32_t irq_enabled;
  45     uint32_t fiq_enabled;
  46 } IntegratorCMState;
  47
  48 static uint8_t integrator_spd[128] = {
  49    128, 8, 4, 11, 9, 1, 64, 0,  2, 0xa0, 0xa0, 0, 0, 8, 0, 1,
  50    0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40
  51 };
  52
  53 static uint64_t integratorcm_read(void *opaque, hwaddr offset,
  54                                   unsigned size)
  55 {
  56     IntegratorCMState *s = opaque;
  57     if (offset >= 0x100 && offset < 0x200) {
  58         /* CM_SPD */
  59         if (offset >= 0x180)
  60             return 0;
  61         return integrator_spd[offset >> 2];
  62     }
  63     switch (offset >> 2) {
  64     case 0: /* CM_ID */
  65         return 0x411a3001;
  66     case 1: /* CM_PROC */
  67         return 0;
  68     case 2: /* CM_OSC */
  69         return s->cm_osc;
  70     case 3: /* CM_CTRL */
  71         return s->cm_ctrl;
  72     case 4: /* CM_STAT */
  73         return 0x00100000;
  74     case 5: /* CM_LOCK */
  75         if (s->cm_lock == 0xa05f) {
  76             return 0x1a05f;
  77         } else {
  78             return s->cm_lock;
  79         }
  80     case 6: /* CM_LMBUSCNT */
  81         /* ??? High frequency timer.  */
  82         hw_error("integratorcm_read: CM_LMBUSCNT");
  83     case 7: /* CM_AUXOSC */
  84         return s->cm_auxosc;
  85     case 8: /* CM_SDRAM */
  86         return s->cm_sdram;
  87     case 9: /* CM_INIT */
  88         return s->cm_init;
  89     case 10: /* CM_REFCNT */
  90         /* This register, CM_REFCNT, provides a 32-bit count value.
  91          * The count increments at the fixed reference clock frequency of 24MHz
  92          * and can be used as a real-time counter.
  93          */
  94         return (uint32_t)muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24,
  95                                   1000) - s->cm_refcnt_offset;
  96     case 12: /* CM_FLAGS */
  97         return s->cm_flags;
  98     case 14: /* CM_NVFLAGS */
  99         return s->cm_nvflags;
 100     case 16: /* CM_IRQ_STAT */
 101         return s->int_level & s->irq_enabled;
 102     case 17: /* CM_IRQ_RSTAT */
 103         return s->int_level;
 104     case 18: /* CM_IRQ_ENSET */
 105         return s->irq_enabled;
 106     case 20: /* CM_SOFT_INTSET */
 107         return s->int_level & 1;
 108     case 24: /* CM_FIQ_STAT */
 109         return s->int_level & s->fiq_enabled;
 110     case 25: /* CM_FIQ_RSTAT */
 111         return s->int_level;
 112     case 26: /* CM_FIQ_ENSET */
 113         return s->fiq_enabled;
 114     case 32: /* CM_VOLTAGE_CTL0 */
 115     case 33: /* CM_VOLTAGE_CTL1 */
 116     case 34: /* CM_VOLTAGE_CTL2 */
 117     case 35: /* CM_VOLTAGE_CTL3 */
 118         /* ??? Voltage control unimplemented.  */
 119         return 0;
 120     default:
 121         hw_error("integratorcm_read: Unimplemented offset 0x%x\n",
 122                  (int)offset);
 123         return 0;
 124     }
 125 }
 126
 127 static void integratorcm_do_remap(IntegratorCMState *s)
 128 {
 129     /* Sync memory region state with CM_CTRL REMAP bit:
 130      * bit 0 => flash at address 0; bit 1 => RAM
 131      */
 132     memory_region_set_enabled(&s->flash, !(s->cm_ctrl & 4));
 133 }
 134
 135 static void integratorcm_set_ctrl(IntegratorCMState *s, uint32_t value)
 136 {
 137     if (value & 8) {
 138         qemu_system_reset_request();
 139     }
 140     if ((s->cm_ctrl ^ value) & 1) {
 141         /* (value & 1) != 0 means the green "MISC LED" is lit.
 142          * We don't have any nice place to display LEDs. printf is a bad
 143          * idea because Linux uses the LED as a heartbeat and the output
 144          * will swamp anything else on the terminal.
 145          */
 146     }
 147     /* Note that the RESET bit [3] always reads as zero */
 148     s->cm_ctrl = (s->cm_ctrl & ~5) | (value & 5);
 149     integratorcm_do_remap(s);
 150 }
 151
 152 static void integratorcm_update(IntegratorCMState *s)
 153 {
 154     /* ??? The CPU irq/fiq is raised when either the core module or base PIC
 155        are active.  */
 156     if (s->int_level & (s->irq_enabled | s->fiq_enabled))
 157         hw_error("Core module interrupt\n");
 158 }
 159
 160 static void integratorcm_write(void *opaque, hwaddr offset,
 161                                uint64_t value, unsigned size)
 162 {
 163     IntegratorCMState *s = opaque;
 164     switch (offset >> 2) {
 165     case 2: /* CM_OSC */
 166         if (s->cm_lock == 0xa05f)
 167             s->cm_osc = value;
 168         break;
 169     case 3: /* CM_CTRL */
 170         integratorcm_set_ctrl(s, value);
 171         break;
 172     case 5: /* CM_LOCK */
 173         s->cm_lock = value & 0xffff;
 174         break;
 175     case 7: /* CM_AUXOSC */
 176         if (s->cm_lock == 0xa05f)
 177             s->cm_auxosc = value;
 178         break;
 179     case 8: /* CM_SDRAM */
 180         s->cm_sdram = value;
 181         break;
 182     case 9: /* CM_INIT */
 183         /* ??? This can change the memory bus frequency.  */
 184         s->cm_init = value;
 185         break;
 186     case 12: /* CM_FLAGSS */
 187         s->cm_flags |= value;
 188         break;
 189     case 13: /* CM_FLAGSC */
 190         s->cm_flags &= ~value;
 191         break;
 192     case 14: /* CM_NVFLAGSS */
 193         s->cm_nvflags |= value;
 194         break;
 195     case 15: /* CM_NVFLAGSS */
 196         s->cm_nvflags &= ~value;
 197         break;
 198     case 18: /* CM_IRQ_ENSET */
 199         s->irq_enabled |= value;
 200         integratorcm_update(s);
 201         break;
 202     case 19: /* CM_IRQ_ENCLR */
 203         s->irq_enabled &= ~value;
 204         integratorcm_update(s);
 205         break;
 206     case 20: /* CM_SOFT_INTSET */
 207         s->int_level |= (value & 1);
 208         integratorcm_update(s);
 209         break;
 210     case 21: /* CM_SOFT_INTCLR */
 211         s->int_level &= ~(value & 1);
 212         integratorcm_update(s);
 213         break;
 214     case 26: /* CM_FIQ_ENSET */
 215         s->fiq_enabled |= value;
 216         integratorcm_update(s);
 217         break;
 218     case 27: /* CM_FIQ_ENCLR */
 219         s->fiq_enabled &= ~value;
 220         integratorcm_update(s);
 221         break;
 222     case 32: /* CM_VOLTAGE_CTL0 */
 223     case 33: /* CM_VOLTAGE_CTL1 */
 224     case 34: /* CM_VOLTAGE_CTL2 */
 225     case 35: /* CM_VOLTAGE_CTL3 */
 226         /* ??? Voltage control unimplemented.  */
 227         break;
 228     default:
 229         hw_error("integratorcm_write: Unimplemented offset 0x%x\n",
 230                  (int)offset);
 231         break;
 232     }
 233 }
 234
 235 /* Integrator/CM control registers.  */
 236
 237 static const MemoryRegionOps integratorcm_ops = {
 238     .read = integratorcm_read,
 239     .write = integratorcm_write,
 240     .endianness = DEVICE_NATIVE_ENDIAN,
 241 };
 242
 243 static int integratorcm_init(SysBusDevice *dev)
 244 {
 245     IntegratorCMState *s = INTEGRATOR_CM(dev);
 246
 247     s->cm_osc = 0x01000048;
 248     /* ??? What should the high bits of this value be?  */
 249     s->cm_auxosc = 0x0007feff;
 250     s->cm_sdram = 0x00011122;
 251     if (s->memsz >= 256) {
 252         integrator_spd[31] = 64;
 253         s->cm_sdram |= 0x10;
 254     } else if (s->memsz >= 128) {
 255         integrator_spd[31] = 32;
 256         s->cm_sdram |= 0x0c;
 257     } else if (s->memsz >= 64) {
 258         integrator_spd[31] = 16;
 259         s->cm_sdram |= 0x08;
 260     } else if (s->memsz >= 32) {
 261         integrator_spd[31] = 4;
 262         s->cm_sdram |= 0x04;
 263     } else {
 264         integrator_spd[31] = 2;
 265     }
 266     memcpy(integrator_spd + 73, "QEMU-MEMORY", 11);
 267     s->cm_init = 0x00000112;
 268     s->cm_refcnt_offset = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24,
 269                                    1000);
 270     memory_region_init_ram(&s->flash, OBJECT(s), "integrator.flash", 0x100000,
 271                            &error_fatal);
 272     vmstate_register_ram_global(&s->flash);
 273
 274     memory_region_init_io(&s->iomem, OBJECT(s), &integratorcm_ops, s,
 275                           "integratorcm", 0x00800000);
 276     sysbus_init_mmio(dev, &s->iomem);
 277
 278     integratorcm_do_remap(s);
 279     /* ??? Save/restore.  */
 280     return 0;
 281 }
 282
 283 /* Integrator/CP hardware emulation.  */
 284 /* Primary interrupt controller.  */
 285
 286 #define TYPE_INTEGRATOR_PIC "integrator_pic"
 287 #define INTEGRATOR_PIC(obj) \
 288    OBJECT_CHECK(icp_pic_state, (obj), TYPE_INTEGRATOR_PIC)
 289
 290 typedef struct icp_pic_state {
 291     /*< private >*/
 292     SysBusDevice parent_obj;
 293     /*< public >*/
 294
 295     MemoryRegion iomem;
 296     uint32_t level;
 297     uint32_t irq_enabled;
 298     uint32_t fiq_enabled;
 299     qemu_irq parent_irq;
 300     qemu_irq parent_fiq;
 301 } icp_pic_state;
 302
 303 static void icp_pic_update(icp_pic_state *s)
 304 {
 305     uint32_t flags;
 306
 307     flags = (s->level & s->irq_enabled);
 308     qemu_set_irq(s->parent_irq, flags != 0);
 309     flags = (s->level & s->fiq_enabled);
 310     qemu_set_irq(s->parent_fiq, flags != 0);
 311 }
 312
 313 static void icp_pic_set_irq(void *opaque, int irq, int level)
 314 {
 315     icp_pic_state *s = (icp_pic_state *)opaque;
 316     if (level)
 317         s->level |= 1 << irq;
 318     else
 319         s->level &= ~(1 << irq);
 320     icp_pic_update(s);
 321 }
 322
 323 static uint64_t icp_pic_read(void *opaque, hwaddr offset,
 324                              unsigned size)
 325 {
 326     icp_pic_state *s = (icp_pic_state *)opaque;
 327
 328     switch (offset >> 2) {
 329     case 0: /* IRQ_STATUS */
 330         return s->level & s->irq_enabled;
 331     case 1: /* IRQ_RAWSTAT */
 332         return s->level;
 333     case 2: /* IRQ_ENABLESET */
 334         return s->irq_enabled;
 335     case 4: /* INT_SOFTSET */
 336         return s->level & 1;
 337     case 8: /* FRQ_STATUS */
 338         return s->level & s->fiq_enabled;
 339     case 9: /* FRQ_RAWSTAT */
 340         return s->level;
 341     case 10: /* FRQ_ENABLESET */
 342         return s->fiq_enabled;
 343     case 3: /* IRQ_ENABLECLR */
 344     case 5: /* INT_SOFTCLR */
 345     case 11: /* FRQ_ENABLECLR */
 346     default:
 347         printf ("icp_pic_read: Bad register offset 0x%x\n", (int)offset);
 348         return 0;
 349     }
 350 }
 351
 352 static void icp_pic_write(void *opaque, hwaddr offset,
 353                           uint64_t value, unsigned size)
 354 {
 355     icp_pic_state *s = (icp_pic_state *)opaque;
 356
 357     switch (offset >> 2) {
 358     case 2: /* IRQ_ENABLESET */
 359         s->irq_enabled |= value;
 360         break;
 361     case 3: /* IRQ_ENABLECLR */
 362         s->irq_enabled &= ~value;
 363         break;
 364     case 4: /* INT_SOFTSET */
 365         if (value & 1)
 366             icp_pic_set_irq(s, 0, 1);
 367         break;
 368     case 5: /* INT_SOFTCLR */
 369         if (value & 1)
 370             icp_pic_set_irq(s, 0, 0);
 371         break;
 372     case 10: /* FRQ_ENABLESET */
 373         s->fiq_enabled |= value;
 374         break;
 375     case 11: /* FRQ_ENABLECLR */
 376         s->fiq_enabled &= ~value;
 377         break;
 378     case 0: /* IRQ_STATUS */
 379     case 1: /* IRQ_RAWSTAT */
 380     case 8: /* FRQ_STATUS */
 381     case 9: /* FRQ_RAWSTAT */
 382     default:
 383         printf ("icp_pic_write: Bad register offset 0x%x\n", (int)offset);
 384         return;
 385     }
 386     icp_pic_update(s);
 387 }
 388
 389 static const MemoryRegionOps icp_pic_ops = {
 390     .read = icp_pic_read,
 391     .write = icp_pic_write,
 392     .endianness = DEVICE_NATIVE_ENDIAN,
 393 };
 394
 395 static int icp_pic_init(SysBusDevice *sbd)
 396 {
 397     DeviceState *dev = DEVICE(sbd);
 398     icp_pic_state *s = INTEGRATOR_PIC(dev);
 399
 400     qdev_init_gpio_in(dev, icp_pic_set_irq, 32);
 401     sysbus_init_irq(sbd, &s->parent_irq);
 402     sysbus_init_irq(sbd, &s->parent_fiq);
 403     memory_region_init_io(&s->iomem, OBJECT(s), &icp_pic_ops, s,
 404                           "icp-pic", 0x00800000);
 405     sysbus_init_mmio(sbd, &s->iomem);
 406     return 0;
 407 }
 408
 409 /* CP control registers.  */
 410
 411 #define TYPE_ICP_CONTROL_REGS "icp-ctrl-regs"
 412 #define ICP_CONTROL_REGS(obj) \
 413     OBJECT_CHECK(ICPCtrlRegsState, (obj), TYPE_ICP_CONTROL_REGS)
 414
 415 typedef struct ICPCtrlRegsState {
 416     /*< private >*/
 417     SysBusDevice parent_obj;
 418     /*< public >*/
 419
 420     MemoryRegion iomem;
 421
 422     qemu_irq mmc_irq;
 423     uint32_t intreg_state;
 424 } ICPCtrlRegsState;
 425
 426 #define ICP_GPIO_MMC_WPROT      "mmc-wprot"
 427 #define ICP_GPIO_MMC_CARDIN     "mmc-cardin"
 428
 429 #define ICP_INTREG_WPROT        (1 << 0)
 430 #define ICP_INTREG_CARDIN       (1 << 3)
 431
 432 static uint64_t icp_control_read(void *opaque, hwaddr offset,
 433                                  unsigned size)
 434 {
 435     ICPCtrlRegsState *s = opaque;
 436
 437     switch (offset >> 2) {
 438     case 0: /* CP_IDFIELD */
 439         return 0x41034003;
 440     case 1: /* CP_FLASHPROG */
 441         return 0;
 442     case 2: /* CP_INTREG */
 443         return s->intreg_state;
 444     case 3: /* CP_DECODE */
 445         return 0x11;
 446     default:
 447         hw_error("icp_control_read: Bad offset %x\n", (int)offset);
 448         return 0;
 449     }
 450 }
 451
 452 static void icp_control_write(void *opaque, hwaddr offset,
 453                           uint64_t value, unsigned size)
 454 {
 455     ICPCtrlRegsState *s = opaque;
 456
 457     switch (offset >> 2) {
 458     case 2: /* CP_INTREG */
 459         s->intreg_state &= ~(value & ICP_INTREG_CARDIN);
 460         qemu_set_irq(s->mmc_irq, !!(s->intreg_state & ICP_INTREG_CARDIN));
 461         break;
 462     case 1: /* CP_FLASHPROG */
 463     case 3: /* CP_DECODE */
 464         /* Nothing interesting implemented yet.  */
 465         break;
 466     default:
 467         hw_error("icp_control_write: Bad offset %x\n", (int)offset);
 468     }
 469 }
 470
 471 static const MemoryRegionOps icp_control_ops = {
 472     .read = icp_control_read,
 473     .write = icp_control_write,
 474     .endianness = DEVICE_NATIVE_ENDIAN,
 475 };
 476
 477 static void icp_control_mmc_wprot(void *opaque, int line, int level)
 478 {
 479     ICPCtrlRegsState *s = opaque;
 480
 481     s->intreg_state &= ~ICP_INTREG_WPROT;
 482     if (level) {
 483         s->intreg_state |= ICP_INTREG_WPROT;
 484     }
 485 }
 486
 487 static void icp_control_mmc_cardin(void *opaque, int line, int level)
 488 {
 489     ICPCtrlRegsState *s = opaque;
 490
 491     /* line is released by writing to CP_INTREG */
 492     if (level) {
 493         s->intreg_state |= ICP_INTREG_CARDIN;
 494         qemu_set_irq(s->mmc_irq, 1);
 495     }
 496 }
 497
 498 static void icp_control_init(Object *obj)
 499 {
 500     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 501     ICPCtrlRegsState *s = ICP_CONTROL_REGS(obj);
 502     DeviceState *dev = DEVICE(obj);
 503
 504     memory_region_init_io(&s->iomem, OBJECT(s), &icp_control_ops, s,
 505                           "icp_ctrl_regs", 0x00800000);
 506     sysbus_init_mmio(sbd, &s->iomem);
 507
 508     qdev_init_gpio_in_named(dev, icp_control_mmc_wprot, ICP_GPIO_MMC_WPROT, 1);
 509     qdev_init_gpio_in_named(dev, icp_control_mmc_cardin,
 510                             ICP_GPIO_MMC_CARDIN, 1);
 511     sysbus_init_irq(sbd, &s->mmc_irq);
 512 }
 513
 514
 515 /* Board init.  */
 516
 517 static struct arm_boot_info integrator_binfo = {
 518     .loader_start = 0x0,
 519     .board_id = 0x113,
 520 };
 521
 522 static void integratorcp_init(MachineState *machine)
 523 {
 524     ram_addr_t ram_size = machine->ram_size;
 525     const char *cpu_model = machine->cpu_model;
 526     const char *kernel_filename = machine->kernel_filename;
 527     const char *kernel_cmdline = machine->kernel_cmdline;
 528     const char *initrd_filename = machine->initrd_filename;
 529     ObjectClass *cpu_oc;
 530     Object *cpuobj;
 531     ARMCPU *cpu;
 532     MemoryRegion *address_space_mem = get_system_memory();
 533     MemoryRegion *ram = g_new(MemoryRegion, 1);
 534     MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
 535     qemu_irq pic[32];
 536     DeviceState *dev, *sic, *icp;
 537     int i;
 538
 539     if (!cpu_model) {
 540         cpu_model = "arm926";
 541     }
 542
 543     cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
 544     if (!cpu_oc) {
 545         fprintf(stderr, "Unable to find CPU definition\n");
 546         exit(1);
 547     }
 548
 549     cpuobj = object_new(object_class_get_name(cpu_oc));
 550
 551     /* By default ARM1176 CPUs have EL3 enabled.  This board does not
 552      * currently support EL3 so the CPU EL3 property is disabled before
 553      * realization.
 554      */
 555     if (object_property_find(cpuobj, "has_el3", NULL)) {
 556         object_property_set_bool(cpuobj, false, "has_el3", &error_fatal);
 557     }
 558
 559     object_property_set_bool(cpuobj, true, "realized", &error_fatal);
 560
 561     cpu = ARM_CPU(cpuobj);
 562
 563     memory_region_allocate_system_memory(ram, NULL, "integrator.ram",
 564                                          ram_size);
 565     /* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash.  */
 566     /* ??? RAM should repeat to fill physical memory space.  */
 567     /* SDRAM at address zero*/
 568     memory_region_add_subregion(address_space_mem, 0, ram);
 569     /* And again at address 0x80000000 */
 570     memory_region_init_alias(ram_alias, NULL, "ram.alias", ram, 0, ram_size);
 571     memory_region_add_subregion(address_space_mem, 0x80000000, ram_alias);
 572
 573     dev = qdev_create(NULL, TYPE_INTEGRATOR_CM);
 574     qdev_prop_set_uint32(dev, "memsz", ram_size >> 20);
 575     qdev_init_nofail(dev);
 576     sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000);
 577
 578     dev = sysbus_create_varargs(TYPE_INTEGRATOR_PIC, 0x14000000,
 579                                 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ),
 580                                 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ),
 581                                 NULL);
 582     for (i = 0; i < 32; i++) {
 583         pic[i] = qdev_get_gpio_in(dev, i);
 584     }
 585     sic = sysbus_create_simple(TYPE_INTEGRATOR_PIC, 0xca000000, pic[26]);
 586     sysbus_create_varargs("integrator_pit", 0x13000000,
 587                           pic[5], pic[6], pic[7], NULL);
 588     sysbus_create_simple("pl031", 0x15000000, pic[8]);
 589     sysbus_create_simple("pl011", 0x16000000, pic[1]);
 590     sysbus_create_simple("pl011", 0x17000000, pic[2]);
 591     icp = sysbus_create_simple(TYPE_ICP_CONTROL_REGS, 0xcb000000,
 592                                qdev_get_gpio_in(sic, 3));
 593     sysbus_create_simple("pl050_keyboard", 0x18000000, pic[3]);
 594     sysbus_create_simple("pl050_mouse", 0x19000000, pic[4]);
 595     sysbus_create_simple(TYPE_INTEGRATOR_DEBUG, 0x1a000000, 0);
 596
 597     dev = sysbus_create_varargs("pl181", 0x1c000000, pic[23], pic[24], NULL);
 598     qdev_connect_gpio_out(dev, 0,
 599                           qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_WPROT, 0));
 600     qdev_connect_gpio_out(dev, 1,
 601                           qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_CARDIN, 0));
 602
 603     if (nd_table[0].used)
 604         smc91c111_init(&nd_table[0], 0xc8000000, pic[27]);
 605
 606     sysbus_create_simple("pl110", 0xc0000000, pic[22]);
 607
 608     integrator_binfo.ram_size = ram_size;
 609     integrator_binfo.kernel_filename = kernel_filename;
 610     integrator_binfo.kernel_cmdline = kernel_cmdline;
 611     integrator_binfo.initrd_filename = initrd_filename;
 612     arm_load_kernel(cpu, &integrator_binfo);
 613 }
 614
 615 static void integratorcp_machine_init(MachineClass *mc)
 616 {
 617     mc->desc = "ARM Integrator/CP (ARM926EJ-S)";
 618     mc->init = integratorcp_init;
 619 }
 620
 621 DEFINE_MACHINE("integratorcp", integratorcp_machine_init)
 622
 623 static Property core_properties[] = {
 624     DEFINE_PROP_UINT32("memsz", IntegratorCMState, memsz, 0),
 625     DEFINE_PROP_END_OF_LIST(),
 626 };
 627
 628 static void core_class_init(ObjectClass *klass, void *data)
 629 {
 630     DeviceClass *dc = DEVICE_CLASS(klass);
 631     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 632
 633     k->init = integratorcm_init;
 634     dc->props = core_properties;
 635 }
 636
 637 static const TypeInfo core_info = {
 638     .name          = TYPE_INTEGRATOR_CM,
 639     .parent        = TYPE_SYS_BUS_DEVICE,
 640     .instance_size = sizeof(IntegratorCMState),
 641     .class_init    = core_class_init,
 642 };
 643
 644 static void icp_pic_class_init(ObjectClass *klass, void *data)
 645 {
 646     SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
 647
 648     sdc->init = icp_pic_init;
 649 }
 650
 651 static const TypeInfo icp_pic_info = {
 652     .name          = TYPE_INTEGRATOR_PIC,
 653     .parent        = TYPE_SYS_BUS_DEVICE,
 654     .instance_size = sizeof(icp_pic_state),
 655     .class_init    = icp_pic_class_init,
 656 };
 657
 658 static const TypeInfo icp_ctrl_regs_info = {
 659     .name          = TYPE_ICP_CONTROL_REGS,
 660     .parent        = TYPE_SYS_BUS_DEVICE,
 661     .instance_size = sizeof(ICPCtrlRegsState),
 662     .instance_init = icp_control_init,
 663 };
 664
 665 static void integratorcp_register_types(void)
 666 {
 667     type_register_static(&icp_pic_info);
 668     type_register_static(&core_info);
 669     type_register_static(&icp_ctrl_regs_info);
 670 }
 671
 672 type_init(integratorcp_register_types)