hw/arm/integratorcp.c

   1 /*
   2  * ARM Integrator CP System emulation.
   3  *
   4  * Copyright (c) 2005-2007 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL
   8  */
   9
  10 #include "qemu/osdep.h"
  11 #include "qapi/error.h"
  12 #include "hw/sysbus.h"
  13 #include "migration/vmstate.h"
  14 #include "hw/boards.h"
  15 #include "hw/arm/boot.h"
  16 #include "hw/misc/arm_integrator_debug.h"
  17 #include "hw/net/smc91c111.h"
  18 #include "net/net.h"
  19 #include "exec/address-spaces.h"
  20 #include "sysemu/runstate.h"
  21 #include "sysemu/sysemu.h"
  22 #include "qemu/log.h"
  23 #include "qemu/error-report.h"
  24 #include "hw/char/pl011.h"
  25 #include "hw/hw.h"
  26 #include "hw/irq.h"
  27 #include "hw/sd/sd.h"
  28 #include "qom/object.h"
  29 #include "audio/audio.h"
  30 #include "target/arm/cpu-qom.h"
  31
  32 #define TYPE_INTEGRATOR_CM "integrator_core"
  33 OBJECT_DECLARE_SIMPLE_TYPE(IntegratorCMState, INTEGRATOR_CM)
  34
  35 struct IntegratorCMState {
  36     /*< private >*/
  37     SysBusDevice parent_obj;
  38     /*< public >*/
  39
  40     MemoryRegion iomem;
  41     uint32_t memsz;
  42     MemoryRegion flash;
  43     uint32_t cm_osc;
  44     uint32_t cm_ctrl;
  45     uint32_t cm_lock;
  46     uint32_t cm_auxosc;
  47     uint32_t cm_sdram;
  48     uint32_t cm_init;
  49     uint32_t cm_flags;
  50     uint32_t cm_nvflags;
  51     uint32_t cm_refcnt_offset;
  52     uint32_t int_level;
  53     uint32_t irq_enabled;
  54     uint32_t fiq_enabled;
  55 };
  56
  57 static uint8_t integrator_spd[128] = {
  58    128, 8, 4, 11, 9, 1, 64, 0,  2, 0xa0, 0xa0, 0, 0, 8, 0, 1,
  59    0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40
  60 };
  61
  62 static const VMStateDescription vmstate_integratorcm = {
  63     .name = "integratorcm",
  64     .version_id = 1,
  65     .minimum_version_id = 1,
  66     .fields = (const VMStateField[]) {
  67         VMSTATE_UINT32(cm_osc, IntegratorCMState),
  68         VMSTATE_UINT32(cm_ctrl, IntegratorCMState),
  69         VMSTATE_UINT32(cm_lock, IntegratorCMState),
  70         VMSTATE_UINT32(cm_auxosc, IntegratorCMState),
  71         VMSTATE_UINT32(cm_sdram, IntegratorCMState),
  72         VMSTATE_UINT32(cm_init, IntegratorCMState),
  73         VMSTATE_UINT32(cm_flags, IntegratorCMState),
  74         VMSTATE_UINT32(cm_nvflags, IntegratorCMState),
  75         VMSTATE_UINT32(int_level, IntegratorCMState),
  76         VMSTATE_UINT32(irq_enabled, IntegratorCMState),
  77         VMSTATE_UINT32(fiq_enabled, IntegratorCMState),
  78         VMSTATE_END_OF_LIST()
  79     }
  80 };
  81
  82 static uint64_t integratorcm_read(void *opaque, hwaddr offset,
  83                                   unsigned size)
  84 {
  85     IntegratorCMState *s = opaque;
  86     if (offset >= 0x100 && offset < 0x200) {
  87         /* CM_SPD */
  88         if (offset >= 0x180)
  89             return 0;
  90         return integrator_spd[offset >> 2];
  91     }
  92     switch (offset >> 2) {
  93     case 0: /* CM_ID */
  94         return 0x411a3001;
  95     case 1: /* CM_PROC */
  96         return 0;
  97     case 2: /* CM_OSC */
  98         return s->cm_osc;
  99     case 3: /* CM_CTRL */
 100         return s->cm_ctrl;
 101     case 4: /* CM_STAT */
 102         return 0x00100000;
 103     case 5: /* CM_LOCK */
 104         if (s->cm_lock == 0xa05f) {
 105             return 0x1a05f;
 106         } else {
 107             return s->cm_lock;
 108         }
 109     case 6: /* CM_LMBUSCNT */
 110         /* ??? High frequency timer.  */
 111         hw_error("integratorcm_read: CM_LMBUSCNT");
 112     case 7: /* CM_AUXOSC */
 113         return s->cm_auxosc;
 114     case 8: /* CM_SDRAM */
 115         return s->cm_sdram;
 116     case 9: /* CM_INIT */
 117         return s->cm_init;
 118     case 10: /* CM_REFCNT */
 119         /* This register, CM_REFCNT, provides a 32-bit count value.
 120          * The count increments at the fixed reference clock frequency of 24MHz
 121          * and can be used as a real-time counter.
 122          */
 123         return (uint32_t)muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24,
 124                                   1000) - s->cm_refcnt_offset;
 125     case 12: /* CM_FLAGS */
 126         return s->cm_flags;
 127     case 14: /* CM_NVFLAGS */
 128         return s->cm_nvflags;
 129     case 16: /* CM_IRQ_STAT */
 130         return s->int_level & s->irq_enabled;
 131     case 17: /* CM_IRQ_RSTAT */
 132         return s->int_level;
 133     case 18: /* CM_IRQ_ENSET */
 134         return s->irq_enabled;
 135     case 20: /* CM_SOFT_INTSET */
 136         return s->int_level & 1;
 137     case 24: /* CM_FIQ_STAT */
 138         return s->int_level & s->fiq_enabled;
 139     case 25: /* CM_FIQ_RSTAT */
 140         return s->int_level;
 141     case 26: /* CM_FIQ_ENSET */
 142         return s->fiq_enabled;
 143     case 32: /* CM_VOLTAGE_CTL0 */
 144     case 33: /* CM_VOLTAGE_CTL1 */
 145     case 34: /* CM_VOLTAGE_CTL2 */
 146     case 35: /* CM_VOLTAGE_CTL3 */
 147         /* ??? Voltage control unimplemented.  */
 148         return 0;
 149     default:
 150         qemu_log_mask(LOG_UNIMP,
 151                       "%s: Unimplemented offset 0x%" HWADDR_PRIX "\n",
 152                       __func__, offset);
 153         return 0;
 154     }
 155 }
 156
 157 static void integratorcm_do_remap(IntegratorCMState *s)
 158 {
 159     /* Sync memory region state with CM_CTRL REMAP bit:
 160      * bit 0 => flash at address 0; bit 1 => RAM
 161      */
 162     memory_region_set_enabled(&s->flash, !(s->cm_ctrl & 4));
 163 }
 164
 165 static void integratorcm_set_ctrl(IntegratorCMState *s, uint32_t value)
 166 {
 167     if (value & 8) {
 168         qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 169     }
 170     if ((s->cm_ctrl ^ value) & 1) {
 171         /* (value & 1) != 0 means the green "MISC LED" is lit.
 172          * We don't have any nice place to display LEDs. printf is a bad
 173          * idea because Linux uses the LED as a heartbeat and the output
 174          * will swamp anything else on the terminal.
 175          */
 176     }
 177     /* Note that the RESET bit [3] always reads as zero */
 178     s->cm_ctrl = (s->cm_ctrl & ~5) | (value & 5);
 179     integratorcm_do_remap(s);
 180 }
 181
 182 static void integratorcm_update(IntegratorCMState *s)
 183 {
 184     /* ??? The CPU irq/fiq is raised when either the core module or base PIC
 185        are active.  */
 186     if (s->int_level & (s->irq_enabled | s->fiq_enabled))
 187         hw_error("Core module interrupt\n");
 188 }
 189
 190 static void integratorcm_write(void *opaque, hwaddr offset,
 191                                uint64_t value, unsigned size)
 192 {
 193     IntegratorCMState *s = opaque;
 194     switch (offset >> 2) {
 195     case 2: /* CM_OSC */
 196         if (s->cm_lock == 0xa05f)
 197             s->cm_osc = value;
 198         break;
 199     case 3: /* CM_CTRL */
 200         integratorcm_set_ctrl(s, value);
 201         break;
 202     case 5: /* CM_LOCK */
 203         s->cm_lock = value & 0xffff;
 204         break;
 205     case 7: /* CM_AUXOSC */
 206         if (s->cm_lock == 0xa05f)
 207             s->cm_auxosc = value;
 208         break;
 209     case 8: /* CM_SDRAM */
 210         s->cm_sdram = value;
 211         break;
 212     case 9: /* CM_INIT */
 213         /* ??? This can change the memory bus frequency.  */
 214         s->cm_init = value;
 215         break;
 216     case 12: /* CM_FLAGSS */
 217         s->cm_flags |= value;
 218         break;
 219     case 13: /* CM_FLAGSC */
 220         s->cm_flags &= ~value;
 221         break;
 222     case 14: /* CM_NVFLAGSS */
 223         s->cm_nvflags |= value;
 224         break;
 225     case 15: /* CM_NVFLAGSS */
 226         s->cm_nvflags &= ~value;
 227         break;
 228     case 18: /* CM_IRQ_ENSET */
 229         s->irq_enabled |= value;
 230         integratorcm_update(s);
 231         break;
 232     case 19: /* CM_IRQ_ENCLR */
 233         s->irq_enabled &= ~value;
 234         integratorcm_update(s);
 235         break;
 236     case 20: /* CM_SOFT_INTSET */
 237         s->int_level |= (value & 1);
 238         integratorcm_update(s);
 239         break;
 240     case 21: /* CM_SOFT_INTCLR */
 241         s->int_level &= ~(value & 1);
 242         integratorcm_update(s);
 243         break;
 244     case 26: /* CM_FIQ_ENSET */
 245         s->fiq_enabled |= value;
 246         integratorcm_update(s);
 247         break;
 248     case 27: /* CM_FIQ_ENCLR */
 249         s->fiq_enabled &= ~value;
 250         integratorcm_update(s);
 251         break;
 252     case 32: /* CM_VOLTAGE_CTL0 */
 253     case 33: /* CM_VOLTAGE_CTL1 */
 254     case 34: /* CM_VOLTAGE_CTL2 */
 255     case 35: /* CM_VOLTAGE_CTL3 */
 256         /* ??? Voltage control unimplemented.  */
 257         break;
 258     default:
 259         qemu_log_mask(LOG_UNIMP,
 260                       "%s: Unimplemented offset 0x%" HWADDR_PRIX "\n",
 261                       __func__, offset);
 262         break;
 263     }
 264 }
 265
 266 /* Integrator/CM control registers.  */
 267
 268 static const MemoryRegionOps integratorcm_ops = {
 269     .read = integratorcm_read,
 270     .write = integratorcm_write,
 271     .endianness = DEVICE_NATIVE_ENDIAN,
 272 };
 273
 274 static void integratorcm_init(Object *obj)
 275 {
 276     IntegratorCMState *s = INTEGRATOR_CM(obj);
 277
 278     s->cm_osc = 0x01000048;
 279     /* ??? What should the high bits of this value be?  */
 280     s->cm_auxosc = 0x0007feff;
 281     s->cm_sdram = 0x00011122;
 282     memcpy(integrator_spd + 73, "QEMU-MEMORY", 11);
 283     s->cm_init = 0x00000112;
 284     s->cm_refcnt_offset = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24,
 285                                    1000);
 286
 287     /* ??? Save/restore.  */
 288 }
 289
 290 static void integratorcm_realize(DeviceState *d, Error **errp)
 291 {
 292     IntegratorCMState *s = INTEGRATOR_CM(d);
 293     SysBusDevice *dev = SYS_BUS_DEVICE(d);
 294
 295     if (!memory_region_init_ram(&s->flash, OBJECT(d), "integrator.flash",
 296                                 0x100000, errp)) {
 297         return;
 298     }
 299
 300     memory_region_init_io(&s->iomem, OBJECT(d), &integratorcm_ops, s,
 301                           "integratorcm", 0x00800000);
 302     sysbus_init_mmio(dev, &s->iomem);
 303
 304     integratorcm_do_remap(s);
 305
 306     if (s->memsz >= 256) {
 307         integrator_spd[31] = 64;
 308         s->cm_sdram |= 0x10;
 309     } else if (s->memsz >= 128) {
 310         integrator_spd[31] = 32;
 311         s->cm_sdram |= 0x0c;
 312     } else if (s->memsz >= 64) {
 313         integrator_spd[31] = 16;
 314         s->cm_sdram |= 0x08;
 315     } else if (s->memsz >= 32) {
 316         integrator_spd[31] = 4;
 317         s->cm_sdram |= 0x04;
 318     } else {
 319         integrator_spd[31] = 2;
 320     }
 321 }
 322
 323 /* Integrator/CP hardware emulation.  */
 324 /* Primary interrupt controller.  */
 325
 326 #define TYPE_INTEGRATOR_PIC "integrator_pic"
 327 OBJECT_DECLARE_SIMPLE_TYPE(icp_pic_state, INTEGRATOR_PIC)
 328
 329 struct icp_pic_state {
 330     /*< private >*/
 331     SysBusDevice parent_obj;
 332     /*< public >*/
 333
 334     MemoryRegion iomem;
 335     uint32_t level;
 336     uint32_t irq_enabled;
 337     uint32_t fiq_enabled;
 338     qemu_irq parent_irq;
 339     qemu_irq parent_fiq;
 340 };
 341
 342 static const VMStateDescription vmstate_icp_pic = {
 343     .name = "icp_pic",
 344     .version_id = 1,
 345     .minimum_version_id = 1,
 346     .fields = (const VMStateField[]) {
 347         VMSTATE_UINT32(level, icp_pic_state),
 348         VMSTATE_UINT32(irq_enabled, icp_pic_state),
 349         VMSTATE_UINT32(fiq_enabled, icp_pic_state),
 350         VMSTATE_END_OF_LIST()
 351     }
 352 };
 353
 354 static void icp_pic_update(icp_pic_state *s)
 355 {
 356     uint32_t flags;
 357
 358     flags = (s->level & s->irq_enabled);
 359     qemu_set_irq(s->parent_irq, flags != 0);
 360     flags = (s->level & s->fiq_enabled);
 361     qemu_set_irq(s->parent_fiq, flags != 0);
 362 }
 363
 364 static void icp_pic_set_irq(void *opaque, int irq, int level)
 365 {
 366     icp_pic_state *s = (icp_pic_state *)opaque;
 367     if (level)
 368         s->level |= 1 << irq;
 369     else
 370         s->level &= ~(1 << irq);
 371     icp_pic_update(s);
 372 }
 373
 374 static uint64_t icp_pic_read(void *opaque, hwaddr offset,
 375                              unsigned size)
 376 {
 377     icp_pic_state *s = (icp_pic_state *)opaque;
 378
 379     switch (offset >> 2) {
 380     case 0: /* IRQ_STATUS */
 381         return s->level & s->irq_enabled;
 382     case 1: /* IRQ_RAWSTAT */
 383         return s->level;
 384     case 2: /* IRQ_ENABLESET */
 385         return s->irq_enabled;
 386     case 4: /* INT_SOFTSET */
 387         return s->level & 1;
 388     case 8: /* FRQ_STATUS */
 389         return s->level & s->fiq_enabled;
 390     case 9: /* FRQ_RAWSTAT */
 391         return s->level;
 392     case 10: /* FRQ_ENABLESET */
 393         return s->fiq_enabled;
 394     case 3: /* IRQ_ENABLECLR */
 395     case 5: /* INT_SOFTCLR */
 396     case 11: /* FRQ_ENABLECLR */
 397     default:
 398         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
 399                       __func__, offset);
 400         return 0;
 401     }
 402 }
 403
 404 static void icp_pic_write(void *opaque, hwaddr offset,
 405                           uint64_t value, unsigned size)
 406 {
 407     icp_pic_state *s = (icp_pic_state *)opaque;
 408
 409     switch (offset >> 2) {
 410     case 2: /* IRQ_ENABLESET */
 411         s->irq_enabled |= value;
 412         break;
 413     case 3: /* IRQ_ENABLECLR */
 414         s->irq_enabled &= ~value;
 415         break;
 416     case 4: /* INT_SOFTSET */
 417         if (value & 1)
 418             icp_pic_set_irq(s, 0, 1);
 419         break;
 420     case 5: /* INT_SOFTCLR */
 421         if (value & 1)
 422             icp_pic_set_irq(s, 0, 0);
 423         break;
 424     case 10: /* FRQ_ENABLESET */
 425         s->fiq_enabled |= value;
 426         break;
 427     case 11: /* FRQ_ENABLECLR */
 428         s->fiq_enabled &= ~value;
 429         break;
 430     case 0: /* IRQ_STATUS */
 431     case 1: /* IRQ_RAWSTAT */
 432     case 8: /* FRQ_STATUS */
 433     case 9: /* FRQ_RAWSTAT */
 434     default:
 435         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
 436                       __func__, offset);
 437         return;
 438     }
 439     icp_pic_update(s);
 440 }
 441
 442 static const MemoryRegionOps icp_pic_ops = {
 443     .read = icp_pic_read,
 444     .write = icp_pic_write,
 445     .endianness = DEVICE_NATIVE_ENDIAN,
 446 };
 447
 448 static void icp_pic_init(Object *obj)
 449 {
 450     DeviceState *dev = DEVICE(obj);
 451     icp_pic_state *s = INTEGRATOR_PIC(obj);
 452     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 453
 454     qdev_init_gpio_in(dev, icp_pic_set_irq, 32);
 455     sysbus_init_irq(sbd, &s->parent_irq);
 456     sysbus_init_irq(sbd, &s->parent_fiq);
 457     memory_region_init_io(&s->iomem, obj, &icp_pic_ops, s,
 458                           "icp-pic", 0x00800000);
 459     sysbus_init_mmio(sbd, &s->iomem);
 460 }
 461
 462 /* CP control registers.  */
 463
 464 #define TYPE_ICP_CONTROL_REGS "icp-ctrl-regs"
 465 OBJECT_DECLARE_SIMPLE_TYPE(ICPCtrlRegsState, ICP_CONTROL_REGS)
 466
 467 struct ICPCtrlRegsState {
 468     /*< private >*/
 469     SysBusDevice parent_obj;
 470     /*< public >*/
 471
 472     MemoryRegion iomem;
 473
 474     qemu_irq mmc_irq;
 475     uint32_t intreg_state;
 476 };
 477
 478 #define ICP_GPIO_MMC_WPROT      "mmc-wprot"
 479 #define ICP_GPIO_MMC_CARDIN     "mmc-cardin"
 480
 481 #define ICP_INTREG_WPROT        (1 << 0)
 482 #define ICP_INTREG_CARDIN       (1 << 3)
 483
 484 static const VMStateDescription vmstate_icp_control = {
 485     .name = "icp_control",
 486     .version_id = 1,
 487     .minimum_version_id = 1,
 488     .fields = (const VMStateField[]) {
 489         VMSTATE_UINT32(intreg_state, ICPCtrlRegsState),
 490         VMSTATE_END_OF_LIST()
 491     }
 492 };
 493
 494 static uint64_t icp_control_read(void *opaque, hwaddr offset,
 495                                  unsigned size)
 496 {
 497     ICPCtrlRegsState *s = opaque;
 498
 499     switch (offset >> 2) {
 500     case 0: /* CP_IDFIELD */
 501         return 0x41034003;
 502     case 1: /* CP_FLASHPROG */
 503         return 0;
 504     case 2: /* CP_INTREG */
 505         return s->intreg_state;
 506     case 3: /* CP_DECODE */
 507         return 0x11;
 508     default:
 509         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
 510                       __func__, offset);
 511         return 0;
 512     }
 513 }
 514
 515 static void icp_control_write(void *opaque, hwaddr offset,
 516                           uint64_t value, unsigned size)
 517 {
 518     ICPCtrlRegsState *s = opaque;
 519
 520     switch (offset >> 2) {
 521     case 2: /* CP_INTREG */
 522         s->intreg_state &= ~(value & ICP_INTREG_CARDIN);
 523         qemu_set_irq(s->mmc_irq, !!(s->intreg_state & ICP_INTREG_CARDIN));
 524         break;
 525     case 1: /* CP_FLASHPROG */
 526     case 3: /* CP_DECODE */
 527         /* Nothing interesting implemented yet.  */
 528         break;
 529     default:
 530         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
 531                       __func__, offset);
 532     }
 533 }
 534
 535 static const MemoryRegionOps icp_control_ops = {
 536     .read = icp_control_read,
 537     .write = icp_control_write,
 538     .endianness = DEVICE_NATIVE_ENDIAN,
 539 };
 540
 541 static void icp_control_mmc_wprot(void *opaque, int line, int level)
 542 {
 543     ICPCtrlRegsState *s = opaque;
 544
 545     s->intreg_state &= ~ICP_INTREG_WPROT;
 546     if (level) {
 547         s->intreg_state |= ICP_INTREG_WPROT;
 548     }
 549 }
 550
 551 static void icp_control_mmc_cardin(void *opaque, int line, int level)
 552 {
 553     ICPCtrlRegsState *s = opaque;
 554
 555     /* line is released by writing to CP_INTREG */
 556     if (level) {
 557         s->intreg_state |= ICP_INTREG_CARDIN;
 558         qemu_set_irq(s->mmc_irq, 1);
 559     }
 560 }
 561
 562 static void icp_control_init(Object *obj)
 563 {
 564     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 565     ICPCtrlRegsState *s = ICP_CONTROL_REGS(obj);
 566     DeviceState *dev = DEVICE(obj);
 567
 568     memory_region_init_io(&s->iomem, OBJECT(s), &icp_control_ops, s,
 569                           "icp_ctrl_regs", 0x00800000);
 570     sysbus_init_mmio(sbd, &s->iomem);
 571
 572     qdev_init_gpio_in_named(dev, icp_control_mmc_wprot, ICP_GPIO_MMC_WPROT, 1);
 573     qdev_init_gpio_in_named(dev, icp_control_mmc_cardin,
 574                             ICP_GPIO_MMC_CARDIN, 1);
 575     sysbus_init_irq(sbd, &s->mmc_irq);
 576 }
 577
 578
 579 /* Board init.  */
 580
 581 static struct arm_boot_info integrator_binfo = {
 582     .loader_start = 0x0,
 583     .board_id = 0x113,
 584 };
 585
 586 static void integratorcp_init(MachineState *machine)
 587 {
 588     ram_addr_t ram_size = machine->ram_size;
 589     Object *cpuobj;
 590     ARMCPU *cpu;
 591     MemoryRegion *address_space_mem = get_system_memory();
 592     MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
 593     qemu_irq pic[32];
 594     DeviceState *dev, *sic, *icp;
 595     DriveInfo *dinfo;
 596     int i;
 597
 598     cpuobj = object_new(machine->cpu_type);
 599
 600     /* By default ARM1176 CPUs have EL3 enabled.  This board does not
 601      * currently support EL3 so the CPU EL3 property is disabled before
 602      * realization.
 603      */
 604     if (object_property_find(cpuobj, "has_el3")) {
 605         object_property_set_bool(cpuobj, "has_el3", false, &error_fatal);
 606     }
 607
 608     qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
 609
 610     cpu = ARM_CPU(cpuobj);
 611
 612     /* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash.  */
 613     /* ??? RAM should repeat to fill physical memory space.  */
 614     /* SDRAM at address zero*/
 615     memory_region_add_subregion(address_space_mem, 0, machine->ram);
 616     /* And again at address 0x80000000 */
 617     memory_region_init_alias(ram_alias, NULL, "ram.alias", machine->ram,
 618                              0, ram_size);
 619     memory_region_add_subregion(address_space_mem, 0x80000000, ram_alias);
 620
 621     dev = qdev_new(TYPE_INTEGRATOR_CM);
 622     qdev_prop_set_uint32(dev, "memsz", ram_size >> 20);
 623     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 624     sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000);
 625
 626     dev = sysbus_create_varargs(TYPE_INTEGRATOR_PIC, 0x14000000,
 627                                 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ),
 628                                 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ),
 629                                 NULL);
 630     for (i = 0; i < 32; i++) {
 631         pic[i] = qdev_get_gpio_in(dev, i);
 632     }
 633     sic = sysbus_create_simple(TYPE_INTEGRATOR_PIC, 0xca000000, pic[26]);
 634     sysbus_create_varargs("integrator_pit", 0x13000000,
 635                           pic[5], pic[6], pic[7], NULL);
 636     sysbus_create_simple("pl031", 0x15000000, pic[8]);
 637     pl011_create(0x16000000, pic[1], serial_hd(0));
 638     pl011_create(0x17000000, pic[2], serial_hd(1));
 639     icp = sysbus_create_simple(TYPE_ICP_CONTROL_REGS, 0xcb000000,
 640                                qdev_get_gpio_in(sic, 3));
 641     sysbus_create_simple("pl050_keyboard", 0x18000000, pic[3]);
 642     sysbus_create_simple("pl050_mouse", 0x19000000, pic[4]);
 643     sysbus_create_simple(TYPE_INTEGRATOR_DEBUG, 0x1a000000, 0);
 644
 645     dev = sysbus_create_varargs("pl181", 0x1c000000, pic[23], pic[24], NULL);
 646     qdev_connect_gpio_out_named(dev, "card-read-only", 0,
 647                           qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_WPROT, 0));
 648     qdev_connect_gpio_out_named(dev, "card-inserted", 0,
 649                           qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_CARDIN, 0));
 650     dinfo = drive_get(IF_SD, 0, 0);
 651     if (dinfo) {
 652         DeviceState *card;
 653
 654         card = qdev_new(TYPE_SD_CARD);
 655         qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
 656                                 &error_fatal);
 657         qdev_realize_and_unref(card, qdev_get_child_bus(dev, "sd-bus"),
 658                                &error_fatal);
 659     }
 660
 661     dev = qdev_new("pl041");
 662     if (machine->audiodev) {
 663         qdev_prop_set_string(dev, "audiodev", machine->audiodev);
 664     }
 665     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 666     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x1d000000);
 667     sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[25]);
 668
 669     if (qemu_find_nic_info("smc91c111", true, NULL)) {
 670         smc91c111_init(0xc8000000, pic[27]);
 671     }
 672
 673     dev = qdev_new("pl110");
 674     object_property_set_link(OBJECT(dev), "framebuffer-memory",
 675                              OBJECT(address_space_mem), &error_fatal);
 676     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 677     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xc0000000);
 678     sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[22]);
 679
 680     integrator_binfo.ram_size = ram_size;
 681     arm_load_kernel(cpu, machine, &integrator_binfo);
 682 }
 683
 684 static void integratorcp_machine_init(MachineClass *mc)
 685 {
 686     mc->desc = "ARM Integrator/CP (ARM926EJ-S)";
 687     mc->init = integratorcp_init;
 688     mc->ignore_memory_transaction_failures = true;
 689     mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926");
 690     mc->default_ram_id = "integrator.ram";
 691
 692     machine_add_audiodev_property(mc);
 693 }
 694
 695 DEFINE_MACHINE("integratorcp", integratorcp_machine_init)
 696
 697 static Property core_properties[] = {
 698     DEFINE_PROP_UINT32("memsz", IntegratorCMState, memsz, 0),
 699     DEFINE_PROP_END_OF_LIST(),
 700 };
 701
 702 static void core_class_init(ObjectClass *klass, void *data)
 703 {
 704     DeviceClass *dc = DEVICE_CLASS(klass);
 705
 706     device_class_set_props(dc, core_properties);
 707     dc->realize = integratorcm_realize;
 708     dc->vmsd = &vmstate_integratorcm;
 709 }
 710
 711 static void icp_pic_class_init(ObjectClass *klass, void *data)
 712 {
 713     DeviceClass *dc = DEVICE_CLASS(klass);
 714
 715     dc->vmsd = &vmstate_icp_pic;
 716 }
 717
 718 static void icp_control_class_init(ObjectClass *klass, void *data)
 719 {
 720     DeviceClass *dc = DEVICE_CLASS(klass);
 721
 722     dc->vmsd = &vmstate_icp_control;
 723 }
 724
 725 static const TypeInfo core_info = {
 726     .name          = TYPE_INTEGRATOR_CM,
 727     .parent        = TYPE_SYS_BUS_DEVICE,
 728     .instance_size = sizeof(IntegratorCMState),
 729     .instance_init = integratorcm_init,
 730     .class_init    = core_class_init,
 731 };
 732
 733 static const TypeInfo icp_pic_info = {
 734     .name          = TYPE_INTEGRATOR_PIC,
 735     .parent        = TYPE_SYS_BUS_DEVICE,
 736     .instance_size = sizeof(icp_pic_state),
 737     .instance_init = icp_pic_init,
 738     .class_init    = icp_pic_class_init,
 739 };
 740
 741 static const TypeInfo icp_ctrl_regs_info = {
 742     .name          = TYPE_ICP_CONTROL_REGS,
 743     .parent        = TYPE_SYS_BUS_DEVICE,
 744     .instance_size = sizeof(ICPCtrlRegsState),
 745     .instance_init = icp_control_init,
 746     .class_init    = icp_control_class_init,
 747 };
 748
 749 static void integratorcp_register_types(void)
 750 {
 751     type_register_static(&icp_pic_info);
 752     type_register_static(&core_info);
 753     type_register_static(&icp_ctrl_regs_info);
 754 }
 755
 756 type_init(integratorcp_register_types)