4 * Copyright (c) 2005 Samuel Tardieu
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
23 #include "exec/exec-all.h"
26 #if !defined(CONFIG_USER_ONLY)
27 #include "hw/sh4/sh_intc.h"
28 #include "sysemu/runstate.h"
32 #define MMU_ITLB_MISS (-1)
33 #define MMU_ITLB_MULTIPLE (-2)
34 #define MMU_ITLB_VIOLATION (-3)
35 #define MMU_DTLB_MISS_READ (-4)
36 #define MMU_DTLB_MISS_WRITE (-5)
37 #define MMU_DTLB_INITIAL_WRITE (-6)
38 #define MMU_DTLB_VIOLATION_READ (-7)
39 #define MMU_DTLB_VIOLATION_WRITE (-8)
40 #define MMU_DTLB_MULTIPLE (-9)
41 #define MMU_DTLB_MISS (-10)
42 #define MMU_IADDR_ERROR (-11)
43 #define MMU_DADDR_ERROR_READ (-12)
44 #define MMU_DADDR_ERROR_WRITE (-13)
46 #if defined(CONFIG_USER_ONLY)
48 void superh_cpu_do_interrupt(CPUState
*cs
)
50 cs
->exception_index
= -1;
53 int cpu_sh4_is_cached(CPUSH4State
*env
, target_ulong addr
)
55 /* For user mode, only U0 area is cacheable. */
56 return !(addr
& 0x80000000);
59 #else /* !CONFIG_USER_ONLY */
61 void superh_cpu_do_interrupt(CPUState
*cs
)
63 SuperHCPU
*cpu
= SUPERH_CPU(cs
);
64 CPUSH4State
*env
= &cpu
->env
;
65 int do_irq
= cs
->interrupt_request
& CPU_INTERRUPT_HARD
;
66 int do_exp
, irq_vector
= cs
->exception_index
;
68 /* prioritize exceptions over interrupts */
70 do_exp
= cs
->exception_index
!= -1;
71 do_irq
= do_irq
&& (cs
->exception_index
== -1);
73 if (env
->sr
& (1u << SR_BL
)) {
74 if (do_exp
&& cs
->exception_index
!= 0x1e0) {
75 /* In theory a masked exception generates a reset exception,
76 which in turn jumps to the reset vector. However this only
77 works when using a bootloader. When using a kernel and an
78 initrd, they need to be reloaded and the program counter
79 should be loaded with the kernel entry point.
80 qemu_system_reset_request takes care of that. */
81 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
84 if (do_irq
&& !env
->in_sleep
) {
91 irq_vector
= sh_intc_get_pending_vector(env
->intc_handle
,
92 (env
->sr
>> 4) & 0xf);
93 if (irq_vector
== -1) {
98 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
100 switch (cs
->exception_index
) {
102 expname
= "addr_error";
105 expname
= "tlb_miss";
108 expname
= "tlb_violation";
111 expname
= "illegal_instruction";
114 expname
= "slot_illegal_instruction";
117 expname
= "fpu_disable";
120 expname
= "slot_fpu";
123 expname
= "data_write";
126 expname
= "dtlb_miss_write";
129 expname
= "dtlb_violation_write";
132 expname
= "fpu_exception";
135 expname
= "initial_page_write";
141 expname
= do_irq
? "interrupt" : "???";
144 qemu_log("exception 0x%03x [%s] raised\n",
145 irq_vector
, expname
);
146 log_cpu_state(cs
, 0);
149 env
->ssr
= cpu_read_sr(env
);
151 env
->sgr
= env
->gregs
[15];
152 env
->sr
|= (1u << SR_BL
) | (1u << SR_MD
) | (1u << SR_RB
);
155 if (env
->flags
& DELAY_SLOT_MASK
) {
156 /* Branch instruction should be executed again before delay slot. */
158 /* Clear flags for exception/interrupt routine. */
159 env
->flags
&= ~DELAY_SLOT_MASK
;
163 env
->expevt
= cs
->exception_index
;
164 switch (cs
->exception_index
) {
168 env
->sr
&= ~(1u << SR_FD
);
169 env
->sr
|= 0xf << 4; /* IMASK */
170 env
->pc
= 0xa0000000;
174 env
->pc
= env
->vbr
+ 0x400;
177 env
->spc
+= 2; /* special case for TRAPA */
180 env
->pc
= env
->vbr
+ 0x100;
187 env
->intevt
= irq_vector
;
188 env
->pc
= env
->vbr
+ 0x600;
193 static void update_itlb_use(CPUSH4State
* env
, int itlbnb
)
195 uint8_t or_mask
= 0, and_mask
= (uint8_t) - 1;
214 env
->mmucr
&= (and_mask
<< 24) | 0x00ffffff;
215 env
->mmucr
|= (or_mask
<< 24);
218 static int itlb_replacement(CPUSH4State
* env
)
220 if ((env
->mmucr
& 0xe0000000) == 0xe0000000) {
223 if ((env
->mmucr
& 0x98000000) == 0x18000000) {
226 if ((env
->mmucr
& 0x54000000) == 0x04000000) {
229 if ((env
->mmucr
& 0x2c000000) == 0x00000000) {
232 cpu_abort(env_cpu(env
), "Unhandled itlb_replacement");
235 /* Find the corresponding entry in the right TLB
236 Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
238 static int find_tlb_entry(CPUSH4State
* env
, target_ulong address
,
239 tlb_t
* entries
, uint8_t nbtlb
, int use_asid
)
241 int match
= MMU_DTLB_MISS
;
246 asid
= env
->pteh
& 0xff;
248 for (i
= 0; i
< nbtlb
; i
++) {
250 continue; /* Invalid entry */
251 if (!entries
[i
].sh
&& use_asid
&& entries
[i
].asid
!= asid
)
252 continue; /* Bad ASID */
253 start
= (entries
[i
].vpn
<< 10) & ~(entries
[i
].size
- 1);
254 end
= start
+ entries
[i
].size
- 1;
255 if (address
>= start
&& address
<= end
) { /* Match */
256 if (match
!= MMU_DTLB_MISS
)
257 return MMU_DTLB_MULTIPLE
; /* Multiple match */
264 static void increment_urc(CPUSH4State
* env
)
269 urb
= ((env
->mmucr
) >> 18) & 0x3f;
270 urc
= ((env
->mmucr
) >> 10) & 0x3f;
272 if ((urb
> 0 && urc
> urb
) || urc
> (UTLB_SIZE
- 1))
274 env
->mmucr
= (env
->mmucr
& 0xffff03ff) | (urc
<< 10);
277 /* Copy and utlb entry into itlb
280 static int copy_utlb_entry_itlb(CPUSH4State
*env
, int utlb
)
285 itlb
= itlb_replacement(env
);
286 ientry
= &env
->itlb
[itlb
];
288 tlb_flush_page(env_cpu(env
), ientry
->vpn
<< 10);
290 *ientry
= env
->utlb
[utlb
];
291 update_itlb_use(env
, itlb
);
296 Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
298 static int find_itlb_entry(CPUSH4State
* env
, target_ulong address
,
303 e
= find_tlb_entry(env
, address
, env
->itlb
, ITLB_SIZE
, use_asid
);
304 if (e
== MMU_DTLB_MULTIPLE
) {
305 e
= MMU_ITLB_MULTIPLE
;
306 } else if (e
== MMU_DTLB_MISS
) {
309 update_itlb_use(env
, e
);
315 Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
316 static int find_utlb_entry(CPUSH4State
* env
, target_ulong address
, int use_asid
)
318 /* per utlb access */
322 return find_tlb_entry(env
, address
, env
->utlb
, UTLB_SIZE
, use_asid
);
325 /* Match address against MMU
326 Return MMU_OK, MMU_DTLB_MISS_READ, MMU_DTLB_MISS_WRITE,
327 MMU_DTLB_INITIAL_WRITE, MMU_DTLB_VIOLATION_READ,
328 MMU_DTLB_VIOLATION_WRITE, MMU_ITLB_MISS,
329 MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION,
330 MMU_IADDR_ERROR, MMU_DADDR_ERROR_READ, MMU_DADDR_ERROR_WRITE.
332 static int get_mmu_address(CPUSH4State
* env
, target_ulong
* physical
,
333 int *prot
, target_ulong address
,
334 MMUAccessType access_type
)
337 tlb_t
*matching
= NULL
;
339 use_asid
= !(env
->mmucr
& MMUCR_SV
) || !(env
->sr
& (1u << SR_MD
));
341 if (access_type
== MMU_INST_FETCH
) {
342 n
= find_itlb_entry(env
, address
, use_asid
);
344 matching
= &env
->itlb
[n
];
345 if (!(env
->sr
& (1u << SR_MD
)) && !(matching
->pr
& 2)) {
346 n
= MMU_ITLB_VIOLATION
;
351 n
= find_utlb_entry(env
, address
, use_asid
);
353 n
= copy_utlb_entry_itlb(env
, n
);
354 matching
= &env
->itlb
[n
];
355 if (!(env
->sr
& (1u << SR_MD
)) && !(matching
->pr
& 2)) {
356 n
= MMU_ITLB_VIOLATION
;
358 *prot
= PAGE_READ
| PAGE_EXEC
;
359 if ((matching
->pr
& 1) && matching
->d
) {
363 } else if (n
== MMU_DTLB_MULTIPLE
) {
364 n
= MMU_ITLB_MULTIPLE
;
365 } else if (n
== MMU_DTLB_MISS
) {
370 n
= find_utlb_entry(env
, address
, use_asid
);
372 matching
= &env
->utlb
[n
];
373 if (!(env
->sr
& (1u << SR_MD
)) && !(matching
->pr
& 2)) {
374 n
= (access_type
== MMU_DATA_STORE
)
375 ? MMU_DTLB_VIOLATION_WRITE
: MMU_DTLB_VIOLATION_READ
;
376 } else if ((access_type
== MMU_DATA_STORE
) && !(matching
->pr
& 1)) {
377 n
= MMU_DTLB_VIOLATION_WRITE
;
378 } else if ((access_type
== MMU_DATA_STORE
) && !matching
->d
) {
379 n
= MMU_DTLB_INITIAL_WRITE
;
382 if ((matching
->pr
& 1) && matching
->d
) {
386 } else if (n
== MMU_DTLB_MISS
) {
387 n
= (access_type
== MMU_DATA_STORE
)
388 ? MMU_DTLB_MISS_WRITE
: MMU_DTLB_MISS_READ
;
393 *physical
= ((matching
->ppn
<< 10) & ~(matching
->size
- 1))
394 | (address
& (matching
->size
- 1));
399 static int get_physical_address(CPUSH4State
* env
, target_ulong
* physical
,
400 int *prot
, target_ulong address
,
401 MMUAccessType access_type
)
403 /* P1, P2 and P4 areas do not use translation */
404 if ((address
>= 0x80000000 && address
< 0xc0000000) || address
>= 0xe0000000) {
405 if (!(env
->sr
& (1u << SR_MD
))
406 && (address
< 0xe0000000 || address
>= 0xe4000000)) {
407 /* Unauthorized access in user mode (only store queues are available) */
408 qemu_log_mask(LOG_GUEST_ERROR
, "Unauthorized access\n");
409 if (access_type
== MMU_DATA_LOAD
) {
410 return MMU_DADDR_ERROR_READ
;
411 } else if (access_type
== MMU_DATA_STORE
) {
412 return MMU_DADDR_ERROR_WRITE
;
414 return MMU_IADDR_ERROR
;
417 if (address
>= 0x80000000 && address
< 0xc0000000) {
418 /* Mask upper 3 bits for P1 and P2 areas */
419 *physical
= address
& 0x1fffffff;
423 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
427 /* If MMU is disabled, return the corresponding physical page */
428 if (!(env
->mmucr
& MMUCR_AT
)) {
429 *physical
= address
& 0x1FFFFFFF;
430 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
434 /* We need to resort to the MMU */
435 return get_mmu_address(env
, physical
, prot
, address
, access_type
);
438 hwaddr
superh_cpu_get_phys_page_debug(CPUState
*cs
, vaddr addr
)
440 SuperHCPU
*cpu
= SUPERH_CPU(cs
);
441 target_ulong physical
;
444 if (get_physical_address(&cpu
->env
, &physical
, &prot
, addr
, MMU_DATA_LOAD
)
452 void cpu_load_tlb(CPUSH4State
* env
)
454 CPUState
*cs
= env_cpu(env
);
455 int n
= cpu_mmucr_urc(env
->mmucr
);
456 tlb_t
* entry
= &env
->utlb
[n
];
459 /* Overwriting valid entry in utlb. */
460 target_ulong address
= entry
->vpn
<< 10;
461 tlb_flush_page(cs
, address
);
464 /* Take values into cpu status from registers. */
465 entry
->asid
= (uint8_t)cpu_pteh_asid(env
->pteh
);
466 entry
->vpn
= cpu_pteh_vpn(env
->pteh
);
467 entry
->v
= (uint8_t)cpu_ptel_v(env
->ptel
);
468 entry
->ppn
= cpu_ptel_ppn(env
->ptel
);
469 entry
->sz
= (uint8_t)cpu_ptel_sz(env
->ptel
);
472 entry
->size
= 1024; /* 1K */
475 entry
->size
= 1024 * 4; /* 4K */
478 entry
->size
= 1024 * 64; /* 64K */
481 entry
->size
= 1024 * 1024; /* 1M */
484 cpu_abort(cs
, "Unhandled load_tlb");
487 entry
->sh
= (uint8_t)cpu_ptel_sh(env
->ptel
);
488 entry
->c
= (uint8_t)cpu_ptel_c(env
->ptel
);
489 entry
->pr
= (uint8_t)cpu_ptel_pr(env
->ptel
);
490 entry
->d
= (uint8_t)cpu_ptel_d(env
->ptel
);
491 entry
->wt
= (uint8_t)cpu_ptel_wt(env
->ptel
);
492 entry
->sa
= (uint8_t)cpu_ptea_sa(env
->ptea
);
493 entry
->tc
= (uint8_t)cpu_ptea_tc(env
->ptea
);
496 void cpu_sh4_invalidate_tlb(CPUSH4State
*s
)
501 for (i
= 0; i
< UTLB_SIZE
; i
++) {
502 tlb_t
* entry
= &s
->utlb
[i
];
506 for (i
= 0; i
< ITLB_SIZE
; i
++) {
507 tlb_t
* entry
= &s
->itlb
[i
];
511 tlb_flush(env_cpu(s
));
514 uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State
*s
,
517 int index
= (addr
& 0x00000300) >> 8;
518 tlb_t
* entry
= &s
->itlb
[index
];
520 return (entry
->vpn
<< 10) |
525 void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State
*s
, hwaddr addr
,
528 uint32_t vpn
= (mem_value
& 0xfffffc00) >> 10;
529 uint8_t v
= (uint8_t)((mem_value
& 0x00000100) >> 8);
530 uint8_t asid
= (uint8_t)(mem_value
& 0x000000ff);
532 int index
= (addr
& 0x00000300) >> 8;
533 tlb_t
* entry
= &s
->itlb
[index
];
535 /* Overwriting valid entry in itlb. */
536 target_ulong address
= entry
->vpn
<< 10;
537 tlb_flush_page(env_cpu(s
), address
);
544 uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State
*s
,
547 int array
= (addr
& 0x00800000) >> 23;
548 int index
= (addr
& 0x00000300) >> 8;
549 tlb_t
* entry
= &s
->itlb
[index
];
552 /* ITLB Data Array 1 */
553 return (entry
->ppn
<< 10) |
556 ((entry
->sz
& 1) << 6) |
557 ((entry
->sz
& 2) << 4) |
561 /* ITLB Data Array 2 */
562 return (entry
->tc
<< 1) |
567 void cpu_sh4_write_mmaped_itlb_data(CPUSH4State
*s
, hwaddr addr
,
570 int array
= (addr
& 0x00800000) >> 23;
571 int index
= (addr
& 0x00000300) >> 8;
572 tlb_t
* entry
= &s
->itlb
[index
];
575 /* ITLB Data Array 1 */
577 /* Overwriting valid entry in utlb. */
578 target_ulong address
= entry
->vpn
<< 10;
579 tlb_flush_page(env_cpu(s
), address
);
581 entry
->ppn
= (mem_value
& 0x1ffffc00) >> 10;
582 entry
->v
= (mem_value
& 0x00000100) >> 8;
583 entry
->sz
= (mem_value
& 0x00000080) >> 6 |
584 (mem_value
& 0x00000010) >> 4;
585 entry
->pr
= (mem_value
& 0x00000040) >> 5;
586 entry
->c
= (mem_value
& 0x00000008) >> 3;
587 entry
->sh
= (mem_value
& 0x00000002) >> 1;
589 /* ITLB Data Array 2 */
590 entry
->tc
= (mem_value
& 0x00000008) >> 3;
591 entry
->sa
= (mem_value
& 0x00000007);
595 uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State
*s
,
598 int index
= (addr
& 0x00003f00) >> 8;
599 tlb_t
* entry
= &s
->utlb
[index
];
601 increment_urc(s
); /* per utlb access */
603 return (entry
->vpn
<< 10) |
608 void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State
*s
, hwaddr addr
,
611 int associate
= addr
& 0x0000080;
612 uint32_t vpn
= (mem_value
& 0xfffffc00) >> 10;
613 uint8_t d
= (uint8_t)((mem_value
& 0x00000200) >> 9);
614 uint8_t v
= (uint8_t)((mem_value
& 0x00000100) >> 8);
615 uint8_t asid
= (uint8_t)(mem_value
& 0x000000ff);
616 int use_asid
= !(s
->mmucr
& MMUCR_SV
) || !(s
->sr
& (1u << SR_MD
));
620 tlb_t
* utlb_match_entry
= NULL
;
621 int needs_tlb_flush
= 0;
624 for (i
= 0; i
< UTLB_SIZE
; i
++) {
625 tlb_t
* entry
= &s
->utlb
[i
];
629 if (entry
->vpn
== vpn
630 && (!use_asid
|| entry
->asid
== asid
|| entry
->sh
)) {
631 if (utlb_match_entry
) {
632 CPUState
*cs
= env_cpu(s
);
634 /* Multiple TLB Exception */
635 cs
->exception_index
= 0x140;
643 utlb_match_entry
= entry
;
645 increment_urc(s
); /* per utlb access */
649 for (i
= 0; i
< ITLB_SIZE
; i
++) {
650 tlb_t
* entry
= &s
->itlb
[i
];
651 if (entry
->vpn
== vpn
652 && (!use_asid
|| entry
->asid
== asid
|| entry
->sh
)) {
655 if (utlb_match_entry
)
656 *entry
= *utlb_match_entry
;
663 if (needs_tlb_flush
) {
664 tlb_flush_page(env_cpu(s
), vpn
<< 10);
667 int index
= (addr
& 0x00003f00) >> 8;
668 tlb_t
* entry
= &s
->utlb
[index
];
670 CPUState
*cs
= env_cpu(s
);
672 /* Overwriting valid entry in utlb. */
673 target_ulong address
= entry
->vpn
<< 10;
674 tlb_flush_page(cs
, address
);
684 uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State
*s
,
687 int array
= (addr
& 0x00800000) >> 23;
688 int index
= (addr
& 0x00003f00) >> 8;
689 tlb_t
* entry
= &s
->utlb
[index
];
691 increment_urc(s
); /* per utlb access */
694 /* ITLB Data Array 1 */
695 return (entry
->ppn
<< 10) |
698 ((entry
->sz
& 1) << 6) |
699 ((entry
->sz
& 2) << 4) |
705 /* ITLB Data Array 2 */
706 return (entry
->tc
<< 1) |
711 void cpu_sh4_write_mmaped_utlb_data(CPUSH4State
*s
, hwaddr addr
,
714 int array
= (addr
& 0x00800000) >> 23;
715 int index
= (addr
& 0x00003f00) >> 8;
716 tlb_t
* entry
= &s
->utlb
[index
];
718 increment_urc(s
); /* per utlb access */
721 /* UTLB Data Array 1 */
723 /* Overwriting valid entry in utlb. */
724 target_ulong address
= entry
->vpn
<< 10;
725 tlb_flush_page(env_cpu(s
), address
);
727 entry
->ppn
= (mem_value
& 0x1ffffc00) >> 10;
728 entry
->v
= (mem_value
& 0x00000100) >> 8;
729 entry
->sz
= (mem_value
& 0x00000080) >> 6 |
730 (mem_value
& 0x00000010) >> 4;
731 entry
->pr
= (mem_value
& 0x00000060) >> 5;
732 entry
->c
= (mem_value
& 0x00000008) >> 3;
733 entry
->d
= (mem_value
& 0x00000004) >> 2;
734 entry
->sh
= (mem_value
& 0x00000002) >> 1;
735 entry
->wt
= (mem_value
& 0x00000001);
737 /* UTLB Data Array 2 */
738 entry
->tc
= (mem_value
& 0x00000008) >> 3;
739 entry
->sa
= (mem_value
& 0x00000007);
743 int cpu_sh4_is_cached(CPUSH4State
* env
, target_ulong addr
)
746 int use_asid
= !(env
->mmucr
& MMUCR_SV
) || !(env
->sr
& (1u << SR_MD
));
749 if (env
->sr
& (1u << SR_MD
)) {
750 /* For privileged mode, P2 and P4 area is not cacheable. */
751 if ((0xA0000000 <= addr
&& addr
< 0xC0000000) || 0xE0000000 <= addr
)
754 /* For user mode, only U0 area is cacheable. */
755 if (0x80000000 <= addr
)
760 * TODO : Evaluate CCR and check if the cache is on or off.
761 * Now CCR is not in CPUSH4State, but in SH7750State.
762 * When you move the ccr into CPUSH4State, the code will be
766 /* check if operand cache is enabled or not. */
771 /* if MMU is off, no check for TLB. */
772 if (env
->mmucr
& MMUCR_AT
)
776 n
= find_tlb_entry(env
, addr
, env
->itlb
, ITLB_SIZE
, use_asid
);
778 return env
->itlb
[n
].c
;
780 n
= find_tlb_entry(env
, addr
, env
->utlb
, UTLB_SIZE
, use_asid
);
782 return env
->utlb
[n
].c
;
789 bool superh_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
791 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
792 SuperHCPU
*cpu
= SUPERH_CPU(cs
);
793 CPUSH4State
*env
= &cpu
->env
;
795 /* Delay slots are indivisible, ignore interrupts */
796 if (env
->flags
& DELAY_SLOT_MASK
) {
799 superh_cpu_do_interrupt(cs
);
806 bool superh_cpu_tlb_fill(CPUState
*cs
, vaddr address
, int size
,
807 MMUAccessType access_type
, int mmu_idx
,
808 bool probe
, uintptr_t retaddr
)
810 SuperHCPU
*cpu
= SUPERH_CPU(cs
);
811 CPUSH4State
*env
= &cpu
->env
;
814 #ifdef CONFIG_USER_ONLY
815 ret
= (access_type
== MMU_DATA_STORE
? MMU_DTLB_VIOLATION_WRITE
:
816 access_type
== MMU_INST_FETCH
? MMU_ITLB_VIOLATION
:
817 MMU_DTLB_VIOLATION_READ
);
819 target_ulong physical
;
822 ret
= get_physical_address(env
, &physical
, &prot
, address
, access_type
);
825 address
&= TARGET_PAGE_MASK
;
826 physical
&= TARGET_PAGE_MASK
;
827 tlb_set_page(cs
, address
, physical
, prot
, mmu_idx
, TARGET_PAGE_SIZE
);
834 if (ret
!= MMU_DTLB_MULTIPLE
&& ret
!= MMU_ITLB_MULTIPLE
) {
835 env
->pteh
= (env
->pteh
& PTEH_ASID_MASK
) | (address
& PTEH_VPN_MASK
);
842 case MMU_DTLB_MISS_READ
:
843 cs
->exception_index
= 0x040;
845 case MMU_DTLB_MULTIPLE
:
846 case MMU_ITLB_MULTIPLE
:
847 cs
->exception_index
= 0x140;
849 case MMU_ITLB_VIOLATION
:
850 cs
->exception_index
= 0x0a0;
852 case MMU_DTLB_MISS_WRITE
:
853 cs
->exception_index
= 0x060;
855 case MMU_DTLB_INITIAL_WRITE
:
856 cs
->exception_index
= 0x080;
858 case MMU_DTLB_VIOLATION_READ
:
859 cs
->exception_index
= 0x0a0;
861 case MMU_DTLB_VIOLATION_WRITE
:
862 cs
->exception_index
= 0x0c0;
864 case MMU_IADDR_ERROR
:
865 case MMU_DADDR_ERROR_READ
:
866 cs
->exception_index
= 0x0e0;
868 case MMU_DADDR_ERROR_WRITE
:
869 cs
->exception_index
= 0x100;
872 cpu_abort(cs
, "Unhandled MMU fault");
874 cpu_loop_exit_restore(cs
, retaddr
);