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m25p80: Add Micron n25q032a
[qemu/ar7.git] / hw / block / m25p80.c
bloba927a6bc21dc6afcd3398b373cd0a252a4fbb80c
1 /*
2 * ST M25P80 emulator. Emulate all SPI flash devices based on the m25p80 command
3 * set. Known devices table current as of Jun/2012 and taken from linux.
4 * See drivers/mtd/devices/m25p80.c.
5 *
6 * Copyright (C) 2011 Edgar E. Iglesias <edgar.iglesias@gmail.com>
7 * Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
8 * Copyright (C) 2012 PetaLogix
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 or
13 * (at your option) a later version of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, see <http://www.gnu.org/licenses/>.
22 */
23
24 #include "hw/hw.h"
25 #include "sysemu/blockdev.h"
26 #include "hw/ssi.h"
27
28 #ifndef M25P80_ERR_DEBUG
29 #define M25P80_ERR_DEBUG 0
30 #endif
31
32 #define DB_PRINT_L(level, ...) do { \
33 if (M25P80_ERR_DEBUG > (level)) { \
34 fprintf(stderr, ": %s: ", __func__); \
35 fprintf(stderr, ## __VA_ARGS__); \
36 } \
37 } while (0);
38
39 /* Fields for FlashPartInfo->flags */
40
41 /* erase capabilities */
42 #define ER_4K 1
43 #define ER_32K 2
44 /* set to allow the page program command to write 0s back to 1. Useful for
45 * modelling EEPROM with SPI flash command set
46 */
47 #define WR_1 0x100
48
49 typedef struct FlashPartInfo {
50 const char *part_name;
51 /* jedec code. (jedec >> 16) & 0xff is the 1st byte, >> 8 the 2nd etc */
52 uint32_t jedec;
53 /* extended jedec code */
54 uint16_t ext_jedec;
55 /* there is confusion between manufacturers as to what a sector is. In this
56 * device model, a "sector" is the size that is erased by the ERASE_SECTOR
57 * command (opcode 0xd8).
58 */
59 uint32_t sector_size;
60 uint32_t n_sectors;
61 uint32_t page_size;
62 uint8_t flags;
63 } FlashPartInfo;
64
65 /* adapted from linux */
66
67 #define INFO(_part_name, _jedec, _ext_jedec, _sector_size, _n_sectors, _flags)\
68 .part_name = (_part_name),\
69 .jedec = (_jedec),\
70 .ext_jedec = (_ext_jedec),\
71 .sector_size = (_sector_size),\
72 .n_sectors = (_n_sectors),\
73 .page_size = 256,\
74 .flags = (_flags),\
75
76 #define JEDEC_NUMONYX 0x20
77 #define JEDEC_WINBOND 0xEF
78 #define JEDEC_SPANSION 0x01
79
80 static const FlashPartInfo known_devices[] = {
81 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
82 { INFO("at25fs010", 0x1f6601, 0, 32 << 10, 4, ER_4K) },
83 { INFO("at25fs040", 0x1f6604, 0, 64 << 10, 8, ER_4K) },
84
85 { INFO("at25df041a", 0x1f4401, 0, 64 << 10, 8, ER_4K) },
86 { INFO("at25df321a", 0x1f4701, 0, 64 << 10, 64, ER_4K) },
87 { INFO("at25df641", 0x1f4800, 0, 64 << 10, 128, ER_4K) },
88
89 { INFO("at26f004", 0x1f0400, 0, 64 << 10, 8, ER_4K) },
90 { INFO("at26df081a", 0x1f4501, 0, 64 << 10, 16, ER_4K) },
91 { INFO("at26df161a", 0x1f4601, 0, 64 << 10, 32, ER_4K) },
92 { INFO("at26df321", 0x1f4700, 0, 64 << 10, 64, ER_4K) },
93
94 { INFO("at45db081d", 0x1f2500, 0, 64 << 10, 16, ER_4K) },
95
96 /* EON -- en25xxx */
97 { INFO("en25f32", 0x1c3116, 0, 64 << 10, 64, ER_4K) },
98 { INFO("en25p32", 0x1c2016, 0, 64 << 10, 64, 0) },
99 { INFO("en25q32b", 0x1c3016, 0, 64 << 10, 64, 0) },
100 { INFO("en25p64", 0x1c2017, 0, 64 << 10, 128, 0) },
101 { INFO("en25q64", 0x1c3017, 0, 64 << 10, 128, ER_4K) },
102
103 /* GigaDevice */
104 { INFO("gd25q32", 0xc84016, 0, 64 << 10, 64, ER_4K) },
105 { INFO("gd25q64", 0xc84017, 0, 64 << 10, 128, ER_4K) },
106
107 /* Intel/Numonyx -- xxxs33b */
108 { INFO("160s33b", 0x898911, 0, 64 << 10, 32, 0) },
109 { INFO("320s33b", 0x898912, 0, 64 << 10, 64, 0) },
110 { INFO("640s33b", 0x898913, 0, 64 << 10, 128, 0) },
111 { INFO("n25q064", 0x20ba17, 0, 64 << 10, 128, 0) },
112
113 /* Macronix */
114 { INFO("mx25l2005a", 0xc22012, 0, 64 << 10, 4, ER_4K) },
115 { INFO("mx25l4005a", 0xc22013, 0, 64 << 10, 8, ER_4K) },
116 { INFO("mx25l8005", 0xc22014, 0, 64 << 10, 16, 0) },
117 { INFO("mx25l1606e", 0xc22015, 0, 64 << 10, 32, ER_4K) },
118 { INFO("mx25l3205d", 0xc22016, 0, 64 << 10, 64, 0) },
119 { INFO("mx25l6405d", 0xc22017, 0, 64 << 10, 128, 0) },
120 { INFO("mx25l12805d", 0xc22018, 0, 64 << 10, 256, 0) },
121 { INFO("mx25l12855e", 0xc22618, 0, 64 << 10, 256, 0) },
122 { INFO("mx25l25635e", 0xc22019, 0, 64 << 10, 512, 0) },
123 { INFO("mx25l25655e", 0xc22619, 0, 64 << 10, 512, 0) },
124
125 /* Micron */
126 { INFO("n25q032a", 0x20bb16, 0, 64 << 10, 64, ER_4K) },
127 { INFO("n25q128a11", 0x20bb18, 0, 64 << 10, 256, 0) },
128 { INFO("n25q128a13", 0x20ba18, 0, 64 << 10, 256, 0) },
129 { INFO("n25q256a", 0x20ba19, 0, 64 << 10, 512, ER_4K) },
130
131 /* Spansion -- single (large) sector size only, at least
132 * for the chips listed here (without boot sectors).
133 */
134 { INFO("s25sl032p", 0x010215, 0x4d00, 64 << 10, 64, ER_4K) },
135 { INFO("s25sl064p", 0x010216, 0x4d00, 64 << 10, 128, ER_4K) },
136 { INFO("s25fl256s0", 0x010219, 0x4d00, 256 << 10, 128, 0) },
137 { INFO("s25fl256s1", 0x010219, 0x4d01, 64 << 10, 512, 0) },
138 { INFO("s25fl512s", 0x010220, 0x4d00, 256 << 10, 256, 0) },
139 { INFO("s70fl01gs", 0x010221, 0x4d00, 256 << 10, 256, 0) },
140 { INFO("s25sl12800", 0x012018, 0x0300, 256 << 10, 64, 0) },
141 { INFO("s25sl12801", 0x012018, 0x0301, 64 << 10, 256, 0) },
142 { INFO("s25fl129p0", 0x012018, 0x4d00, 256 << 10, 64, 0) },
143 { INFO("s25fl129p1", 0x012018, 0x4d01, 64 << 10, 256, 0) },
144 { INFO("s25sl004a", 0x010212, 0, 64 << 10, 8, 0) },
145 { INFO("s25sl008a", 0x010213, 0, 64 << 10, 16, 0) },
146 { INFO("s25sl016a", 0x010214, 0, 64 << 10, 32, 0) },
147 { INFO("s25sl032a", 0x010215, 0, 64 << 10, 64, 0) },
148 { INFO("s25sl064a", 0x010216, 0, 64 << 10, 128, 0) },
149 { INFO("s25fl016k", 0xef4015, 0, 64 << 10, 32, ER_4K | ER_32K) },
150 { INFO("s25fl064k", 0xef4017, 0, 64 << 10, 128, ER_4K | ER_32K) },
151
152 /* SST -- large erase sizes are "overlays", "sectors" are 4<< 10 */
153 { INFO("sst25vf040b", 0xbf258d, 0, 64 << 10, 8, ER_4K) },
154 { INFO("sst25vf080b", 0xbf258e, 0, 64 << 10, 16, ER_4K) },
155 { INFO("sst25vf016b", 0xbf2541, 0, 64 << 10, 32, ER_4K) },
156 { INFO("sst25vf032b", 0xbf254a, 0, 64 << 10, 64, ER_4K) },
157 { INFO("sst25wf512", 0xbf2501, 0, 64 << 10, 1, ER_4K) },
158 { INFO("sst25wf010", 0xbf2502, 0, 64 << 10, 2, ER_4K) },
159 { INFO("sst25wf020", 0xbf2503, 0, 64 << 10, 4, ER_4K) },
160 { INFO("sst25wf040", 0xbf2504, 0, 64 << 10, 8, ER_4K) },
161
162 /* ST Microelectronics -- newer production may have feature updates */
163 { INFO("m25p05", 0x202010, 0, 32 << 10, 2, 0) },
164 { INFO("m25p10", 0x202011, 0, 32 << 10, 4, 0) },
165 { INFO("m25p20", 0x202012, 0, 64 << 10, 4, 0) },
166 { INFO("m25p40", 0x202013, 0, 64 << 10, 8, 0) },
167 { INFO("m25p80", 0x202014, 0, 64 << 10, 16, 0) },
168 { INFO("m25p16", 0x202015, 0, 64 << 10, 32, 0) },
169 { INFO("m25p32", 0x202016, 0, 64 << 10, 64, 0) },
170 { INFO("m25p64", 0x202017, 0, 64 << 10, 128, 0) },
171 { INFO("m25p128", 0x202018, 0, 256 << 10, 64, 0) },
172 { INFO("n25q032", 0x20ba16, 0, 64 << 10, 64, 0) },
173
174 { INFO("m45pe10", 0x204011, 0, 64 << 10, 2, 0) },
175 { INFO("m45pe80", 0x204014, 0, 64 << 10, 16, 0) },
176 { INFO("m45pe16", 0x204015, 0, 64 << 10, 32, 0) },
177
178 { INFO("m25pe20", 0x208012, 0, 64 << 10, 4, 0) },
179 { INFO("m25pe80", 0x208014, 0, 64 << 10, 16, 0) },
180 { INFO("m25pe16", 0x208015, 0, 64 << 10, 32, ER_4K) },
181
182 { INFO("m25px32", 0x207116, 0, 64 << 10, 64, ER_4K) },
183 { INFO("m25px32-s0", 0x207316, 0, 64 << 10, 64, ER_4K) },
184 { INFO("m25px32-s1", 0x206316, 0, 64 << 10, 64, ER_4K) },
185 { INFO("m25px64", 0x207117, 0, 64 << 10, 128, 0) },
186
187 /* Winbond -- w25x "blocks" are 64k, "sectors" are 4KiB */
188 { INFO("w25x10", 0xef3011, 0, 64 << 10, 2, ER_4K) },
189 { INFO("w25x20", 0xef3012, 0, 64 << 10, 4, ER_4K) },
190 { INFO("w25x40", 0xef3013, 0, 64 << 10, 8, ER_4K) },
191 { INFO("w25x80", 0xef3014, 0, 64 << 10, 16, ER_4K) },
192 { INFO("w25x16", 0xef3015, 0, 64 << 10, 32, ER_4K) },
193 { INFO("w25x32", 0xef3016, 0, 64 << 10, 64, ER_4K) },
194 { INFO("w25q32", 0xef4016, 0, 64 << 10, 64, ER_4K) },
195 { INFO("w25q32dw", 0xef6016, 0, 64 << 10, 64, ER_4K) },
196 { INFO("w25x64", 0xef3017, 0, 64 << 10, 128, ER_4K) },
197 { INFO("w25q64", 0xef4017, 0, 64 << 10, 128, ER_4K) },
198 { INFO("w25q80", 0xef5014, 0, 64 << 10, 16, ER_4K) },
199 { INFO("w25q80bl", 0xef4014, 0, 64 << 10, 16, ER_4K) },
200 { INFO("w25q256", 0xef4019, 0, 64 << 10, 512, ER_4K) },
201
202 /* Numonyx -- n25q128 */
203 { INFO("n25q128", 0x20ba18, 0, 64 << 10, 256, 0) },
204 };
205
206 typedef enum {
207 NOP = 0,
208 WRSR = 0x1,
209 WRDI = 0x4,
210 RDSR = 0x5,
211 WREN = 0x6,
212 JEDEC_READ = 0x9f,
213 BULK_ERASE = 0xc7,
214
215 READ = 0x3,
216 FAST_READ = 0xb,
217 DOR = 0x3b,
218 QOR = 0x6b,
219 DIOR = 0xbb,
220 QIOR = 0xeb,
221
222 PP = 0x2,
223 DPP = 0xa2,
224 QPP = 0x32,
225
226 ERASE_4K = 0x20,
227 ERASE_32K = 0x52,
228 ERASE_SECTOR = 0xd8,
229 } FlashCMD;
230
231 typedef enum {
232 STATE_IDLE,
233 STATE_PAGE_PROGRAM,
234 STATE_READ,
235 STATE_COLLECTING_DATA,
236 STATE_READING_DATA,
237 } CMDState;
238
239 typedef struct Flash {
240 SSISlave ssidev;
241 uint32_t r;
242
243 BlockDriverState *bdrv;
244
245 uint8_t *storage;
246 uint32_t size;
247 int page_size;
248
249 uint8_t state;
250 uint8_t data[16];
251 uint32_t len;
252 uint32_t pos;
253 uint8_t needed_bytes;
254 uint8_t cmd_in_progress;
255 uint64_t cur_addr;
256 bool write_enable;
257
258 int64_t dirty_page;
259
260 const FlashPartInfo *pi;
261
262 } Flash;
263
264 typedef struct M25P80Class {
265 SSISlaveClass parent_class;
266 FlashPartInfo *pi;
267 } M25P80Class;
268
269 #define TYPE_M25P80 "m25p80-generic"
270 #define M25P80(obj) \
271 OBJECT_CHECK(Flash, (obj), TYPE_M25P80)
272 #define M25P80_CLASS(klass) \
273 OBJECT_CLASS_CHECK(M25P80Class, (klass), TYPE_M25P80)
274 #define M25P80_GET_CLASS(obj) \
275 OBJECT_GET_CLASS(M25P80Class, (obj), TYPE_M25P80)
276
277 static void bdrv_sync_complete(void *opaque, int ret)
278 {
279 /* do nothing. Masters do not directly interact with the backing store,
280 * only the working copy so no mutexing required.
281 */
282 }
283
284 static void flash_sync_page(Flash *s, int page)
285 {
286 if (s->bdrv) {
287 int bdrv_sector, nb_sectors;
288 QEMUIOVector iov;
289
290 bdrv_sector = (page * s->pi->page_size) / BDRV_SECTOR_SIZE;
291 nb_sectors = DIV_ROUND_UP(s->pi->page_size, BDRV_SECTOR_SIZE);
292 qemu_iovec_init(&iov, 1);
293 qemu_iovec_add(&iov, s->storage + bdrv_sector * BDRV_SECTOR_SIZE,
294 nb_sectors * BDRV_SECTOR_SIZE);
295 bdrv_aio_writev(s->bdrv, bdrv_sector, &iov, nb_sectors,
296 bdrv_sync_complete, NULL);
297 }
298 }
299
300 static inline void flash_sync_area(Flash *s, int64_t off, int64_t len)
301 {
302 int64_t start, end, nb_sectors;
303 QEMUIOVector iov;
304
305 if (!s->bdrv) {
306 return;
307 }
308
309 assert(!(len % BDRV_SECTOR_SIZE));
310 start = off / BDRV_SECTOR_SIZE;
311 end = (off + len) / BDRV_SECTOR_SIZE;
312 nb_sectors = end - start;
313 qemu_iovec_init(&iov, 1);
314 qemu_iovec_add(&iov, s->storage + (start * BDRV_SECTOR_SIZE),
315 nb_sectors * BDRV_SECTOR_SIZE);
316 bdrv_aio_writev(s->bdrv, start, &iov, nb_sectors, bdrv_sync_complete, NULL);
317 }
318
319 static void flash_erase(Flash *s, int offset, FlashCMD cmd)
320 {
321 uint32_t len;
322 uint8_t capa_to_assert = 0;
323
324 switch (cmd) {
325 case ERASE_4K:
326 len = 4 << 10;
327 capa_to_assert = ER_4K;
328 break;
329 case ERASE_32K:
330 len = 32 << 10;
331 capa_to_assert = ER_32K;
332 break;
333 case ERASE_SECTOR:
334 len = s->pi->sector_size;
335 break;
336 case BULK_ERASE:
337 len = s->size;
338 break;
339 default:
340 abort();
341 }
342
343 DB_PRINT_L(0, "offset = %#x, len = %d\n", offset, len);
344 if ((s->pi->flags & capa_to_assert) != capa_to_assert) {
345 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: %d erase size not supported by"
346 " device\n", len);
347 }
348
349 if (!s->write_enable) {
350 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: erase with write protect!\n");
351 return;
352 }
353 memset(s->storage + offset, 0xff, len);
354 flash_sync_area(s, offset, len);
355 }
356
357 static inline void flash_sync_dirty(Flash *s, int64_t newpage)
358 {
359 if (s->dirty_page >= 0 && s->dirty_page != newpage) {
360 flash_sync_page(s, s->dirty_page);
361 s->dirty_page = newpage;
362 }
363 }
364
365 static inline
366 void flash_write8(Flash *s, uint64_t addr, uint8_t data)
367 {
368 int64_t page = addr / s->pi->page_size;
369 uint8_t prev = s->storage[s->cur_addr];
370
371 if (!s->write_enable) {
372 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: write with write protect!\n");
373 }
374
375 if ((prev ^ data) & data) {
376 DB_PRINT_L(1, "programming zero to one! addr=%" PRIx64 " %" PRIx8
377 " -> %" PRIx8 "\n", addr, prev, data);
378 }
379
380 if (s->pi->flags & WR_1) {
381 s->storage[s->cur_addr] = data;
382 } else {
383 s->storage[s->cur_addr] &= data;
384 }
385
386 flash_sync_dirty(s, page);
387 s->dirty_page = page;
388 }
389
390 static void complete_collecting_data(Flash *s)
391 {
392 s->cur_addr = s->data[0] << 16;
393 s->cur_addr |= s->data[1] << 8;
394 s->cur_addr |= s->data[2];
395
396 s->state = STATE_IDLE;
397
398 switch (s->cmd_in_progress) {
399 case DPP:
400 case QPP:
401 case PP:
402 s->state = STATE_PAGE_PROGRAM;
403 break;
404 case READ:
405 case FAST_READ:
406 case DOR:
407 case QOR:
408 case DIOR:
409 case QIOR:
410 s->state = STATE_READ;
411 break;
412 case ERASE_4K:
413 case ERASE_32K:
414 case ERASE_SECTOR:
415 flash_erase(s, s->cur_addr, s->cmd_in_progress);
416 break;
417 case WRSR:
418 if (s->write_enable) {
419 s->write_enable = false;
420 }
421 break;
422 default:
423 break;
424 }
425 }
426
427 static void decode_new_cmd(Flash *s, uint32_t value)
428 {
429 s->cmd_in_progress = value;
430 DB_PRINT_L(0, "decoded new command:%x\n", value);
431
432 switch (value) {
433
434 case ERASE_4K:
435 case ERASE_32K:
436 case ERASE_SECTOR:
437 case READ:
438 case DPP:
439 case QPP:
440 case PP:
441 s->needed_bytes = 3;
442 s->pos = 0;
443 s->len = 0;
444 s->state = STATE_COLLECTING_DATA;
445 break;
446
447 case FAST_READ:
448 case DOR:
449 case QOR:
450 s->needed_bytes = 4;
451 s->pos = 0;
452 s->len = 0;
453 s->state = STATE_COLLECTING_DATA;
454 break;
455
456 case DIOR:
457 switch ((s->pi->jedec >> 16) & 0xFF) {
458 case JEDEC_WINBOND:
459 case JEDEC_SPANSION:
460 s->needed_bytes = 4;
461 break;
462 case JEDEC_NUMONYX:
463 default:
464 s->needed_bytes = 5;
465 }
466 s->pos = 0;
467 s->len = 0;
468 s->state = STATE_COLLECTING_DATA;
469 break;
470
471 case QIOR:
472 switch ((s->pi->jedec >> 16) & 0xFF) {
473 case JEDEC_WINBOND:
474 case JEDEC_SPANSION:
475 s->needed_bytes = 6;
476 break;
477 case JEDEC_NUMONYX:
478 default:
479 s->needed_bytes = 8;
480 }
481 s->pos = 0;
482 s->len = 0;
483 s->state = STATE_COLLECTING_DATA;
484 break;
485
486 case WRSR:
487 if (s->write_enable) {
488 s->needed_bytes = 1;
489 s->pos = 0;
490 s->len = 0;
491 s->state = STATE_COLLECTING_DATA;
492 }
493 break;
494
495 case WRDI:
496 s->write_enable = false;
497 break;
498 case WREN:
499 s->write_enable = true;
500 break;
501
502 case RDSR:
503 s->data[0] = (!!s->write_enable) << 1;
504 s->pos = 0;
505 s->len = 1;
506 s->state = STATE_READING_DATA;
507 break;
508
509 case JEDEC_READ:
510 DB_PRINT_L(0, "populated jedec code\n");
511 s->data[0] = (s->pi->jedec >> 16) & 0xff;
512 s->data[1] = (s->pi->jedec >> 8) & 0xff;
513 s->data[2] = s->pi->jedec & 0xff;
514 if (s->pi->ext_jedec) {
515 s->data[3] = (s->pi->ext_jedec >> 8) & 0xff;
516 s->data[4] = s->pi->ext_jedec & 0xff;
517 s->len = 5;
518 } else {
519 s->len = 3;
520 }
521 s->pos = 0;
522 s->state = STATE_READING_DATA;
523 break;
524
525 case BULK_ERASE:
526 if (s->write_enable) {
527 DB_PRINT_L(0, "chip erase\n");
528 flash_erase(s, 0, BULK_ERASE);
529 } else {
530 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: chip erase with write "
531 "protect!\n");
532 }
533 break;
534 case NOP:
535 break;
536 default:
537 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value);
538 break;
539 }
540 }
541
542 static int m25p80_cs(SSISlave *ss, bool select)
543 {
544 Flash *s = FROM_SSI_SLAVE(Flash, ss);
545
546 if (select) {
547 s->len = 0;
548 s->pos = 0;
549 s->state = STATE_IDLE;
550 flash_sync_dirty(s, -1);
551 }
552
553 DB_PRINT_L(0, "%sselect\n", select ? "de" : "");
554
555 return 0;
556 }
557
558 static uint32_t m25p80_transfer8(SSISlave *ss, uint32_t tx)
559 {
560 Flash *s = FROM_SSI_SLAVE(Flash, ss);
561 uint32_t r = 0;
562
563 switch (s->state) {
564
565 case STATE_PAGE_PROGRAM:
566 DB_PRINT_L(1, "page program cur_addr=%#" PRIx64 " data=%" PRIx8 "\n",
567 s->cur_addr, (uint8_t)tx);
568 flash_write8(s, s->cur_addr, (uint8_t)tx);
569 s->cur_addr++;
570 break;
571
572 case STATE_READ:
573 r = s->storage[s->cur_addr];
574 DB_PRINT_L(1, "READ 0x%" PRIx64 "=%" PRIx8 "\n", s->cur_addr,
575 (uint8_t)r);
576 s->cur_addr = (s->cur_addr + 1) % s->size;
577 break;
578
579 case STATE_COLLECTING_DATA:
580 s->data[s->len] = (uint8_t)tx;
581 s->len++;
582
583 if (s->len == s->needed_bytes) {
584 complete_collecting_data(s);
585 }
586 break;
587
588 case STATE_READING_DATA:
589 r = s->data[s->pos];
590 s->pos++;
591 if (s->pos == s->len) {
592 s->pos = 0;
593 s->state = STATE_IDLE;
594 }
595 break;
596
597 default:
598 case STATE_IDLE:
599 decode_new_cmd(s, (uint8_t)tx);
600 break;
601 }
602
603 return r;
604 }
605
606 static int m25p80_init(SSISlave *ss)
607 {
608 DriveInfo *dinfo;
609 Flash *s = FROM_SSI_SLAVE(Flash, ss);
610 M25P80Class *mc = M25P80_GET_CLASS(s);
611
612 s->pi = mc->pi;
613
614 s->size = s->pi->sector_size * s->pi->n_sectors;
615 s->dirty_page = -1;
616 s->storage = qemu_blockalign(s->bdrv, s->size);
617
618 dinfo = drive_get_next(IF_MTD);
619
620 if (dinfo && dinfo->bdrv) {
621 DB_PRINT_L(0, "Binding to IF_MTD drive\n");
622 s->bdrv = dinfo->bdrv;
623 /* FIXME: Move to late init */
624 if (bdrv_read(s->bdrv, 0, s->storage, DIV_ROUND_UP(s->size,
625 BDRV_SECTOR_SIZE))) {
626 fprintf(stderr, "Failed to initialize SPI flash!\n");
627 return 1;
628 }
629 } else {
630 DB_PRINT_L(0, "No BDRV - binding to RAM\n");
631 memset(s->storage, 0xFF, s->size);
632 }
633
634 return 0;
635 }
636
637 static void m25p80_pre_save(void *opaque)
638 {
639 flash_sync_dirty((Flash *)opaque, -1);
640 }
641
642 static const VMStateDescription vmstate_m25p80 = {
643 .name = "xilinx_spi",
644 .version_id = 1,
645 .minimum_version_id = 1,
646 .minimum_version_id_old = 1,
647 .pre_save = m25p80_pre_save,
648 .fields = (VMStateField[]) {
649 VMSTATE_UINT8(state, Flash),
650 VMSTATE_UINT8_ARRAY(data, Flash, 16),
651 VMSTATE_UINT32(len, Flash),
652 VMSTATE_UINT32(pos, Flash),
653 VMSTATE_UINT8(needed_bytes, Flash),
654 VMSTATE_UINT8(cmd_in_progress, Flash),
655 VMSTATE_UINT64(cur_addr, Flash),
656 VMSTATE_BOOL(write_enable, Flash),
657 VMSTATE_END_OF_LIST()
658 }
659 };
660
661 static void m25p80_class_init(ObjectClass *klass, void *data)
662 {
663 DeviceClass *dc = DEVICE_CLASS(klass);
664 SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
665 M25P80Class *mc = M25P80_CLASS(klass);
666
667 k->init = m25p80_init;
668 k->transfer = m25p80_transfer8;
669 k->set_cs = m25p80_cs;
670 k->cs_polarity = SSI_CS_LOW;
671 dc->vmsd = &vmstate_m25p80;
672 mc->pi = data;
673 }
674
675 static const TypeInfo m25p80_info = {
676 .name = TYPE_M25P80,
677 .parent = TYPE_SSI_SLAVE,
678 .instance_size = sizeof(Flash),
679 .class_size = sizeof(M25P80Class),
680 .abstract = true,
681 };
682
683 static void m25p80_register_types(void)
684 {
685 int i;
686
687 type_register_static(&m25p80_info);
688 for (i = 0; i < ARRAY_SIZE(known_devices); ++i) {
689 TypeInfo ti = {
690 .name = known_devices[i].part_name,
691 .parent = TYPE_M25P80,
692 .class_init = m25p80_class_init,
693 .class_data = (void *)&known_devices[i],
694 };
695 type_register(&ti);
696 }
697 }
698
699 type_init(m25p80_register_types)
AR7 emulation for QEMU