?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge tag 'v9.0.0-rc3'
[qemu/ar7.git] / hw / block / m25p80.c
blob8dec134832a14b03d065080db49a029d0450acdd
1 /*
2 * ST M25P80 emulator. Emulate all SPI flash devices based on the m25p80 command
3 * set. Known devices table current as of Jun/2012 and taken from linux.
4 * See drivers/mtd/devices/m25p80.c.
5 *
6 * Copyright (C) 2011 Edgar E. Iglesias <edgar.iglesias@gmail.com>
7 * Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
8 * Copyright (C) 2012 PetaLogix
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 or
13 * (at your option) a later version of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, see <http://www.gnu.org/licenses/>.
22 */
23
24 #include "qemu/osdep.h"
25 #include "qemu/units.h"
26 #include "sysemu/block-backend.h"
27 #include "hw/block/block.h"
28 #include "hw/block/flash.h"
29 #include "hw/qdev-properties.h"
30 #include "hw/qdev-properties-system.h"
31 #include "hw/ssi/ssi.h"
32 #include "migration/vmstate.h"
33 #include "qemu/bitops.h"
34 #include "qemu/log.h"
35 #include "qemu/module.h"
36 #include "qemu/error-report.h"
37 #include "qapi/error.h"
38 #include "trace.h"
39 #include "qom/object.h"
40 #include "m25p80_sfdp.h"
41
42 /* 16 MiB max in 3 byte address mode */
43 #define MAX_3BYTES_SIZE 0x1000000
44 #define SPI_NOR_MAX_ID_LEN 6
45
46 /* Fields for FlashPartInfo->flags */
47 enum spi_flash_option_flags {
48 ER_4K = BIT(0),
49 ER_32K = BIT(1),
50 EEPROM = BIT(2),
51 HAS_SR_TB = BIT(3),
52 HAS_SR_BP3_BIT6 = BIT(4),
53 };
54
55 typedef struct FlashPartInfo {
56 const char *part_name;
57 /*
58 * This array stores the ID bytes.
59 * The first three bytes are the JEDIC ID.
60 * JEDEC ID zero means "no ID" (mostly older chips).
61 */
62 uint8_t id[SPI_NOR_MAX_ID_LEN];
63 uint8_t id_len;
64 /* there is confusion between manufacturers as to what a sector is. In this
65 * device model, a "sector" is the size that is erased by the ERASE_SECTOR
66 * command (opcode 0xd8).
67 */
68 uint32_t sector_size;
69 uint32_t n_sectors;
70 uint32_t page_size;
71 uint16_t flags;
72 /*
73 * Big sized spi nor are often stacked devices, thus sometime
74 * replace chip erase with die erase.
75 * This field inform how many die is in the chip.
76 */
77 uint8_t die_cnt;
78 uint8_t (*sfdp_read)(uint32_t sfdp_addr);
79 } FlashPartInfo;
80
81 /* adapted from linux */
82 /* Used when the "_ext_id" is two bytes at most */
83 #define INFO(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\
84 .part_name = _part_name,\
85 .id = {\
86 ((_jedec_id) >> 16) & 0xff,\
87 ((_jedec_id) >> 8) & 0xff,\
88 (_jedec_id) & 0xff,\
89 ((_ext_id) >> 8) & 0xff,\
90 (_ext_id) & 0xff,\
91 },\
92 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\
93 .sector_size = (_sector_size),\
94 .n_sectors = (_n_sectors),\
95 .page_size = 256,\
96 .flags = (_flags),\
97 .die_cnt = 0
98
99 #define INFO6(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\
100 .part_name = _part_name,\
101 .id = {\
102 ((_jedec_id) >> 16) & 0xff,\
103 ((_jedec_id) >> 8) & 0xff,\
104 (_jedec_id) & 0xff,\
105 ((_ext_id) >> 16) & 0xff,\
106 ((_ext_id) >> 8) & 0xff,\
107 (_ext_id) & 0xff,\
108 },\
109 .id_len = 6,\
110 .sector_size = (_sector_size),\
111 .n_sectors = (_n_sectors),\
112 .page_size = 256,\
113 .flags = (_flags),\
114 .die_cnt = 0
115
116 #define INFO_STACKED(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors,\
117 _flags, _die_cnt)\
118 .part_name = _part_name,\
119 .id = {\
120 ((_jedec_id) >> 16) & 0xff,\
121 ((_jedec_id) >> 8) & 0xff,\
122 (_jedec_id) & 0xff,\
123 ((_ext_id) >> 8) & 0xff,\
124 (_ext_id) & 0xff,\
125 },\
126 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\
127 .sector_size = (_sector_size),\
128 .n_sectors = (_n_sectors),\
129 .page_size = 256,\
130 .flags = (_flags),\
131 .die_cnt = _die_cnt
132
133 #define JEDEC_NUMONYX 0x20
134 #define JEDEC_WINBOND 0xEF
135 #define JEDEC_SPANSION 0x01
136
137 /* Numonyx (Micron) Configuration register macros */
138 #define VCFG_DUMMY 0x1
139 #define VCFG_WRAP_SEQUENTIAL 0x2
140 #define NVCFG_XIP_MODE_DISABLED (7 << 9)
141 #define NVCFG_XIP_MODE_MASK (7 << 9)
142 #define VCFG_XIP_MODE_DISABLED (1 << 3)
143 #define CFG_DUMMY_CLK_LEN 4
144 #define NVCFG_DUMMY_CLK_POS 12
145 #define VCFG_DUMMY_CLK_POS 4
146 #define EVCFG_OUT_DRIVER_STRENGTH_DEF 7
147 #define EVCFG_VPP_ACCELERATOR (1 << 3)
148 #define EVCFG_RESET_HOLD_ENABLED (1 << 4)
149 #define NVCFG_DUAL_IO_MASK (1 << 2)
150 #define EVCFG_DUAL_IO_DISABLED (1 << 6)
151 #define NVCFG_QUAD_IO_MASK (1 << 3)
152 #define EVCFG_QUAD_IO_DISABLED (1 << 7)
153 #define NVCFG_4BYTE_ADDR_MASK (1 << 0)
154 #define NVCFG_LOWER_SEGMENT_MASK (1 << 1)
155
156 /* Numonyx (Micron) Flag Status Register macros */
157 #define FSR_4BYTE_ADDR_MODE_ENABLED 0x1
158 #define FSR_FLASH_READY (1 << 7)
159
160 /* Spansion configuration registers macros. */
161 #define SPANSION_QUAD_CFG_POS 0
162 #define SPANSION_QUAD_CFG_LEN 1
163 #define SPANSION_DUMMY_CLK_POS 0
164 #define SPANSION_DUMMY_CLK_LEN 4
165 #define SPANSION_ADDR_LEN_POS 7
166 #define SPANSION_ADDR_LEN_LEN 1
167
168 /*
169 * Spansion read mode command length in bytes,
170 * the mode is currently not supported.
171 */
172
173 #define SPANSION_CONTINUOUS_READ_MODE_CMD_LEN 1
174 #define WINBOND_CONTINUOUS_READ_MODE_CMD_LEN 1
175
176 static const FlashPartInfo known_devices[] = {
177 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
178 { INFO("at25fs010", 0x1f6601, 0, 32 << 10, 4, ER_4K) },
179 { INFO("at25fs040", 0x1f6604, 0, 64 << 10, 8, ER_4K) },
180
181 { INFO("at25df041a", 0x1f4401, 0, 64 << 10, 8, ER_4K) },
182 { INFO("at25df321a", 0x1f4701, 0, 64 << 10, 64, ER_4K) },
183 { INFO("at25df641", 0x1f4800, 0, 64 << 10, 128, ER_4K) },
184
185 { INFO("at26f004", 0x1f0400, 0, 64 << 10, 8, ER_4K) },
186 { INFO("at26df081a", 0x1f4501, 0, 64 << 10, 16, ER_4K) },
187 { INFO("at26df161a", 0x1f4601, 0, 64 << 10, 32, ER_4K) },
188 { INFO("at26df321", 0x1f4700, 0, 64 << 10, 64, ER_4K) },
189
190 { INFO("at45db081d", 0x1f2500, 0, 64 << 10, 16, ER_4K) },
191
192 /* Atmel EEPROMS - it is assumed, that don't care bit in command
193 * is set to 0. Block protection is not supported.
194 */
195 { INFO("at25128a-nonjedec", 0x0, 0, 1, 131072, EEPROM) },
196 { INFO("at25256a-nonjedec", 0x0, 0, 1, 262144, EEPROM) },
197
198 /* EON -- en25xxx */
199 { INFO("en25f32", 0x1c3116, 0, 64 << 10, 64, ER_4K) },
200 { INFO("en25p32", 0x1c2016, 0, 64 << 10, 64, 0) },
201 { INFO("en25q32b", 0x1c3016, 0, 64 << 10, 64, 0) },
202 { INFO("en25p64", 0x1c2017, 0, 64 << 10, 128, 0) },
203 { INFO("en25q64", 0x1c3017, 0, 64 << 10, 128, ER_4K) },
204
205 /* GigaDevice */
206 { INFO("gd25q32", 0xc84016, 0, 64 << 10, 64, ER_4K) },
207 { INFO("gd25q64", 0xc84017, 0, 64 << 10, 128, ER_4K) },
208
209 /* Intel/Numonyx -- xxxs33b */
210 { INFO("160s33b", 0x898911, 0, 64 << 10, 32, 0) },
211 { INFO("320s33b", 0x898912, 0, 64 << 10, 64, 0) },
212 { INFO("640s33b", 0x898913, 0, 64 << 10, 128, 0) },
213 { INFO("n25q064", 0x20ba17, 0, 64 << 10, 128, 0) },
214
215 /* ISSI */
216 { INFO("is25lq040b", 0x9d4013, 0, 64 << 10, 8, ER_4K) },
217 { INFO("is25lp080d", 0x9d6014, 0, 64 << 10, 16, ER_4K) },
218 { INFO("is25lp016d", 0x9d6015, 0, 64 << 10, 32, ER_4K) },
219 { INFO("is25lp032", 0x9d6016, 0, 64 << 10, 64, ER_4K) },
220 { INFO("is25lp064", 0x9d6017, 0, 64 << 10, 128, ER_4K) },
221 { INFO("is25lp128", 0x9d6018, 0, 64 << 10, 256, ER_4K) },
222 { INFO("is25lp256", 0x9d6019, 0, 64 << 10, 512, ER_4K) },
223 { INFO("is25wp032", 0x9d7016, 0, 64 << 10, 64, ER_4K) },
224 { INFO("is25wp064", 0x9d7017, 0, 64 << 10, 128, ER_4K) },
225 { INFO("is25wp128", 0x9d7018, 0, 64 << 10, 256, ER_4K) },
226 { INFO("is25wp256", 0x9d7019, 0, 64 << 10, 512, ER_4K),
227 .sfdp_read = m25p80_sfdp_is25wp256 },
228
229 /* Macronix */
230 { INFO("mx25l2005a", 0xc22012, 0, 64 << 10, 4, ER_4K) },
231 { INFO("mx25l4005a", 0xc22013, 0, 64 << 10, 8, ER_4K) },
232 { INFO("mx25l8005", 0xc22014, 0, 64 << 10, 16, 0) },
233 { INFO("mx25l1606e", 0xc22015, 0, 64 << 10, 32, ER_4K) },
234 { INFO("mx25l3205d", 0xc22016, 0, 64 << 10, 64, 0) },
235 { INFO("mx25l6405d", 0xc22017, 0, 64 << 10, 128, 0) },
236 { INFO("mx25l12805d", 0xc22018, 0, 64 << 10, 256, 0) },
237 { INFO("mx25l12855e", 0xc22618, 0, 64 << 10, 256, 0) },
238 { INFO6("mx25l25635e", 0xc22019, 0xc22019, 64 << 10, 512,
239 ER_4K | ER_32K), .sfdp_read = m25p80_sfdp_mx25l25635e },
240 { INFO6("mx25l25635f", 0xc22019, 0xc22019, 64 << 10, 512,
241 ER_4K | ER_32K), .sfdp_read = m25p80_sfdp_mx25l25635f },
242 { INFO("mx25l25655e", 0xc22619, 0, 64 << 10, 512, 0) },
243 { INFO("mx66l51235f", 0xc2201a, 0, 64 << 10, 1024, ER_4K | ER_32K) },
244 { INFO("mx66u51235f", 0xc2253a, 0, 64 << 10, 1024, ER_4K | ER_32K) },
245 { INFO("mx66u1g45g", 0xc2253b, 0, 64 << 10, 2048, ER_4K | ER_32K) },
246 { INFO("mx66l1g45g", 0xc2201b, 0, 64 << 10, 2048, ER_4K | ER_32K),
247 .sfdp_read = m25p80_sfdp_mx66l1g45g },
248
249 /* Micron */
250 { INFO("n25q032a11", 0x20bb16, 0, 64 << 10, 64, ER_4K) },
251 { INFO("n25q032a13", 0x20ba16, 0, 64 << 10, 64, ER_4K) },
252 { INFO("n25q064a11", 0x20bb17, 0, 64 << 10, 128, ER_4K) },
253 { INFO("n25q064a13", 0x20ba17, 0, 64 << 10, 128, ER_4K) },
254 { INFO("n25q128a11", 0x20bb18, 0, 64 << 10, 256, ER_4K) },
255 { INFO("n25q128a13", 0x20ba18, 0, 64 << 10, 256, ER_4K) },
256 { INFO("n25q256a11", 0x20bb19, 0, 64 << 10, 512, ER_4K) },
257 { INFO("n25q256a13", 0x20ba19, 0, 64 << 10, 512, ER_4K),
258 .sfdp_read = m25p80_sfdp_n25q256a },
259 { INFO("n25q512a11", 0x20bb20, 0, 64 << 10, 1024, ER_4K) },
260 { INFO("n25q512a13", 0x20ba20, 0, 64 << 10, 1024, ER_4K) },
261 { INFO("n25q128", 0x20ba18, 0, 64 << 10, 256, 0) },
262 { INFO("n25q256a", 0x20ba19, 0, 64 << 10, 512,
263 ER_4K | HAS_SR_BP3_BIT6 | HAS_SR_TB),
264 .sfdp_read = m25p80_sfdp_n25q256a },
265 { INFO("n25q512a", 0x20ba20, 0, 64 << 10, 1024, ER_4K) },
266 { INFO("n25q512ax3", 0x20ba20, 0x1000, 64 << 10, 1024, ER_4K) },
267 { INFO("mt25ql512ab", 0x20ba20, 0x1044, 64 << 10, 1024, ER_4K | ER_32K) },
268 { INFO_STACKED("mt35xu01g", 0x2c5b1b, 0x104100, 128 << 10, 1024,
269 ER_4K | ER_32K, 2) },
270 { INFO_STACKED("mt35xu02gbba", 0x2c5b1c, 0x104100, 128 << 10, 2048,
271 ER_4K | ER_32K, 4),
272 .sfdp_read = m25p80_sfdp_mt35xu02g },
273 { INFO_STACKED("n25q00", 0x20ba21, 0x1000, 64 << 10, 2048, ER_4K, 4) },
274 { INFO_STACKED("n25q00a", 0x20bb21, 0x1000, 64 << 10, 2048, ER_4K, 4) },
275 { INFO_STACKED("mt25ql01g", 0x20ba21, 0x1040, 64 << 10, 2048, ER_4K, 2) },
276 { INFO_STACKED("mt25qu01g", 0x20bb21, 0x1040, 64 << 10, 2048, ER_4K, 2) },
277 { INFO_STACKED("mt25ql02g", 0x20ba22, 0x1040, 64 << 10, 4096, ER_4K | ER_32K, 2) },
278 { INFO_STACKED("mt25qu02g", 0x20bb22, 0x1040, 64 << 10, 4096, ER_4K | ER_32K, 2) },
279
280 /* Spansion -- single (large) sector size only, at least
281 * for the chips listed here (without boot sectors).
282 */
283 { INFO("s25sl032p", 0x010215, 0x4d00, 64 << 10, 64, ER_4K) },
284 { INFO("s25sl064p", 0x010216, 0x4d00, 64 << 10, 128, ER_4K) },
285 { INFO("s25fl256s0", 0x010219, 0x4d00, 256 << 10, 128, 0) },
286 { INFO("s25fl256s1", 0x010219, 0x4d01, 64 << 10, 512, 0) },
287 { INFO6("s25fl512s", 0x010220, 0x4d0080, 256 << 10, 256, 0) },
288 { INFO6("s70fl01gs", 0x010221, 0x4d0080, 256 << 10, 512, 0) },
289 { INFO("s25sl12800", 0x012018, 0x0300, 256 << 10, 64, 0) },
290 { INFO("s25sl12801", 0x012018, 0x0301, 64 << 10, 256, 0) },
291 { INFO("s25fl129p0", 0x012018, 0x4d00, 256 << 10, 64, 0) },
292 { INFO("s25fl129p1", 0x012018, 0x4d01, 64 << 10, 256, 0) },
293 { INFO("s25sl004a", 0x010212, 0, 64 << 10, 8, 0) },
294 { INFO("s25sl008a", 0x010213, 0, 64 << 10, 16, 0) },
295 { INFO("s25sl016a", 0x010214, 0, 64 << 10, 32, 0) },
296 { INFO("s25sl032a", 0x010215, 0, 64 << 10, 64, 0) },
297 { INFO("s25sl064a", 0x010216, 0, 64 << 10, 128, 0) },
298 { INFO("s25fl016k", 0xef4015, 0, 64 << 10, 32, ER_4K | ER_32K) },
299 { INFO("s25fl064k", 0xef4017, 0, 64 << 10, 128, ER_4K | ER_32K) },
300
301 /* Spansion -- boot sectors support */
302 { INFO6("s25fs512s", 0x010220, 0x4d0081, 256 << 10, 256, 0) },
303 { INFO6("s70fs01gs", 0x010221, 0x4d0081, 256 << 10, 512, 0) },
304
305 /* SST -- large erase sizes are "overlays", "sectors" are 4<< 10 */
306 { INFO("sst25vf040b", 0xbf258d, 0, 64 << 10, 8, ER_4K) },
307 { INFO("sst25vf080b", 0xbf258e, 0, 64 << 10, 16, ER_4K) },
308 { INFO("sst25vf016b", 0xbf2541, 0, 64 << 10, 32, ER_4K) },
309 { INFO("sst25vf032b", 0xbf254a, 0, 64 << 10, 64, ER_4K) },
310 { INFO("sst25wf512", 0xbf2501, 0, 64 << 10, 1, ER_4K) },
311 { INFO("sst25wf010", 0xbf2502, 0, 64 << 10, 2, ER_4K) },
312 { INFO("sst25wf020", 0xbf2503, 0, 64 << 10, 4, ER_4K) },
313 { INFO("sst25wf040", 0xbf2504, 0, 64 << 10, 8, ER_4K) },
314 { INFO("sst25wf080", 0xbf2505, 0, 64 << 10, 16, ER_4K) },
315
316 /* ST Microelectronics -- newer production may have feature updates */
317 { INFO("m25p05", 0x202010, 0, 32 << 10, 2, 0) },
318 { INFO("m25p10", 0x202011, 0, 32 << 10, 4, 0) },
319 { INFO("m25p20", 0x202012, 0, 64 << 10, 4, 0) },
320 { INFO("m25p40", 0x202013, 0, 64 << 10, 8, 0) },
321 { INFO("m25p80", 0x202014, 0, 64 << 10, 16, 0) },
322 { INFO("m25p16", 0x202015, 0, 64 << 10, 32, 0) },
323 { INFO("m25p32", 0x202016, 0, 64 << 10, 64, 0) },
324 { INFO("m25p64", 0x202017, 0, 64 << 10, 128, 0) },
325 { INFO("m25p128", 0x202018, 0, 256 << 10, 64, 0) },
326 { INFO("n25q032", 0x20ba16, 0, 64 << 10, 64, 0) },
327
328 { INFO("m45pe10", 0x204011, 0, 64 << 10, 2, 0) },
329 { INFO("m45pe80", 0x204014, 0, 64 << 10, 16, 0) },
330 { INFO("m45pe16", 0x204015, 0, 64 << 10, 32, 0) },
331
332 { INFO("m25pe20", 0x208012, 0, 64 << 10, 4, 0) },
333 { INFO("m25pe80", 0x208014, 0, 64 << 10, 16, 0) },
334 { INFO("m25pe16", 0x208015, 0, 64 << 10, 32, ER_4K) },
335
336 { INFO("m25px32", 0x207116, 0, 64 << 10, 64, ER_4K) },
337 { INFO("m25px32-s0", 0x207316, 0, 64 << 10, 64, ER_4K) },
338 { INFO("m25px32-s1", 0x206316, 0, 64 << 10, 64, ER_4K) },
339 { INFO("m25px64", 0x207117, 0, 64 << 10, 128, 0) },
340
341 /* Winbond -- w25x "blocks" are 64k, "sectors" are 4KiB */
342 { INFO("w25x10", 0xef3011, 0, 64 << 10, 2, ER_4K) },
343 { INFO("w25x20", 0xef3012, 0, 64 << 10, 4, ER_4K) },
344 { INFO("w25x40", 0xef3013, 0, 64 << 10, 8, ER_4K) },
345 { INFO("w25x80", 0xef3014, 0, 64 << 10, 16, ER_4K) },
346 { INFO("w25x16", 0xef3015, 0, 64 << 10, 32, ER_4K) },
347 { INFO("w25x32", 0xef3016, 0, 64 << 10, 64, ER_4K) },
348 { INFO("w25q32", 0xef4016, 0, 64 << 10, 64, ER_4K) },
349 { INFO("w25q32dw", 0xef6016, 0, 64 << 10, 64, ER_4K) },
350 { INFO("w25x64", 0xef3017, 0, 64 << 10, 128, ER_4K) },
351 { INFO("w25q64", 0xef4017, 0, 64 << 10, 128, ER_4K) },
352 { INFO("w25q80", 0xef5014, 0, 64 << 10, 16, ER_4K) },
353 { INFO("w25q80bl", 0xef4014, 0, 64 << 10, 16, ER_4K) },
354 { INFO("w25q256", 0xef4019, 0, 64 << 10, 512, ER_4K),
355 .sfdp_read = m25p80_sfdp_w25q256 },
356 { INFO("w25q512jv", 0xef4020, 0, 64 << 10, 1024, ER_4K),
357 .sfdp_read = m25p80_sfdp_w25q512jv },
358 { INFO("w25q01jvq", 0xef4021, 0, 64 << 10, 2048, ER_4K),
359 .sfdp_read = m25p80_sfdp_w25q01jvq },
360 };
361
362 typedef enum {
363 NOP = 0,
364 WRSR = 0x1,
365 WRDI = 0x4,
366 RDSR = 0x5,
367 WREN = 0x6,
368 BRRD = 0x16,
369 BRWR = 0x17,
370 JEDEC_READ = 0x9f,
371 BULK_ERASE_60 = 0x60,
372 BULK_ERASE = 0xc7,
373 READ_FSR = 0x70,
374 RDCR = 0x15,
375 RDSFDP = 0x5a,
376
377 READ = 0x03,
378 READ4 = 0x13,
379 FAST_READ = 0x0b,
380 FAST_READ4 = 0x0c,
381 DOR = 0x3b,
382 DOR4 = 0x3c,
383 QOR = 0x6b,
384 QOR4 = 0x6c,
385 DIOR = 0xbb,
386 DIOR4 = 0xbc,
387 QIOR = 0xeb,
388 QIOR4 = 0xec,
389
390 PP = 0x02,
391 PP4 = 0x12,
392 PP4_4 = 0x3e,
393 DPP = 0xa2,
394 QPP = 0x32,
395 QPP_4 = 0x34,
396 RDID_90 = 0x90,
397 RDID_AB = 0xab,
398 AAI_WP = 0xad,
399
400 ERASE_4K = 0x20,
401 ERASE4_4K = 0x21,
402 ERASE_32K = 0x52,
403 ERASE4_32K = 0x5c,
404 ERASE_SECTOR = 0xd8,
405 ERASE4_SECTOR = 0xdc,
406
407 EN_4BYTE_ADDR = 0xB7,
408 EX_4BYTE_ADDR = 0xE9,
409
410 EXTEND_ADDR_READ = 0xC8,
411 EXTEND_ADDR_WRITE = 0xC5,
412
413 RESET_ENABLE = 0x66,
414 RESET_MEMORY = 0x99,
415
416 /*
417 * Micron: 0x35 - enable QPI
418 * Spansion: 0x35 - read control register
419 */
420 RDCR_EQIO = 0x35,
421 RSTQIO = 0xf5,
422
423 RNVCR = 0xB5,
424 WNVCR = 0xB1,
425
426 RVCR = 0x85,
427 WVCR = 0x81,
428
429 REVCR = 0x65,
430 WEVCR = 0x61,
431
432 DIE_ERASE = 0xC4,
433 } FlashCMD;
434
435 typedef enum {
436 STATE_IDLE,
437 STATE_PAGE_PROGRAM,
438 STATE_READ,
439 STATE_COLLECTING_DATA,
440 STATE_COLLECTING_VAR_LEN_DATA,
441 STATE_READING_DATA,
442 STATE_READING_SFDP,
443 } CMDState;
444
445 typedef enum {
446 MAN_SPANSION,
447 MAN_MACRONIX,
448 MAN_NUMONYX,
449 MAN_WINBOND,
450 MAN_SST,
451 MAN_ISSI,
452 MAN_GENERIC,
453 } Manufacturer;
454
455 typedef enum {
456 MODE_STD = 0,
457 MODE_DIO = 1,
458 MODE_QIO = 2
459 } SPIMode;
460
461 #define M25P80_INTERNAL_DATA_BUFFER_SZ 16
462
463 struct Flash {
464 SSIPeripheral parent_obj;
465
466 BlockBackend *blk;
467
468 uint8_t *storage;
469 uint32_t size;
470 int page_size;
471
472 uint8_t state;
473 uint8_t data[M25P80_INTERNAL_DATA_BUFFER_SZ];
474 uint32_t len;
475 uint32_t pos;
476 bool data_read_loop;
477 uint8_t needed_bytes;
478 uint8_t cmd_in_progress;
479 uint32_t cur_addr;
480 uint32_t nonvolatile_cfg;
481 /* Configuration register for Macronix */
482 uint32_t volatile_cfg;
483 uint32_t enh_volatile_cfg;
484 /* Spansion cfg registers. */
485 uint8_t spansion_cr1nv;
486 uint8_t spansion_cr2nv;
487 uint8_t spansion_cr3nv;
488 uint8_t spansion_cr4nv;
489 uint8_t spansion_cr1v;
490 uint8_t spansion_cr2v;
491 uint8_t spansion_cr3v;
492 uint8_t spansion_cr4v;
493 bool wp_level;
494 bool write_enable;
495 bool four_bytes_address_mode;
496 bool reset_enable;
497 bool quad_enable;
498 bool aai_enable;
499 bool block_protect0;
500 bool block_protect1;
501 bool block_protect2;
502 bool block_protect3;
503 bool top_bottom_bit;
504 bool status_register_write_disabled;
505 uint8_t ear;
506
507 int64_t dirty_page;
508
509 const FlashPartInfo *pi;
510
511 };
512
513 struct M25P80Class {
514 SSIPeripheralClass parent_class;
515 FlashPartInfo *pi;
516 };
517
518 OBJECT_DECLARE_TYPE(Flash, M25P80Class, M25P80)
519
520 static inline Manufacturer get_man(Flash *s)
521 {
522 switch (s->pi->id[0]) {
523 case 0x20:
524 return MAN_NUMONYX;
525 case 0xEF:
526 return MAN_WINBOND;
527 case 0x01:
528 return MAN_SPANSION;
529 case 0xC2:
530 return MAN_MACRONIX;
531 case 0xBF:
532 return MAN_SST;
533 case 0x9D:
534 return MAN_ISSI;
535 default:
536 return MAN_GENERIC;
537 }
538 }
539
540 static void blk_sync_complete(void *opaque, int ret)
541 {
542 QEMUIOVector *iov = opaque;
543
544 qemu_iovec_destroy(iov);
545 g_free(iov);
546
547 /* do nothing. Masters do not directly interact with the backing store,
548 * only the working copy so no mutexing required.
549 */
550 }
551
552 static void flash_sync_page(Flash *s, int page)
553 {
554 QEMUIOVector *iov;
555
556 if (!s->blk || !blk_is_writable(s->blk)) {
557 return;
558 }
559
560 iov = g_new(QEMUIOVector, 1);
561 qemu_iovec_init(iov, 1);
562 qemu_iovec_add(iov, s->storage + page * s->pi->page_size,
563 s->pi->page_size);
564 blk_aio_pwritev(s->blk, page * s->pi->page_size, iov, 0,
565 blk_sync_complete, iov);
566 }
567
568 static inline void flash_sync_area(Flash *s, int64_t off, int64_t len)
569 {
570 QEMUIOVector *iov;
571
572 if (!s->blk || !blk_is_writable(s->blk)) {
573 return;
574 }
575
576 assert(!(len % BDRV_SECTOR_SIZE));
577 iov = g_new(QEMUIOVector, 1);
578 qemu_iovec_init(iov, 1);
579 qemu_iovec_add(iov, s->storage + off, len);
580 blk_aio_pwritev(s->blk, off, iov, 0, blk_sync_complete, iov);
581 }
582
583 static void flash_erase(Flash *s, int offset, FlashCMD cmd)
584 {
585 uint32_t len;
586 uint8_t capa_to_assert = 0;
587
588 switch (cmd) {
589 case ERASE_4K:
590 case ERASE4_4K:
591 len = 4 * KiB;
592 capa_to_assert = ER_4K;
593 break;
594 case ERASE_32K:
595 case ERASE4_32K:
596 len = 32 * KiB;
597 capa_to_assert = ER_32K;
598 break;
599 case ERASE_SECTOR:
600 case ERASE4_SECTOR:
601 len = s->pi->sector_size;
602 break;
603 case BULK_ERASE:
604 len = s->size;
605 break;
606 case DIE_ERASE:
607 if (s->pi->die_cnt) {
608 len = s->size / s->pi->die_cnt;
609 offset = offset & (~(len - 1));
610 } else {
611 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: die erase is not supported"
612 " by device\n");
613 return;
614 }
615 break;
616 default:
617 abort();
618 }
619
620 trace_m25p80_flash_erase(s, offset, len);
621
622 if ((s->pi->flags & capa_to_assert) != capa_to_assert) {
623 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: %d erase size not supported by"
624 " device\n", len);
625 }
626
627 if (!s->write_enable) {
628 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: erase with write protect!\n");
629 return;
630 }
631 memset(s->storage + offset, 0xff, len);
632 flash_sync_area(s, offset, len);
633 }
634
635 static inline void flash_sync_dirty(Flash *s, int64_t newpage)
636 {
637 if (s->dirty_page >= 0 && s->dirty_page != newpage) {
638 flash_sync_page(s, s->dirty_page);
639 s->dirty_page = newpage;
640 }
641 }
642
643 static inline
644 void flash_write8(Flash *s, uint32_t addr, uint8_t data)
645 {
646 uint32_t page = addr / s->pi->page_size;
647 uint8_t prev = s->storage[s->cur_addr];
648 uint32_t block_protect_value = (s->block_protect3 << 3) |
649 (s->block_protect2 << 2) |
650 (s->block_protect1 << 1) |
651 (s->block_protect0 << 0);
652
653 if (!s->write_enable) {
654 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: write with write protect!\n");
655 return;
656 }
657
658 if (block_protect_value > 0) {
659 uint32_t num_protected_sectors = 1 << (block_protect_value - 1);
660 uint32_t sector = addr / s->pi->sector_size;
661
662 /* top_bottom_bit == 0 means TOP */
663 if (!s->top_bottom_bit) {
664 if (s->pi->n_sectors <= sector + num_protected_sectors) {
665 qemu_log_mask(LOG_GUEST_ERROR,
666 "M25P80: write with write protect!\n");
667 return;
668 }
669 } else {
670 if (sector < num_protected_sectors) {
671 qemu_log_mask(LOG_GUEST_ERROR,
672 "M25P80: write with write protect!\n");
673 return;
674 }
675 }
676 }
677
678 if ((prev ^ data) & data) {
679 trace_m25p80_programming_zero_to_one(s, addr, prev, data);
680 }
681
682 if (s->pi->flags & EEPROM) {
683 s->storage[s->cur_addr] = data;
684 } else {
685 s->storage[s->cur_addr] &= data;
686 }
687
688 flash_sync_dirty(s, page);
689 s->dirty_page = page;
690 }
691
692 static inline int get_addr_length(Flash *s)
693 {
694 /* check if eeprom is in use */
695 if (s->pi->flags == EEPROM) {
696 return 2;
697 }
698
699 switch (s->cmd_in_progress) {
700 case RDSFDP:
701 return 3;
702 case PP4:
703 case PP4_4:
704 case QPP_4:
705 case READ4:
706 case QIOR4:
707 case ERASE4_4K:
708 case ERASE4_32K:
709 case ERASE4_SECTOR:
710 case FAST_READ4:
711 case DOR4:
712 case QOR4:
713 case DIOR4:
714 return 4;
715 default:
716 return s->four_bytes_address_mode ? 4 : 3;
717 }
718 }
719
720 static void complete_collecting_data(Flash *s)
721 {
722 int i, n;
723
724 n = get_addr_length(s);
725 s->cur_addr = (n == 3 ? s->ear : 0);
726 for (i = 0; i < n; ++i) {
727 s->cur_addr <<= 8;
728 s->cur_addr |= s->data[i];
729 }
730
731 s->cur_addr &= s->size - 1;
732
733 s->state = STATE_IDLE;
734
735 trace_m25p80_complete_collecting(s, s->cmd_in_progress, n, s->ear,
736 s->cur_addr);
737
738 switch (s->cmd_in_progress) {
739 case DPP:
740 case QPP:
741 case QPP_4:
742 case PP:
743 case PP4:
744 case PP4_4:
745 s->state = STATE_PAGE_PROGRAM;
746 break;
747 case AAI_WP:
748 /* AAI programming starts from the even address */
749 s->cur_addr &= ~BIT(0);
750 s->state = STATE_PAGE_PROGRAM;
751 break;
752 case READ:
753 case READ4:
754 case FAST_READ:
755 case FAST_READ4:
756 case DOR:
757 case DOR4:
758 case QOR:
759 case QOR4:
760 case DIOR:
761 case DIOR4:
762 case QIOR:
763 case QIOR4:
764 s->state = STATE_READ;
765 break;
766 case ERASE_4K:
767 case ERASE4_4K:
768 case ERASE_32K:
769 case ERASE4_32K:
770 case ERASE_SECTOR:
771 case ERASE4_SECTOR:
772 case DIE_ERASE:
773 flash_erase(s, s->cur_addr, s->cmd_in_progress);
774 break;
775 case WRSR:
776 s->status_register_write_disabled = extract32(s->data[0], 7, 1);
777 s->block_protect0 = extract32(s->data[0], 2, 1);
778 s->block_protect1 = extract32(s->data[0], 3, 1);
779 s->block_protect2 = extract32(s->data[0], 4, 1);
780 if (s->pi->flags & HAS_SR_TB) {
781 s->top_bottom_bit = extract32(s->data[0], 5, 1);
782 }
783 if (s->pi->flags & HAS_SR_BP3_BIT6) {
784 s->block_protect3 = extract32(s->data[0], 6, 1);
785 }
786
787 switch (get_man(s)) {
788 case MAN_SPANSION:
789 s->quad_enable = !!(s->data[1] & 0x02);
790 break;
791 case MAN_ISSI:
792 s->quad_enable = extract32(s->data[0], 6, 1);
793 break;
794 case MAN_MACRONIX:
795 s->quad_enable = extract32(s->data[0], 6, 1);
796 if (s->len > 1) {
797 s->volatile_cfg = s->data[1];
798 s->four_bytes_address_mode = extract32(s->data[1], 5, 1);
799 }
800 break;
801 default:
802 break;
803 }
804 if (s->write_enable) {
805 s->write_enable = false;
806 }
807 break;
808 case BRWR:
809 case EXTEND_ADDR_WRITE:
810 s->ear = s->data[0];
811 break;
812 case WNVCR:
813 s->nonvolatile_cfg = s->data[0] | (s->data[1] << 8);
814 break;
815 case WVCR:
816 s->volatile_cfg = s->data[0];
817 break;
818 case WEVCR:
819 s->enh_volatile_cfg = s->data[0];
820 break;
821 case RDID_90:
822 case RDID_AB:
823 if (get_man(s) == MAN_SST) {
824 if (s->cur_addr <= 1) {
825 if (s->cur_addr) {
826 s->data[0] = s->pi->id[2];
827 s->data[1] = s->pi->id[0];
828 } else {
829 s->data[0] = s->pi->id[0];
830 s->data[1] = s->pi->id[2];
831 }
832 s->pos = 0;
833 s->len = 2;
834 s->data_read_loop = true;
835 s->state = STATE_READING_DATA;
836 } else {
837 qemu_log_mask(LOG_GUEST_ERROR,
838 "M25P80: Invalid read id address\n");
839 }
840 } else {
841 qemu_log_mask(LOG_GUEST_ERROR,
842 "M25P80: Read id (command 0x90/0xAB) is not supported"
843 " by device\n");
844 }
845 break;
846
847 case RDSFDP:
848 s->state = STATE_READING_SFDP;
849 break;
850
851 default:
852 break;
853 }
854 }
855
856 static void reset_memory(Flash *s)
857 {
858 s->cmd_in_progress = NOP;
859 s->cur_addr = 0;
860 s->ear = 0;
861 s->four_bytes_address_mode = false;
862 s->len = 0;
863 s->needed_bytes = 0;
864 s->pos = 0;
865 s->state = STATE_IDLE;
866 s->write_enable = false;
867 s->reset_enable = false;
868 s->quad_enable = false;
869 s->aai_enable = false;
870
871 switch (get_man(s)) {
872 case MAN_NUMONYX:
873 s->volatile_cfg = 0;
874 s->volatile_cfg |= VCFG_DUMMY;
875 s->volatile_cfg |= VCFG_WRAP_SEQUENTIAL;
876 if ((s->nonvolatile_cfg & NVCFG_XIP_MODE_MASK)
877 == NVCFG_XIP_MODE_DISABLED) {
878 s->volatile_cfg |= VCFG_XIP_MODE_DISABLED;
879 }
880 s->volatile_cfg |= deposit32(s->volatile_cfg,
881 VCFG_DUMMY_CLK_POS,
882 CFG_DUMMY_CLK_LEN,
883 extract32(s->nonvolatile_cfg,
884 NVCFG_DUMMY_CLK_POS,
885 CFG_DUMMY_CLK_LEN)
886 );
887
888 s->enh_volatile_cfg = 0;
889 s->enh_volatile_cfg |= EVCFG_OUT_DRIVER_STRENGTH_DEF;
890 s->enh_volatile_cfg |= EVCFG_VPP_ACCELERATOR;
891 s->enh_volatile_cfg |= EVCFG_RESET_HOLD_ENABLED;
892 if (s->nonvolatile_cfg & NVCFG_DUAL_IO_MASK) {
893 s->enh_volatile_cfg |= EVCFG_DUAL_IO_DISABLED;
894 }
895 if (s->nonvolatile_cfg & NVCFG_QUAD_IO_MASK) {
896 s->enh_volatile_cfg |= EVCFG_QUAD_IO_DISABLED;
897 }
898 if (!(s->nonvolatile_cfg & NVCFG_4BYTE_ADDR_MASK)) {
899 s->four_bytes_address_mode = true;
900 }
901 if (!(s->nonvolatile_cfg & NVCFG_LOWER_SEGMENT_MASK)) {
902 s->ear = s->size / MAX_3BYTES_SIZE - 1;
903 }
904 break;
905 case MAN_MACRONIX:
906 s->volatile_cfg = 0x7;
907 break;
908 case MAN_SPANSION:
909 s->spansion_cr1v = s->spansion_cr1nv;
910 s->spansion_cr2v = s->spansion_cr2nv;
911 s->spansion_cr3v = s->spansion_cr3nv;
912 s->spansion_cr4v = s->spansion_cr4nv;
913 s->quad_enable = extract32(s->spansion_cr1v,
914 SPANSION_QUAD_CFG_POS,
915 SPANSION_QUAD_CFG_LEN
916 );
917 s->four_bytes_address_mode = extract32(s->spansion_cr2v,
918 SPANSION_ADDR_LEN_POS,
919 SPANSION_ADDR_LEN_LEN
920 );
921 break;
922 default:
923 break;
924 }
925
926 trace_m25p80_reset_done(s);
927 }
928
929 static uint8_t numonyx_mode(Flash *s)
930 {
931 if (!(s->enh_volatile_cfg & EVCFG_QUAD_IO_DISABLED)) {
932 return MODE_QIO;
933 } else if (!(s->enh_volatile_cfg & EVCFG_DUAL_IO_DISABLED)) {
934 return MODE_DIO;
935 } else {
936 return MODE_STD;
937 }
938 }
939
940 static uint8_t numonyx_extract_cfg_num_dummies(Flash *s)
941 {
942 uint8_t num_dummies;
943 uint8_t mode;
944 assert(get_man(s) == MAN_NUMONYX);
945
946 mode = numonyx_mode(s);
947 num_dummies = extract32(s->volatile_cfg, 4, 4);
948
949 if (num_dummies == 0x0 || num_dummies == 0xf) {
950 switch (s->cmd_in_progress) {
951 case QIOR:
952 case QIOR4:
953 num_dummies = 10;
954 break;
955 default:
956 num_dummies = (mode == MODE_QIO) ? 10 : 8;
957 break;
958 }
959 }
960
961 return num_dummies;
962 }
963
964 static void decode_fast_read_cmd(Flash *s)
965 {
966 s->needed_bytes = get_addr_length(s);
967 switch (get_man(s)) {
968 /* Dummy cycles - modeled with bytes writes instead of bits */
969 case MAN_SST:
970 s->needed_bytes += 1;
971 break;
972 case MAN_WINBOND:
973 s->needed_bytes += 8;
974 break;
975 case MAN_NUMONYX:
976 s->needed_bytes += numonyx_extract_cfg_num_dummies(s);
977 break;
978 case MAN_MACRONIX:
979 if (extract32(s->volatile_cfg, 6, 2) == 1) {
980 s->needed_bytes += 6;
981 } else {
982 s->needed_bytes += 8;
983 }
984 break;
985 case MAN_SPANSION:
986 s->needed_bytes += extract32(s->spansion_cr2v,
987 SPANSION_DUMMY_CLK_POS,
988 SPANSION_DUMMY_CLK_LEN
989 );
990 break;
991 case MAN_ISSI:
992 /*
993 * The Fast Read instruction code is followed by address bytes and
994 * dummy cycles, transmitted via the SI line.
995 *
996 * The number of dummy cycles is configurable but this is currently
997 * unmodeled, hence the default value 8 is used.
998 *
999 * QPI (Quad Peripheral Interface) mode has different default value
1000 * of dummy cycles, but this is unsupported at the time being.
1001 */
1002 s->needed_bytes += 1;
1003 break;
1004 default:
1005 break;
1006 }
1007 s->pos = 0;
1008 s->len = 0;
1009 s->state = STATE_COLLECTING_DATA;
1010 }
1011
1012 static void decode_dio_read_cmd(Flash *s)
1013 {
1014 s->needed_bytes = get_addr_length(s);
1015 /* Dummy cycles modeled with bytes writes instead of bits */
1016 switch (get_man(s)) {
1017 case MAN_WINBOND:
1018 s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN;
1019 break;
1020 case MAN_SPANSION:
1021 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN;
1022 s->needed_bytes += extract32(s->spansion_cr2v,
1023 SPANSION_DUMMY_CLK_POS,
1024 SPANSION_DUMMY_CLK_LEN
1025 );
1026 break;
1027 case MAN_NUMONYX:
1028 s->needed_bytes += numonyx_extract_cfg_num_dummies(s);
1029 break;
1030 case MAN_MACRONIX:
1031 switch (extract32(s->volatile_cfg, 6, 2)) {
1032 case 1:
1033 s->needed_bytes += 6;
1034 break;
1035 case 2:
1036 s->needed_bytes += 8;
1037 break;
1038 default:
1039 s->needed_bytes += 4;
1040 break;
1041 }
1042 break;
1043 case MAN_ISSI:
1044 /*
1045 * The Fast Read Dual I/O instruction code is followed by address bytes
1046 * and dummy cycles, transmitted via the IO1 and IO0 line.
1047 *
1048 * The number of dummy cycles is configurable but this is currently
1049 * unmodeled, hence the default value 4 is used.
1050 */
1051 s->needed_bytes += 1;
1052 break;
1053 default:
1054 break;
1055 }
1056 s->pos = 0;
1057 s->len = 0;
1058 s->state = STATE_COLLECTING_DATA;
1059 }
1060
1061 static void decode_qio_read_cmd(Flash *s)
1062 {
1063 s->needed_bytes = get_addr_length(s);
1064 /* Dummy cycles modeled with bytes writes instead of bits */
1065 switch (get_man(s)) {
1066 case MAN_WINBOND:
1067 s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN;
1068 s->needed_bytes += 4;
1069 break;
1070 case MAN_SPANSION:
1071 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN;
1072 s->needed_bytes += extract32(s->spansion_cr2v,
1073 SPANSION_DUMMY_CLK_POS,
1074 SPANSION_DUMMY_CLK_LEN
1075 );
1076 break;
1077 case MAN_NUMONYX:
1078 s->needed_bytes += numonyx_extract_cfg_num_dummies(s);
1079 break;
1080 case MAN_MACRONIX:
1081 switch (extract32(s->volatile_cfg, 6, 2)) {
1082 case 1:
1083 s->needed_bytes += 4;
1084 break;
1085 case 2:
1086 s->needed_bytes += 8;
1087 break;
1088 default:
1089 s->needed_bytes += 6;
1090 break;
1091 }
1092 break;
1093 case MAN_ISSI:
1094 /*
1095 * The Fast Read Quad I/O instruction code is followed by address bytes
1096 * and dummy cycles, transmitted via the IO3, IO2, IO1 and IO0 line.
1097 *
1098 * The number of dummy cycles is configurable but this is currently
1099 * unmodeled, hence the default value 6 is used.
1100 *
1101 * QPI (Quad Peripheral Interface) mode has different default value
1102 * of dummy cycles, but this is unsupported at the time being.
1103 */
1104 s->needed_bytes += 3;
1105 break;
1106 default:
1107 break;
1108 }
1109 s->pos = 0;
1110 s->len = 0;
1111 s->state = STATE_COLLECTING_DATA;
1112 }
1113
1114 static bool is_valid_aai_cmd(uint32_t cmd)
1115 {
1116 return cmd == AAI_WP || cmd == WRDI || cmd == RDSR;
1117 }
1118
1119 static void decode_new_cmd(Flash *s, uint32_t value)
1120 {
1121 int i;
1122
1123 s->cmd_in_progress = value;
1124 trace_m25p80_command_decoded(s, value);
1125
1126 if (value != RESET_MEMORY) {
1127 s->reset_enable = false;
1128 }
1129
1130 if (get_man(s) == MAN_SST && s->aai_enable && !is_valid_aai_cmd(value)) {
1131 qemu_log_mask(LOG_GUEST_ERROR,
1132 "M25P80: Invalid cmd within AAI programming sequence");
1133 }
1134
1135 switch (value) {
1136
1137 case ERASE_4K:
1138 case ERASE4_4K:
1139 case ERASE_32K:
1140 case ERASE4_32K:
1141 case ERASE_SECTOR:
1142 case ERASE4_SECTOR:
1143 case PP:
1144 case PP4:
1145 case DIE_ERASE:
1146 case RDID_90:
1147 case RDID_AB:
1148 s->needed_bytes = get_addr_length(s);
1149 s->pos = 0;
1150 s->len = 0;
1151 s->state = STATE_COLLECTING_DATA;
1152 break;
1153 case READ:
1154 case READ4:
1155 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) == MODE_STD) {
1156 s->needed_bytes = get_addr_length(s);
1157 s->pos = 0;
1158 s->len = 0;
1159 s->state = STATE_COLLECTING_DATA;
1160 } else {
1161 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
1162 "DIO or QIO mode\n", s->cmd_in_progress);
1163 }
1164 break;
1165 case DPP:
1166 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) {
1167 s->needed_bytes = get_addr_length(s);
1168 s->pos = 0;
1169 s->len = 0;
1170 s->state = STATE_COLLECTING_DATA;
1171 } else {
1172 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
1173 "QIO mode\n", s->cmd_in_progress);
1174 }
1175 break;
1176 case QPP:
1177 case QPP_4:
1178 case PP4_4:
1179 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) {
1180 s->needed_bytes = get_addr_length(s);
1181 s->pos = 0;
1182 s->len = 0;
1183 s->state = STATE_COLLECTING_DATA;
1184 } else {
1185 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
1186 "DIO mode\n", s->cmd_in_progress);
1187 }
1188 break;
1189
1190 case FAST_READ:
1191 case FAST_READ4:
1192 decode_fast_read_cmd(s);
1193 break;
1194 case DOR:
1195 case DOR4:
1196 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) {
1197 decode_fast_read_cmd(s);
1198 } else {
1199 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
1200 "QIO mode\n", s->cmd_in_progress);
1201 }
1202 break;
1203 case QOR:
1204 case QOR4:
1205 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) {
1206 decode_fast_read_cmd(s);
1207 } else {
1208 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
1209 "DIO mode\n", s->cmd_in_progress);
1210 }
1211 break;
1212
1213 case DIOR:
1214 case DIOR4:
1215 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) {
1216 decode_dio_read_cmd(s);
1217 } else {
1218 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
1219 "QIO mode\n", s->cmd_in_progress);
1220 }
1221 break;
1222
1223 case QIOR:
1224 case QIOR4:
1225 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) {
1226 decode_qio_read_cmd(s);
1227 } else {
1228 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
1229 "DIO mode\n", s->cmd_in_progress);
1230 }
1231 break;
1232
1233 case WRSR:
1234 /*
1235 * If WP# is low and status_register_write_disabled is high,
1236 * status register writes are disabled.
1237 * This is also called "hardware protected mode" (HPM). All other
1238 * combinations of the two states are called "software protected mode"
1239 * (SPM), and status register writes are permitted.
1240 */
1241 if ((s->wp_level == 0 && s->status_register_write_disabled)
1242 || !s->write_enable) {
1243 qemu_log_mask(LOG_GUEST_ERROR,
1244 "M25P80: Status register write is disabled!\n");
1245 break;
1246 }
1247
1248 switch (get_man(s)) {
1249 case MAN_SPANSION:
1250 s->needed_bytes = 2;
1251 s->state = STATE_COLLECTING_DATA;
1252 break;
1253 case MAN_MACRONIX:
1254 s->needed_bytes = 2;
1255 s->state = STATE_COLLECTING_VAR_LEN_DATA;
1256 break;
1257 default:
1258 s->needed_bytes = 1;
1259 s->state = STATE_COLLECTING_DATA;
1260 }
1261 s->pos = 0;
1262 break;
1263
1264 case WRDI:
1265 s->write_enable = false;
1266 if (get_man(s) == MAN_SST) {
1267 s->aai_enable = false;
1268 }
1269 break;
1270 case WREN:
1271 s->write_enable = true;
1272 break;
1273
1274 case RDSR:
1275 s->data[0] = (!!s->write_enable) << 1;
1276 s->data[0] |= (!!s->status_register_write_disabled) << 7;
1277 s->data[0] |= (!!s->block_protect0) << 2;
1278 s->data[0] |= (!!s->block_protect1) << 3;
1279 s->data[0] |= (!!s->block_protect2) << 4;
1280 if (s->pi->flags & HAS_SR_TB) {
1281 s->data[0] |= (!!s->top_bottom_bit) << 5;
1282 }
1283 if (s->pi->flags & HAS_SR_BP3_BIT6) {
1284 s->data[0] |= (!!s->block_protect3) << 6;
1285 }
1286
1287 if (get_man(s) == MAN_MACRONIX || get_man(s) == MAN_ISSI) {
1288 s->data[0] |= (!!s->quad_enable) << 6;
1289 }
1290 if (get_man(s) == MAN_SST) {
1291 s->data[0] |= (!!s->aai_enable) << 6;
1292 }
1293
1294 s->pos = 0;
1295 s->len = 1;
1296 s->data_read_loop = true;
1297 s->state = STATE_READING_DATA;
1298 break;
1299
1300 case READ_FSR:
1301 s->data[0] = FSR_FLASH_READY;
1302 if (s->four_bytes_address_mode) {
1303 s->data[0] |= FSR_4BYTE_ADDR_MODE_ENABLED;
1304 }
1305 s->pos = 0;
1306 s->len = 1;
1307 s->data_read_loop = true;
1308 s->state = STATE_READING_DATA;
1309 break;
1310
1311 case JEDEC_READ:
1312 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) == MODE_STD) {
1313 trace_m25p80_populated_jedec(s);
1314 for (i = 0; i < s->pi->id_len; i++) {
1315 s->data[i] = s->pi->id[i];
1316 }
1317 for (; i < SPI_NOR_MAX_ID_LEN; i++) {
1318 s->data[i] = 0;
1319 }
1320
1321 s->len = SPI_NOR_MAX_ID_LEN;
1322 s->pos = 0;
1323 s->state = STATE_READING_DATA;
1324 } else {
1325 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute JEDEC read "
1326 "in DIO or QIO mode\n");
1327 }
1328 break;
1329
1330 case RDCR:
1331 s->data[0] = s->volatile_cfg & 0xFF;
1332 s->data[0] |= (!!s->four_bytes_address_mode) << 5;
1333 s->pos = 0;
1334 s->len = 1;
1335 s->state = STATE_READING_DATA;
1336 break;
1337
1338 case BULK_ERASE_60:
1339 case BULK_ERASE:
1340 if (s->write_enable) {
1341 trace_m25p80_chip_erase(s);
1342 flash_erase(s, 0, BULK_ERASE);
1343 } else {
1344 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: chip erase with write "
1345 "protect!\n");
1346 }
1347 break;
1348 case NOP:
1349 break;
1350 case EN_4BYTE_ADDR:
1351 s->four_bytes_address_mode = true;
1352 break;
1353 case EX_4BYTE_ADDR:
1354 s->four_bytes_address_mode = false;
1355 break;
1356 case BRRD:
1357 case EXTEND_ADDR_READ:
1358 s->data[0] = s->ear;
1359 s->pos = 0;
1360 s->len = 1;
1361 s->state = STATE_READING_DATA;
1362 break;
1363 case BRWR:
1364 case EXTEND_ADDR_WRITE:
1365 if (s->write_enable) {
1366 s->needed_bytes = 1;
1367 s->pos = 0;
1368 s->len = 0;
1369 s->state = STATE_COLLECTING_DATA;
1370 }
1371 break;
1372 case RNVCR:
1373 s->data[0] = s->nonvolatile_cfg & 0xFF;
1374 s->data[1] = (s->nonvolatile_cfg >> 8) & 0xFF;
1375 s->pos = 0;
1376 s->len = 2;
1377 s->state = STATE_READING_DATA;
1378 break;
1379 case WNVCR:
1380 if (s->write_enable && get_man(s) == MAN_NUMONYX) {
1381 s->needed_bytes = 2;
1382 s->pos = 0;
1383 s->len = 0;
1384 s->state = STATE_COLLECTING_DATA;
1385 }
1386 break;
1387 case RVCR:
1388 s->data[0] = s->volatile_cfg & 0xFF;
1389 s->pos = 0;
1390 s->len = 1;
1391 s->state = STATE_READING_DATA;
1392 break;
1393 case WVCR:
1394 if (s->write_enable) {
1395 s->needed_bytes = 1;
1396 s->pos = 0;
1397 s->len = 0;
1398 s->state = STATE_COLLECTING_DATA;
1399 }
1400 break;
1401 case REVCR:
1402 s->data[0] = s->enh_volatile_cfg & 0xFF;
1403 s->pos = 0;
1404 s->len = 1;
1405 s->state = STATE_READING_DATA;
1406 break;
1407 case WEVCR:
1408 if (s->write_enable) {
1409 s->needed_bytes = 1;
1410 s->pos = 0;
1411 s->len = 0;
1412 s->state = STATE_COLLECTING_DATA;
1413 }
1414 break;
1415 case RESET_ENABLE:
1416 s->reset_enable = true;
1417 break;
1418 case RESET_MEMORY:
1419 if (s->reset_enable) {
1420 reset_memory(s);
1421 }
1422 break;
1423 case RDCR_EQIO:
1424 switch (get_man(s)) {
1425 case MAN_SPANSION:
1426 s->data[0] = (!!s->quad_enable) << 1;
1427 s->pos = 0;
1428 s->len = 1;
1429 s->state = STATE_READING_DATA;
1430 break;
1431 case MAN_MACRONIX:
1432 s->quad_enable = true;
1433 break;
1434 default:
1435 break;
1436 }
1437 break;
1438 case RSTQIO:
1439 s->quad_enable = false;
1440 break;
1441 case AAI_WP:
1442 if (get_man(s) == MAN_SST) {
1443 if (s->write_enable) {
1444 if (s->aai_enable) {
1445 s->state = STATE_PAGE_PROGRAM;
1446 } else {
1447 s->aai_enable = true;
1448 s->needed_bytes = get_addr_length(s);
1449 s->state = STATE_COLLECTING_DATA;
1450 }
1451 } else {
1452 qemu_log_mask(LOG_GUEST_ERROR,
1453 "M25P80: AAI_WP with write protect\n");
1454 }
1455 } else {
1456 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value);
1457 }
1458 break;
1459 case RDSFDP:
1460 if (s->pi->sfdp_read) {
1461 s->needed_bytes = get_addr_length(s) + 1; /* SFDP addr + dummy */
1462 s->pos = 0;
1463 s->len = 0;
1464 s->state = STATE_COLLECTING_DATA;
1465 break;
1466 }
1467 /* Fallthrough */
1468
1469 default:
1470 s->pos = 0;
1471 s->len = 1;
1472 s->state = STATE_READING_DATA;
1473 s->data_read_loop = true;
1474 s->data[0] = 0;
1475 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value);
1476 break;
1477 }
1478 }
1479
1480 static int m25p80_cs(SSIPeripheral *ss, bool select)
1481 {
1482 Flash *s = M25P80(ss);
1483
1484 if (select) {
1485 if (s->state == STATE_COLLECTING_VAR_LEN_DATA) {
1486 complete_collecting_data(s);
1487 }
1488 s->len = 0;
1489 s->pos = 0;
1490 s->state = STATE_IDLE;
1491 flash_sync_dirty(s, -1);
1492 s->data_read_loop = false;
1493 }
1494
1495 trace_m25p80_select(s, select ? "de" : "");
1496
1497 return 0;
1498 }
1499
1500 static uint32_t m25p80_transfer8(SSIPeripheral *ss, uint32_t tx)
1501 {
1502 Flash *s = M25P80(ss);
1503 uint32_t r = 0;
1504
1505 trace_m25p80_transfer(s, s->state, s->len, s->needed_bytes, s->pos,
1506 s->cur_addr, (uint8_t)tx);
1507
1508 switch (s->state) {
1509
1510 case STATE_PAGE_PROGRAM:
1511 trace_m25p80_page_program(s, s->cur_addr, (uint8_t)tx);
1512 flash_write8(s, s->cur_addr, (uint8_t)tx);
1513 s->cur_addr = (s->cur_addr + 1) & (s->size - 1);
1514
1515 if (get_man(s) == MAN_SST && s->aai_enable && s->cur_addr == 0) {
1516 /*
1517 * There is no wrap mode during AAI programming once the highest
1518 * unprotected memory address is reached. The Write-Enable-Latch
1519 * bit is automatically reset, and AAI programming mode aborts.
1520 */
1521 s->write_enable = false;
1522 s->aai_enable = false;
1523 }
1524
1525 break;
1526
1527 case STATE_READ:
1528 r = s->storage[s->cur_addr];
1529 trace_m25p80_read_byte(s, s->cur_addr, (uint8_t)r);
1530 s->cur_addr = (s->cur_addr + 1) & (s->size - 1);
1531 break;
1532
1533 case STATE_COLLECTING_DATA:
1534 case STATE_COLLECTING_VAR_LEN_DATA:
1535
1536 if (s->len >= M25P80_INTERNAL_DATA_BUFFER_SZ) {
1537 qemu_log_mask(LOG_GUEST_ERROR,
1538 "M25P80: Write overrun internal data buffer. "
1539 "SPI controller (QEMU emulator or guest driver) "
1540 "is misbehaving\n");
1541 s->len = s->pos = 0;
1542 s->state = STATE_IDLE;
1543 break;
1544 }
1545
1546 s->data[s->len] = (uint8_t)tx;
1547 s->len++;
1548
1549 if (s->len == s->needed_bytes) {
1550 complete_collecting_data(s);
1551 }
1552 break;
1553
1554 case STATE_READING_DATA:
1555
1556 if (s->pos >= M25P80_INTERNAL_DATA_BUFFER_SZ) {
1557 qemu_log_mask(LOG_GUEST_ERROR,
1558 "M25P80: Read overrun internal data buffer. "
1559 "SPI controller (QEMU emulator or guest driver) "
1560 "is misbehaving\n");
1561 s->len = s->pos = 0;
1562 s->state = STATE_IDLE;
1563 break;
1564 }
1565
1566 r = s->data[s->pos];
1567 trace_m25p80_read_data(s, s->pos, (uint8_t)r);
1568 s->pos++;
1569 if (s->pos == s->len) {
1570 s->pos = 0;
1571 if (!s->data_read_loop) {
1572 s->state = STATE_IDLE;
1573 }
1574 }
1575 break;
1576 case STATE_READING_SFDP:
1577 assert(s->pi->sfdp_read);
1578 r = s->pi->sfdp_read(s->cur_addr);
1579 trace_m25p80_read_sfdp(s, s->cur_addr, (uint8_t)r);
1580 s->cur_addr = (s->cur_addr + 1) & (M25P80_SFDP_MAX_SIZE - 1);
1581 break;
1582
1583 default:
1584 case STATE_IDLE:
1585 decode_new_cmd(s, (uint8_t)tx);
1586 break;
1587 }
1588
1589 return r;
1590 }
1591
1592 static void m25p80_write_protect_pin_irq_handler(void *opaque, int n, int level)
1593 {
1594 Flash *s = M25P80(opaque);
1595 /* WP# is just a single pin. */
1596 assert(n == 0);
1597 s->wp_level = !!level;
1598 }
1599
1600 static void m25p80_realize(SSIPeripheral *ss, Error **errp)
1601 {
1602 Flash *s = M25P80(ss);
1603 M25P80Class *mc = M25P80_GET_CLASS(s);
1604 int ret;
1605
1606 s->pi = mc->pi;
1607
1608 s->size = s->pi->sector_size * s->pi->n_sectors;
1609 s->dirty_page = -1;
1610
1611 if (s->blk) {
1612 uint64_t perm = BLK_PERM_CONSISTENT_READ |
1613 (blk_supports_write_perm(s->blk) ? BLK_PERM_WRITE : 0);
1614 ret = blk_set_perm(s->blk, perm, BLK_PERM_ALL, errp);
1615 if (ret < 0) {
1616 return;
1617 }
1618
1619 trace_m25p80_binding(s);
1620 s->storage = blk_blockalign(s->blk, s->size);
1621
1622 if (!blk_check_size_and_read_all(s->blk, DEVICE(s),
1623 s->storage, s->size, errp)) {
1624 return;
1625 }
1626 } else {
1627 trace_m25p80_binding_no_bdrv(s);
1628 s->storage = blk_blockalign(NULL, s->size);
1629 memset(s->storage, 0xFF, s->size);
1630 }
1631
1632 qdev_init_gpio_in_named(DEVICE(s),
1633 m25p80_write_protect_pin_irq_handler, "WP#", 1);
1634 }
1635
1636 static void m25p80_reset(DeviceState *d)
1637 {
1638 Flash *s = M25P80(d);
1639
1640 s->wp_level = true;
1641 s->status_register_write_disabled = false;
1642 s->block_protect0 = false;
1643 s->block_protect1 = false;
1644 s->block_protect2 = false;
1645 s->block_protect3 = false;
1646 s->top_bottom_bit = false;
1647
1648 reset_memory(s);
1649 }
1650
1651 static int m25p80_pre_save(void *opaque)
1652 {
1653 flash_sync_dirty((Flash *)opaque, -1);
1654
1655 return 0;
1656 }
1657
1658 static Property m25p80_properties[] = {
1659 /* This is default value for Micron flash */
1660 DEFINE_PROP_BOOL("write-enable", Flash, write_enable, false),
1661 DEFINE_PROP_UINT32("nonvolatile-cfg", Flash, nonvolatile_cfg, 0x8FFF),
1662 DEFINE_PROP_UINT8("spansion-cr1nv", Flash, spansion_cr1nv, 0x0),
1663 DEFINE_PROP_UINT8("spansion-cr2nv", Flash, spansion_cr2nv, 0x8),
1664 DEFINE_PROP_UINT8("spansion-cr3nv", Flash, spansion_cr3nv, 0x2),
1665 DEFINE_PROP_UINT8("spansion-cr4nv", Flash, spansion_cr4nv, 0x10),
1666 DEFINE_PROP_DRIVE("drive", Flash, blk),
1667 DEFINE_PROP_END_OF_LIST(),
1668 };
1669
1670 static int m25p80_pre_load(void *opaque)
1671 {
1672 Flash *s = (Flash *)opaque;
1673
1674 s->data_read_loop = false;
1675 return 0;
1676 }
1677
1678 static bool m25p80_data_read_loop_needed(void *opaque)
1679 {
1680 Flash *s = (Flash *)opaque;
1681
1682 return s->data_read_loop;
1683 }
1684
1685 static const VMStateDescription vmstate_m25p80_data_read_loop = {
1686 .name = "m25p80/data_read_loop",
1687 .version_id = 1,
1688 .minimum_version_id = 1,
1689 .needed = m25p80_data_read_loop_needed,
1690 .fields = (const VMStateField[]) {
1691 VMSTATE_BOOL(data_read_loop, Flash),
1692 VMSTATE_END_OF_LIST()
1693 }
1694 };
1695
1696 static bool m25p80_aai_enable_needed(void *opaque)
1697 {
1698 Flash *s = (Flash *)opaque;
1699
1700 return s->aai_enable;
1701 }
1702
1703 static const VMStateDescription vmstate_m25p80_aai_enable = {
1704 .name = "m25p80/aai_enable",
1705 .version_id = 1,
1706 .minimum_version_id = 1,
1707 .needed = m25p80_aai_enable_needed,
1708 .fields = (const VMStateField[]) {
1709 VMSTATE_BOOL(aai_enable, Flash),
1710 VMSTATE_END_OF_LIST()
1711 }
1712 };
1713
1714 static bool m25p80_wp_level_srwd_needed(void *opaque)
1715 {
1716 Flash *s = (Flash *)opaque;
1717
1718 return !s->wp_level || s->status_register_write_disabled;
1719 }
1720
1721 static const VMStateDescription vmstate_m25p80_write_protect = {
1722 .name = "m25p80/write_protect",
1723 .version_id = 1,
1724 .minimum_version_id = 1,
1725 .needed = m25p80_wp_level_srwd_needed,
1726 .fields = (const VMStateField[]) {
1727 VMSTATE_BOOL(wp_level, Flash),
1728 VMSTATE_BOOL(status_register_write_disabled, Flash),
1729 VMSTATE_END_OF_LIST()
1730 }
1731 };
1732
1733 static bool m25p80_block_protect_needed(void *opaque)
1734 {
1735 Flash *s = (Flash *)opaque;
1736
1737 return s->block_protect0 ||
1738 s->block_protect1 ||
1739 s->block_protect2 ||
1740 s->block_protect3 ||
1741 s->top_bottom_bit;
1742 }
1743
1744 static const VMStateDescription vmstate_m25p80_block_protect = {
1745 .name = "m25p80/block_protect",
1746 .version_id = 1,
1747 .minimum_version_id = 1,
1748 .needed = m25p80_block_protect_needed,
1749 .fields = (const VMStateField[]) {
1750 VMSTATE_BOOL(block_protect0, Flash),
1751 VMSTATE_BOOL(block_protect1, Flash),
1752 VMSTATE_BOOL(block_protect2, Flash),
1753 VMSTATE_BOOL(block_protect3, Flash),
1754 VMSTATE_BOOL(top_bottom_bit, Flash),
1755 VMSTATE_END_OF_LIST()
1756 }
1757 };
1758
1759 static const VMStateDescription vmstate_m25p80 = {
1760 .name = "m25p80",
1761 .version_id = 0,
1762 .minimum_version_id = 0,
1763 .pre_save = m25p80_pre_save,
1764 .pre_load = m25p80_pre_load,
1765 .fields = (const VMStateField[]) {
1766 VMSTATE_UINT8(state, Flash),
1767 VMSTATE_UINT8_ARRAY(data, Flash, M25P80_INTERNAL_DATA_BUFFER_SZ),
1768 VMSTATE_UINT32(len, Flash),
1769 VMSTATE_UINT32(pos, Flash),
1770 VMSTATE_UINT8(needed_bytes, Flash),
1771 VMSTATE_UINT8(cmd_in_progress, Flash),
1772 VMSTATE_UINT32(cur_addr, Flash),
1773 VMSTATE_BOOL(write_enable, Flash),
1774 VMSTATE_BOOL(reset_enable, Flash),
1775 VMSTATE_UINT8(ear, Flash),
1776 VMSTATE_BOOL(four_bytes_address_mode, Flash),
1777 VMSTATE_UINT32(nonvolatile_cfg, Flash),
1778 VMSTATE_UINT32(volatile_cfg, Flash),
1779 VMSTATE_UINT32(enh_volatile_cfg, Flash),
1780 VMSTATE_BOOL(quad_enable, Flash),
1781 VMSTATE_UINT8(spansion_cr1nv, Flash),
1782 VMSTATE_UINT8(spansion_cr2nv, Flash),
1783 VMSTATE_UINT8(spansion_cr3nv, Flash),
1784 VMSTATE_UINT8(spansion_cr4nv, Flash),
1785 VMSTATE_END_OF_LIST()
1786 },
1787 .subsections = (const VMStateDescription * const []) {
1788 &vmstate_m25p80_data_read_loop,
1789 &vmstate_m25p80_aai_enable,
1790 &vmstate_m25p80_write_protect,
1791 &vmstate_m25p80_block_protect,
1792 NULL
1793 }
1794 };
1795
1796 static void m25p80_class_init(ObjectClass *klass, void *data)
1797 {
1798 DeviceClass *dc = DEVICE_CLASS(klass);
1799 SSIPeripheralClass *k = SSI_PERIPHERAL_CLASS(klass);
1800 M25P80Class *mc = M25P80_CLASS(klass);
1801
1802 k->realize = m25p80_realize;
1803 k->transfer = m25p80_transfer8;
1804 k->set_cs = m25p80_cs;
1805 k->cs_polarity = SSI_CS_LOW;
1806 dc->vmsd = &vmstate_m25p80;
1807 device_class_set_props(dc, m25p80_properties);
1808 dc->reset = m25p80_reset;
1809 mc->pi = data;
1810 }
1811
1812 static const TypeInfo m25p80_info = {
1813 .name = TYPE_M25P80,
1814 .parent = TYPE_SSI_PERIPHERAL,
1815 .instance_size = sizeof(Flash),
1816 .class_size = sizeof(M25P80Class),
1817 .abstract = true,
1818 };
1819
1820 static void m25p80_register_types(void)
1821 {
1822 int i;
1823
1824 type_register_static(&m25p80_info);
1825 for (i = 0; i < ARRAY_SIZE(known_devices); ++i) {
1826 TypeInfo ti = {
1827 .name = known_devices[i].part_name,
1828 .parent = TYPE_M25P80,
1829 .class_init = m25p80_class_init,
1830 .class_data = (void *)&known_devices[i],
1831 };
1832 type_register(&ti);
1833 }
1834 }
1835
1836 type_init(m25p80_register_types)
1837
1838 BlockBackend *m25p80_get_blk(DeviceState *dev)
1839 {
1840 return M25P80(dev)->blk;
1841 }
AR7 emulation for QEMU