2 * ARM mach-virt emulation
4 * Copyright (c) 2013 Linaro Limited
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
18 * Emulate a virtual board which works by passing Linux all the information
19 * it needs about what devices are present via the device tree.
20 * There are some restrictions about what we can do here:
21 * + we can only present devices whose Linux drivers will work based
22 * purely on the device tree with no platform data at all
23 * + we want to present a very stripped-down minimalist platform,
24 * both because this reduces the security attack surface from the guest
25 * and also because it reduces our exposure to being broken when
26 * the kernel updates its device tree bindings and requires further
27 * information in a device binding that we aren't providing.
28 * This is essentially the same approach kvmtool uses.
31 #include "qemu/osdep.h"
32 #include "hw/sysbus.h"
33 #include "hw/arm/arm.h"
34 #include "hw/arm/primecell.h"
35 #include "hw/arm/virt.h"
36 #include "hw/devices.h"
38 #include "sysemu/block-backend.h"
39 #include "sysemu/device_tree.h"
40 #include "sysemu/sysemu.h"
41 #include "sysemu/kvm.h"
42 #include "hw/boards.h"
43 #include "hw/loader.h"
44 #include "exec/address-spaces.h"
45 #include "qemu/bitops.h"
46 #include "qemu/error-report.h"
47 #include "hw/pci-host/gpex.h"
48 #include "hw/arm/virt-acpi-build.h"
49 #include "hw/arm/sysbus-fdt.h"
50 #include "hw/platform-bus.h"
51 #include "hw/arm/fdt.h"
52 #include "hw/intc/arm_gic_common.h"
54 #include "hw/smbios/smbios.h"
55 #include "qapi/visitor.h"
56 #include "standard-headers/linux/input.h"
58 /* Number of external interrupt lines to configure the GIC with */
61 #define PLATFORM_BUS_NUM_IRQS 64
63 static ARMPlatformBusSystemParams platform_bus_params
;
65 typedef struct VirtBoardInfo
{
66 struct arm_boot_info bootinfo
;
67 const char *cpu_model
;
68 const MemMapEntry
*memmap
;
73 uint32_t clock_phandle
;
80 VirtBoardInfo
*daughterboard
;
90 #define TYPE_VIRT_MACHINE MACHINE_TYPE_NAME("virt")
91 #define VIRT_MACHINE(obj) \
92 OBJECT_CHECK(VirtMachineState, (obj), TYPE_VIRT_MACHINE)
93 #define VIRT_MACHINE_GET_CLASS(obj) \
94 OBJECT_GET_CLASS(VirtMachineClass, obj, TYPE_VIRT_MACHINE)
95 #define VIRT_MACHINE_CLASS(klass) \
96 OBJECT_CLASS_CHECK(VirtMachineClass, klass, TYPE_VIRT_MACHINE)
98 /* Addresses and sizes of our components.
99 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
100 * 128MB..256MB is used for miscellaneous device I/O.
101 * 256MB..1GB is reserved for possible future PCI support (ie where the
102 * PCI memory window will go if we add a PCI host controller).
103 * 1GB and up is RAM (which may happily spill over into the
104 * high memory region beyond 4GB).
105 * This represents a compromise between how much RAM can be given to
106 * a 32 bit VM and leaving space for expansion and in particular for PCI.
107 * Note that devices should generally be placed at multiples of 0x10000,
108 * to accommodate guests using 64K pages.
110 static const MemMapEntry a15memmap
[] = {
111 /* Space up to 0x8000000 is reserved for a boot ROM */
112 [VIRT_FLASH
] = { 0, 0x08000000 },
113 [VIRT_CPUPERIPHS
] = { 0x08000000, 0x00020000 },
114 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
115 [VIRT_GIC_DIST
] = { 0x08000000, 0x00010000 },
116 [VIRT_GIC_CPU
] = { 0x08010000, 0x00010000 },
117 [VIRT_GIC_V2M
] = { 0x08020000, 0x00001000 },
118 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */
119 [VIRT_GIC_ITS
] = { 0x08080000, 0x00020000 },
120 /* This redistributor space allows up to 2*64kB*123 CPUs */
121 [VIRT_GIC_REDIST
] = { 0x080A0000, 0x00F60000 },
122 [VIRT_UART
] = { 0x09000000, 0x00001000 },
123 [VIRT_RTC
] = { 0x09010000, 0x00001000 },
124 [VIRT_FW_CFG
] = { 0x09020000, 0x00000018 },
125 [VIRT_GPIO
] = { 0x09030000, 0x00001000 },
126 [VIRT_MMIO
] = { 0x0a000000, 0x00000200 },
127 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
128 [VIRT_PLATFORM_BUS
] = { 0x0c000000, 0x02000000 },
129 [VIRT_PCIE_MMIO
] = { 0x10000000, 0x2eff0000 },
130 [VIRT_PCIE_PIO
] = { 0x3eff0000, 0x00010000 },
131 [VIRT_PCIE_ECAM
] = { 0x3f000000, 0x01000000 },
132 [VIRT_MEM
] = { 0x40000000, 30ULL * 1024 * 1024 * 1024 },
133 /* Second PCIe window, 512GB wide at the 512GB boundary */
134 [VIRT_PCIE_MMIO_HIGH
] = { 0x8000000000ULL
, 0x8000000000ULL
},
137 static const int a15irqmap
[] = {
140 [VIRT_PCIE
] = 3, /* ... to 6 */
142 [VIRT_MMIO
] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
143 [VIRT_GIC_V2M
] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
144 [VIRT_PLATFORM_BUS
] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
147 static VirtBoardInfo machines
[] = {
149 .cpu_model
= "cortex-a15",
154 .cpu_model
= "cortex-a53",
159 .cpu_model
= "cortex-a57",
170 static VirtBoardInfo
*find_machine_info(const char *cpu
)
174 for (i
= 0; i
< ARRAY_SIZE(machines
); i
++) {
175 if (strcmp(cpu
, machines
[i
].cpu_model
) == 0) {
182 static void create_fdt(VirtBoardInfo
*vbi
)
184 void *fdt
= create_device_tree(&vbi
->fdt_size
);
187 error_report("create_device_tree() failed");
194 qemu_fdt_setprop_string(fdt
, "/", "compatible", "linux,dummy-virt");
195 qemu_fdt_setprop_cell(fdt
, "/", "#address-cells", 0x2);
196 qemu_fdt_setprop_cell(fdt
, "/", "#size-cells", 0x2);
199 * /chosen and /memory nodes must exist for load_dtb
200 * to fill in necessary properties later
202 qemu_fdt_add_subnode(fdt
, "/chosen");
203 qemu_fdt_add_subnode(fdt
, "/memory");
204 qemu_fdt_setprop_string(fdt
, "/memory", "device_type", "memory");
206 /* Clock node, for the benefit of the UART. The kernel device tree
207 * binding documentation claims the PL011 node clock properties are
208 * optional but in practice if you omit them the kernel refuses to
209 * probe for the device.
211 vbi
->clock_phandle
= qemu_fdt_alloc_phandle(fdt
);
212 qemu_fdt_add_subnode(fdt
, "/apb-pclk");
213 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "compatible", "fixed-clock");
214 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "#clock-cells", 0x0);
215 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "clock-frequency", 24000000);
216 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "clock-output-names",
218 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "phandle", vbi
->clock_phandle
);
222 static void fdt_add_psci_node(const VirtBoardInfo
*vbi
)
224 uint32_t cpu_suspend_fn
;
228 void *fdt
= vbi
->fdt
;
229 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(0));
231 qemu_fdt_add_subnode(fdt
, "/psci");
232 if (armcpu
->psci_version
== 2) {
233 const char comp
[] = "arm,psci-0.2\0arm,psci";
234 qemu_fdt_setprop(fdt
, "/psci", "compatible", comp
, sizeof(comp
));
236 cpu_off_fn
= QEMU_PSCI_0_2_FN_CPU_OFF
;
237 if (arm_feature(&armcpu
->env
, ARM_FEATURE_AARCH64
)) {
238 cpu_suspend_fn
= QEMU_PSCI_0_2_FN64_CPU_SUSPEND
;
239 cpu_on_fn
= QEMU_PSCI_0_2_FN64_CPU_ON
;
240 migrate_fn
= QEMU_PSCI_0_2_FN64_MIGRATE
;
242 cpu_suspend_fn
= QEMU_PSCI_0_2_FN_CPU_SUSPEND
;
243 cpu_on_fn
= QEMU_PSCI_0_2_FN_CPU_ON
;
244 migrate_fn
= QEMU_PSCI_0_2_FN_MIGRATE
;
247 qemu_fdt_setprop_string(fdt
, "/psci", "compatible", "arm,psci");
249 cpu_suspend_fn
= QEMU_PSCI_0_1_FN_CPU_SUSPEND
;
250 cpu_off_fn
= QEMU_PSCI_0_1_FN_CPU_OFF
;
251 cpu_on_fn
= QEMU_PSCI_0_1_FN_CPU_ON
;
252 migrate_fn
= QEMU_PSCI_0_1_FN_MIGRATE
;
255 /* We adopt the PSCI spec's nomenclature, and use 'conduit' to refer
256 * to the instruction that should be used to invoke PSCI functions.
257 * However, the device tree binding uses 'method' instead, so that is
258 * what we should use here.
260 qemu_fdt_setprop_string(fdt
, "/psci", "method", "hvc");
262 qemu_fdt_setprop_cell(fdt
, "/psci", "cpu_suspend", cpu_suspend_fn
);
263 qemu_fdt_setprop_cell(fdt
, "/psci", "cpu_off", cpu_off_fn
);
264 qemu_fdt_setprop_cell(fdt
, "/psci", "cpu_on", cpu_on_fn
);
265 qemu_fdt_setprop_cell(fdt
, "/psci", "migrate", migrate_fn
);
268 static void fdt_add_timer_nodes(const VirtBoardInfo
*vbi
, int gictype
)
270 /* Note that on A15 h/w these interrupts are level-triggered,
271 * but for the GIC implementation provided by both QEMU and KVM
272 * they are edge-triggered.
275 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
;
278 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
279 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
280 (1 << vbi
->smp_cpus
) - 1);
283 qemu_fdt_add_subnode(vbi
->fdt
, "/timer");
285 armcpu
= ARM_CPU(qemu_get_cpu(0));
286 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
287 const char compat
[] = "arm,armv8-timer\0arm,armv7-timer";
288 qemu_fdt_setprop(vbi
->fdt
, "/timer", "compatible",
289 compat
, sizeof(compat
));
291 qemu_fdt_setprop_string(vbi
->fdt
, "/timer", "compatible",
294 qemu_fdt_setprop_cells(vbi
->fdt
, "/timer", "interrupts",
295 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_S_EL1_IRQ
, irqflags
,
296 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_NS_EL1_IRQ
, irqflags
,
297 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_VIRT_IRQ
, irqflags
,
298 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_NS_EL2_IRQ
, irqflags
);
301 static void fdt_add_cpu_nodes(const VirtBoardInfo
*vbi
)
307 * From Documentation/devicetree/bindings/arm/cpus.txt
308 * On ARM v8 64-bit systems value should be set to 2,
309 * that corresponds to the MPIDR_EL1 register size.
310 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
311 * in the system, #address-cells can be set to 1, since
312 * MPIDR_EL1[63:32] bits are not used for CPUs
315 * Here we actually don't know whether our system is 32- or 64-bit one.
316 * The simplest way to go is to examine affinity IDs of all our CPUs. If
317 * at least one of them has Aff3 populated, we set #address-cells to 2.
319 for (cpu
= 0; cpu
< vbi
->smp_cpus
; cpu
++) {
320 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
322 if (armcpu
->mp_affinity
& ARM_AFF3_MASK
) {
328 qemu_fdt_add_subnode(vbi
->fdt
, "/cpus");
329 qemu_fdt_setprop_cell(vbi
->fdt
, "/cpus", "#address-cells", addr_cells
);
330 qemu_fdt_setprop_cell(vbi
->fdt
, "/cpus", "#size-cells", 0x0);
332 for (cpu
= vbi
->smp_cpus
- 1; cpu
>= 0; cpu
--) {
333 char *nodename
= g_strdup_printf("/cpus/cpu@%d", cpu
);
334 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
336 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
337 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "device_type", "cpu");
338 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "compatible",
339 armcpu
->dtb_compatible
);
341 if (vbi
->smp_cpus
> 1) {
342 qemu_fdt_setprop_string(vbi
->fdt
, nodename
,
343 "enable-method", "psci");
346 if (addr_cells
== 2) {
347 qemu_fdt_setprop_u64(vbi
->fdt
, nodename
, "reg",
348 armcpu
->mp_affinity
);
350 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "reg",
351 armcpu
->mp_affinity
);
358 static void fdt_add_v2m_gic_node(VirtBoardInfo
*vbi
)
360 vbi
->v2m_phandle
= qemu_fdt_alloc_phandle(vbi
->fdt
);
361 qemu_fdt_add_subnode(vbi
->fdt
, "/intc/v2m");
362 qemu_fdt_setprop_string(vbi
->fdt
, "/intc/v2m", "compatible",
363 "arm,gic-v2m-frame");
364 qemu_fdt_setprop(vbi
->fdt
, "/intc/v2m", "msi-controller", NULL
, 0);
365 qemu_fdt_setprop_sized_cells(vbi
->fdt
, "/intc/v2m", "reg",
366 2, vbi
->memmap
[VIRT_GIC_V2M
].base
,
367 2, vbi
->memmap
[VIRT_GIC_V2M
].size
);
368 qemu_fdt_setprop_cell(vbi
->fdt
, "/intc/v2m", "phandle", vbi
->v2m_phandle
);
371 static void fdt_add_gic_node(VirtBoardInfo
*vbi
, int type
)
373 vbi
->gic_phandle
= qemu_fdt_alloc_phandle(vbi
->fdt
);
374 qemu_fdt_setprop_cell(vbi
->fdt
, "/", "interrupt-parent", vbi
->gic_phandle
);
376 qemu_fdt_add_subnode(vbi
->fdt
, "/intc");
377 qemu_fdt_setprop_cell(vbi
->fdt
, "/intc", "#interrupt-cells", 3);
378 qemu_fdt_setprop(vbi
->fdt
, "/intc", "interrupt-controller", NULL
, 0);
379 qemu_fdt_setprop_cell(vbi
->fdt
, "/intc", "#address-cells", 0x2);
380 qemu_fdt_setprop_cell(vbi
->fdt
, "/intc", "#size-cells", 0x2);
381 qemu_fdt_setprop(vbi
->fdt
, "/intc", "ranges", NULL
, 0);
383 qemu_fdt_setprop_string(vbi
->fdt
, "/intc", "compatible",
385 qemu_fdt_setprop_sized_cells(vbi
->fdt
, "/intc", "reg",
386 2, vbi
->memmap
[VIRT_GIC_DIST
].base
,
387 2, vbi
->memmap
[VIRT_GIC_DIST
].size
,
388 2, vbi
->memmap
[VIRT_GIC_REDIST
].base
,
389 2, vbi
->memmap
[VIRT_GIC_REDIST
].size
);
391 /* 'cortex-a15-gic' means 'GIC v2' */
392 qemu_fdt_setprop_string(vbi
->fdt
, "/intc", "compatible",
393 "arm,cortex-a15-gic");
394 qemu_fdt_setprop_sized_cells(vbi
->fdt
, "/intc", "reg",
395 2, vbi
->memmap
[VIRT_GIC_DIST
].base
,
396 2, vbi
->memmap
[VIRT_GIC_DIST
].size
,
397 2, vbi
->memmap
[VIRT_GIC_CPU
].base
,
398 2, vbi
->memmap
[VIRT_GIC_CPU
].size
);
401 qemu_fdt_setprop_cell(vbi
->fdt
, "/intc", "phandle", vbi
->gic_phandle
);
404 static void create_v2m(VirtBoardInfo
*vbi
, qemu_irq
*pic
)
407 int irq
= vbi
->irqmap
[VIRT_GIC_V2M
];
410 dev
= qdev_create(NULL
, "arm-gicv2m");
411 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vbi
->memmap
[VIRT_GIC_V2M
].base
);
412 qdev_prop_set_uint32(dev
, "base-spi", irq
);
413 qdev_prop_set_uint32(dev
, "num-spi", NUM_GICV2M_SPIS
);
414 qdev_init_nofail(dev
);
416 for (i
= 0; i
< NUM_GICV2M_SPIS
; i
++) {
417 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
, pic
[irq
+ i
]);
420 fdt_add_v2m_gic_node(vbi
);
423 static void create_gic(VirtBoardInfo
*vbi
, qemu_irq
*pic
, int type
, bool secure
)
425 /* We create a standalone GIC */
427 SysBusDevice
*gicbusdev
;
431 gictype
= (type
== 3) ? gicv3_class_name() : gic_class_name();
433 gicdev
= qdev_create(NULL
, gictype
);
434 qdev_prop_set_uint32(gicdev
, "revision", type
);
435 qdev_prop_set_uint32(gicdev
, "num-cpu", smp_cpus
);
436 /* Note that the num-irq property counts both internal and external
437 * interrupts; there are always 32 of the former (mandated by GIC spec).
439 qdev_prop_set_uint32(gicdev
, "num-irq", NUM_IRQS
+ 32);
440 if (!kvm_irqchip_in_kernel()) {
441 qdev_prop_set_bit(gicdev
, "has-security-extensions", secure
);
443 qdev_init_nofail(gicdev
);
444 gicbusdev
= SYS_BUS_DEVICE(gicdev
);
445 sysbus_mmio_map(gicbusdev
, 0, vbi
->memmap
[VIRT_GIC_DIST
].base
);
447 sysbus_mmio_map(gicbusdev
, 1, vbi
->memmap
[VIRT_GIC_REDIST
].base
);
449 sysbus_mmio_map(gicbusdev
, 1, vbi
->memmap
[VIRT_GIC_CPU
].base
);
452 /* Wire the outputs from each CPU's generic timer to the
453 * appropriate GIC PPI inputs, and the GIC's IRQ output to
454 * the CPU's IRQ input.
456 for (i
= 0; i
< smp_cpus
; i
++) {
457 DeviceState
*cpudev
= DEVICE(qemu_get_cpu(i
));
458 int ppibase
= NUM_IRQS
+ i
* GIC_INTERNAL
+ GIC_NR_SGIS
;
460 /* Mapping from the output timer irq lines from the CPU to the
461 * GIC PPI inputs we use for the virt board.
463 const int timer_irq
[] = {
464 [GTIMER_PHYS
] = ARCH_TIMER_NS_EL1_IRQ
,
465 [GTIMER_VIRT
] = ARCH_TIMER_VIRT_IRQ
,
466 [GTIMER_HYP
] = ARCH_TIMER_NS_EL2_IRQ
,
467 [GTIMER_SEC
] = ARCH_TIMER_S_EL1_IRQ
,
470 for (irq
= 0; irq
< ARRAY_SIZE(timer_irq
); irq
++) {
471 qdev_connect_gpio_out(cpudev
, irq
,
472 qdev_get_gpio_in(gicdev
,
473 ppibase
+ timer_irq
[irq
]));
476 sysbus_connect_irq(gicbusdev
, i
, qdev_get_gpio_in(cpudev
, ARM_CPU_IRQ
));
477 sysbus_connect_irq(gicbusdev
, i
+ smp_cpus
,
478 qdev_get_gpio_in(cpudev
, ARM_CPU_FIQ
));
481 for (i
= 0; i
< NUM_IRQS
; i
++) {
482 pic
[i
] = qdev_get_gpio_in(gicdev
, i
);
485 fdt_add_gic_node(vbi
, type
);
488 create_v2m(vbi
, pic
);
492 static void create_uart(const VirtBoardInfo
*vbi
, qemu_irq
*pic
)
495 hwaddr base
= vbi
->memmap
[VIRT_UART
].base
;
496 hwaddr size
= vbi
->memmap
[VIRT_UART
].size
;
497 int irq
= vbi
->irqmap
[VIRT_UART
];
498 const char compat
[] = "arm,pl011\0arm,primecell";
499 const char clocknames
[] = "uartclk\0apb_pclk";
501 sysbus_create_simple("pl011", base
, pic
[irq
]);
503 nodename
= g_strdup_printf("/pl011@%" PRIx64
, base
);
504 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
505 /* Note that we can't use setprop_string because of the embedded NUL */
506 qemu_fdt_setprop(vbi
->fdt
, nodename
, "compatible",
507 compat
, sizeof(compat
));
508 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
510 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "interrupts",
511 GIC_FDT_IRQ_TYPE_SPI
, irq
,
512 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
513 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "clocks",
514 vbi
->clock_phandle
, vbi
->clock_phandle
);
515 qemu_fdt_setprop(vbi
->fdt
, nodename
, "clock-names",
516 clocknames
, sizeof(clocknames
));
518 qemu_fdt_setprop_string(vbi
->fdt
, "/chosen", "stdout-path", nodename
);
522 static void create_rtc(const VirtBoardInfo
*vbi
, qemu_irq
*pic
)
525 hwaddr base
= vbi
->memmap
[VIRT_RTC
].base
;
526 hwaddr size
= vbi
->memmap
[VIRT_RTC
].size
;
527 int irq
= vbi
->irqmap
[VIRT_RTC
];
528 const char compat
[] = "arm,pl031\0arm,primecell";
530 sysbus_create_simple("pl031", base
, pic
[irq
]);
532 nodename
= g_strdup_printf("/pl031@%" PRIx64
, base
);
533 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
534 qemu_fdt_setprop(vbi
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
535 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
537 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "interrupts",
538 GIC_FDT_IRQ_TYPE_SPI
, irq
,
539 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
540 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "clocks", vbi
->clock_phandle
);
541 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "clock-names", "apb_pclk");
545 static DeviceState
*pl061_dev
;
546 static void virt_powerdown_req(Notifier
*n
, void *opaque
)
548 /* use gpio Pin 3 for power button event */
549 qemu_set_irq(qdev_get_gpio_in(pl061_dev
, 3), 1);
552 static Notifier virt_system_powerdown_notifier
= {
553 .notify
= virt_powerdown_req
556 static void create_gpio(const VirtBoardInfo
*vbi
, qemu_irq
*pic
)
559 hwaddr base
= vbi
->memmap
[VIRT_GPIO
].base
;
560 hwaddr size
= vbi
->memmap
[VIRT_GPIO
].size
;
561 int irq
= vbi
->irqmap
[VIRT_GPIO
];
562 const char compat
[] = "arm,pl061\0arm,primecell";
564 pl061_dev
= sysbus_create_simple("pl061", base
, pic
[irq
]);
566 uint32_t phandle
= qemu_fdt_alloc_phandle(vbi
->fdt
);
567 nodename
= g_strdup_printf("/pl061@%" PRIx64
, base
);
568 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
569 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
571 qemu_fdt_setprop(vbi
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
572 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "#gpio-cells", 2);
573 qemu_fdt_setprop(vbi
->fdt
, nodename
, "gpio-controller", NULL
, 0);
574 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "interrupts",
575 GIC_FDT_IRQ_TYPE_SPI
, irq
,
576 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
577 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "clocks", vbi
->clock_phandle
);
578 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "clock-names", "apb_pclk");
579 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "phandle", phandle
);
581 qemu_fdt_add_subnode(vbi
->fdt
, "/gpio-keys");
582 qemu_fdt_setprop_string(vbi
->fdt
, "/gpio-keys", "compatible", "gpio-keys");
583 qemu_fdt_setprop_cell(vbi
->fdt
, "/gpio-keys", "#size-cells", 0);
584 qemu_fdt_setprop_cell(vbi
->fdt
, "/gpio-keys", "#address-cells", 1);
586 qemu_fdt_add_subnode(vbi
->fdt
, "/gpio-keys/poweroff");
587 qemu_fdt_setprop_string(vbi
->fdt
, "/gpio-keys/poweroff",
588 "label", "GPIO Key Poweroff");
589 qemu_fdt_setprop_cell(vbi
->fdt
, "/gpio-keys/poweroff", "linux,code",
591 qemu_fdt_setprop_cells(vbi
->fdt
, "/gpio-keys/poweroff",
592 "gpios", phandle
, 3, 0);
594 /* connect powerdown request */
595 qemu_register_powerdown_notifier(&virt_system_powerdown_notifier
);
600 static void create_virtio_devices(const VirtBoardInfo
*vbi
, qemu_irq
*pic
)
603 hwaddr size
= vbi
->memmap
[VIRT_MMIO
].size
;
605 /* We create the transports in forwards order. Since qbus_realize()
606 * prepends (not appends) new child buses, the incrementing loop below will
607 * create a list of virtio-mmio buses with decreasing base addresses.
609 * When a -device option is processed from the command line,
610 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards
611 * order. The upshot is that -device options in increasing command line
612 * order are mapped to virtio-mmio buses with decreasing base addresses.
614 * When this code was originally written, that arrangement ensured that the
615 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to
616 * the first -device on the command line. (The end-to-end order is a
617 * function of this loop, qbus_realize(), qbus_find_recursive(), and the
618 * guest kernel's name-to-address assignment strategy.)
620 * Meanwhile, the kernel's traversal seems to have been reversed; see eg.
621 * the message, if not necessarily the code, of commit 70161ff336.
622 * Therefore the loop now establishes the inverse of the original intent.
624 * Unfortunately, we can't counteract the kernel change by reversing the
625 * loop; it would break existing command lines.
627 * In any case, the kernel makes no guarantee about the stability of
628 * enumeration order of virtio devices (as demonstrated by it changing
629 * between kernel versions). For reliable and stable identification
630 * of disks users must use UUIDs or similar mechanisms.
632 for (i
= 0; i
< NUM_VIRTIO_TRANSPORTS
; i
++) {
633 int irq
= vbi
->irqmap
[VIRT_MMIO
] + i
;
634 hwaddr base
= vbi
->memmap
[VIRT_MMIO
].base
+ i
* size
;
636 sysbus_create_simple("virtio-mmio", base
, pic
[irq
]);
639 /* We add dtb nodes in reverse order so that they appear in the finished
640 * device tree lowest address first.
642 * Note that this mapping is independent of the loop above. The previous
643 * loop influences virtio device to virtio transport assignment, whereas
644 * this loop controls how virtio transports are laid out in the dtb.
646 for (i
= NUM_VIRTIO_TRANSPORTS
- 1; i
>= 0; i
--) {
648 int irq
= vbi
->irqmap
[VIRT_MMIO
] + i
;
649 hwaddr base
= vbi
->memmap
[VIRT_MMIO
].base
+ i
* size
;
651 nodename
= g_strdup_printf("/virtio_mmio@%" PRIx64
, base
);
652 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
653 qemu_fdt_setprop_string(vbi
->fdt
, nodename
,
654 "compatible", "virtio,mmio");
655 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
657 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "interrupts",
658 GIC_FDT_IRQ_TYPE_SPI
, irq
,
659 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
);
664 static void create_one_flash(const char *name
, hwaddr flashbase
,
667 /* Create and map a single flash device. We use the same
668 * parameters as the flash devices on the Versatile Express board.
670 DriveInfo
*dinfo
= drive_get_next(IF_PFLASH
);
671 DeviceState
*dev
= qdev_create(NULL
, "cfi.pflash01");
672 const uint64_t sectorlength
= 256 * 1024;
675 qdev_prop_set_drive(dev
, "drive", blk_by_legacy_dinfo(dinfo
),
679 qdev_prop_set_uint32(dev
, "num-blocks", flashsize
/ sectorlength
);
680 qdev_prop_set_uint64(dev
, "sector-length", sectorlength
);
681 qdev_prop_set_uint8(dev
, "width", 4);
682 qdev_prop_set_uint8(dev
, "device-width", 2);
683 qdev_prop_set_bit(dev
, "big-endian", false);
684 qdev_prop_set_uint16(dev
, "id0", 0x89);
685 qdev_prop_set_uint16(dev
, "id1", 0x18);
686 qdev_prop_set_uint16(dev
, "id2", 0x00);
687 qdev_prop_set_uint16(dev
, "id3", 0x00);
688 qdev_prop_set_string(dev
, "name", name
);
689 qdev_init_nofail(dev
);
691 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, flashbase
);
694 static void create_flash(const VirtBoardInfo
*vbi
)
696 /* Create two flash devices to fill the VIRT_FLASH space in the memmap.
697 * Any file passed via -bios goes in the first of these.
699 hwaddr flashsize
= vbi
->memmap
[VIRT_FLASH
].size
/ 2;
700 hwaddr flashbase
= vbi
->memmap
[VIRT_FLASH
].base
;
707 if (drive_get(IF_PFLASH
, 0, 0)) {
708 error_report("The contents of the first flash device may be "
709 "specified with -bios or with -drive if=pflash... "
710 "but you cannot use both options at once");
713 fn
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
715 error_report("Could not find ROM image '%s'", bios_name
);
718 image_size
= load_image_targphys(fn
, flashbase
, flashsize
);
720 if (image_size
< 0) {
721 error_report("Could not load ROM image '%s'", bios_name
);
726 create_one_flash("virt.flash0", flashbase
, flashsize
);
727 create_one_flash("virt.flash1", flashbase
+ flashsize
, flashsize
);
729 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
730 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
731 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "compatible", "cfi-flash");
732 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
733 2, flashbase
, 2, flashsize
,
734 2, flashbase
+ flashsize
, 2, flashsize
);
735 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "bank-width", 4);
739 static void create_fw_cfg(const VirtBoardInfo
*vbi
, AddressSpace
*as
)
741 hwaddr base
= vbi
->memmap
[VIRT_FW_CFG
].base
;
742 hwaddr size
= vbi
->memmap
[VIRT_FW_CFG
].size
;
745 fw_cfg_init_mem_wide(base
+ 8, base
, 8, base
+ 16, as
);
747 nodename
= g_strdup_printf("/fw-cfg@%" PRIx64
, base
);
748 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
749 qemu_fdt_setprop_string(vbi
->fdt
, nodename
,
750 "compatible", "qemu,fw-cfg-mmio");
751 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
756 static void create_pcie_irq_map(const VirtBoardInfo
*vbi
, uint32_t gic_phandle
,
757 int first_irq
, const char *nodename
)
760 uint32_t full_irq_map
[4 * 4 * 10] = { 0 };
761 uint32_t *irq_map
= full_irq_map
;
763 for (devfn
= 0; devfn
<= 0x18; devfn
+= 0x8) {
764 for (pin
= 0; pin
< 4; pin
++) {
765 int irq_type
= GIC_FDT_IRQ_TYPE_SPI
;
766 int irq_nr
= first_irq
+ ((pin
+ PCI_SLOT(devfn
)) % PCI_NUM_PINS
);
767 int irq_level
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
771 devfn
<< 8, 0, 0, /* devfn */
772 pin
+ 1, /* PCI pin */
773 gic_phandle
, 0, 0, irq_type
, irq_nr
, irq_level
}; /* GIC irq */
775 /* Convert map to big endian */
776 for (i
= 0; i
< 10; i
++) {
777 irq_map
[i
] = cpu_to_be32(map
[i
]);
783 qemu_fdt_setprop(vbi
->fdt
, nodename
, "interrupt-map",
784 full_irq_map
, sizeof(full_irq_map
));
786 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "interrupt-map-mask",
787 0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */
791 static void create_pcie(const VirtBoardInfo
*vbi
, qemu_irq
*pic
,
794 hwaddr base_mmio
= vbi
->memmap
[VIRT_PCIE_MMIO
].base
;
795 hwaddr size_mmio
= vbi
->memmap
[VIRT_PCIE_MMIO
].size
;
796 hwaddr base_mmio_high
= vbi
->memmap
[VIRT_PCIE_MMIO_HIGH
].base
;
797 hwaddr size_mmio_high
= vbi
->memmap
[VIRT_PCIE_MMIO_HIGH
].size
;
798 hwaddr base_pio
= vbi
->memmap
[VIRT_PCIE_PIO
].base
;
799 hwaddr size_pio
= vbi
->memmap
[VIRT_PCIE_PIO
].size
;
800 hwaddr base_ecam
= vbi
->memmap
[VIRT_PCIE_ECAM
].base
;
801 hwaddr size_ecam
= vbi
->memmap
[VIRT_PCIE_ECAM
].size
;
802 hwaddr base
= base_mmio
;
803 int nr_pcie_buses
= size_ecam
/ PCIE_MMCFG_SIZE_MIN
;
804 int irq
= vbi
->irqmap
[VIRT_PCIE
];
805 MemoryRegion
*mmio_alias
;
806 MemoryRegion
*mmio_reg
;
807 MemoryRegion
*ecam_alias
;
808 MemoryRegion
*ecam_reg
;
814 dev
= qdev_create(NULL
, TYPE_GPEX_HOST
);
815 qdev_init_nofail(dev
);
817 /* Map only the first size_ecam bytes of ECAM space */
818 ecam_alias
= g_new0(MemoryRegion
, 1);
819 ecam_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0);
820 memory_region_init_alias(ecam_alias
, OBJECT(dev
), "pcie-ecam",
821 ecam_reg
, 0, size_ecam
);
822 memory_region_add_subregion(get_system_memory(), base_ecam
, ecam_alias
);
824 /* Map the MMIO window into system address space so as to expose
825 * the section of PCI MMIO space which starts at the same base address
826 * (ie 1:1 mapping for that part of PCI MMIO space visible through
829 mmio_alias
= g_new0(MemoryRegion
, 1);
830 mmio_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 1);
831 memory_region_init_alias(mmio_alias
, OBJECT(dev
), "pcie-mmio",
832 mmio_reg
, base_mmio
, size_mmio
);
833 memory_region_add_subregion(get_system_memory(), base_mmio
, mmio_alias
);
836 /* Map high MMIO space */
837 MemoryRegion
*high_mmio_alias
= g_new0(MemoryRegion
, 1);
839 memory_region_init_alias(high_mmio_alias
, OBJECT(dev
), "pcie-mmio-high",
840 mmio_reg
, base_mmio_high
, size_mmio_high
);
841 memory_region_add_subregion(get_system_memory(), base_mmio_high
,
845 /* Map IO port space */
846 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 2, base_pio
);
848 for (i
= 0; i
< GPEX_NUM_IRQS
; i
++) {
849 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
, pic
[irq
+ i
]);
852 pci
= PCI_HOST_BRIDGE(dev
);
854 for (i
= 0; i
< nb_nics
; i
++) {
855 NICInfo
*nd
= &nd_table
[i
];
858 nd
->model
= g_strdup("virtio");
861 pci_nic_init_nofail(nd
, pci
->bus
, nd
->model
, NULL
);
865 nodename
= g_strdup_printf("/pcie@%" PRIx64
, base
);
866 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
867 qemu_fdt_setprop_string(vbi
->fdt
, nodename
,
868 "compatible", "pci-host-ecam-generic");
869 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "device_type", "pci");
870 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "#address-cells", 3);
871 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "#size-cells", 2);
872 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "bus-range", 0,
875 if (vbi
->v2m_phandle
) {
876 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "msi-parent",
880 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
881 2, base_ecam
, 2, size_ecam
);
884 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "ranges",
885 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
886 2, base_pio
, 2, size_pio
,
887 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
888 2, base_mmio
, 2, size_mmio
,
889 1, FDT_PCI_RANGE_MMIO_64BIT
,
891 2, base_mmio_high
, 2, size_mmio_high
);
893 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "ranges",
894 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
895 2, base_pio
, 2, size_pio
,
896 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
897 2, base_mmio
, 2, size_mmio
);
900 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "#interrupt-cells", 1);
901 create_pcie_irq_map(vbi
, vbi
->gic_phandle
, irq
, nodename
);
906 static void create_platform_bus(VirtBoardInfo
*vbi
, qemu_irq
*pic
)
911 ARMPlatformBusFDTParams
*fdt_params
= g_new(ARMPlatformBusFDTParams
, 1);
912 MemoryRegion
*sysmem
= get_system_memory();
914 platform_bus_params
.platform_bus_base
= vbi
->memmap
[VIRT_PLATFORM_BUS
].base
;
915 platform_bus_params
.platform_bus_size
= vbi
->memmap
[VIRT_PLATFORM_BUS
].size
;
916 platform_bus_params
.platform_bus_first_irq
= vbi
->irqmap
[VIRT_PLATFORM_BUS
];
917 platform_bus_params
.platform_bus_num_irqs
= PLATFORM_BUS_NUM_IRQS
;
919 fdt_params
->system_params
= &platform_bus_params
;
920 fdt_params
->binfo
= &vbi
->bootinfo
;
921 fdt_params
->intc
= "/intc";
923 * register a machine init done notifier that creates the device tree
924 * nodes of the platform bus and its children dynamic sysbus devices
926 arm_register_platform_bus_fdt_creator(fdt_params
);
928 dev
= qdev_create(NULL
, TYPE_PLATFORM_BUS_DEVICE
);
929 dev
->id
= TYPE_PLATFORM_BUS_DEVICE
;
930 qdev_prop_set_uint32(dev
, "num_irqs",
931 platform_bus_params
.platform_bus_num_irqs
);
932 qdev_prop_set_uint32(dev
, "mmio_size",
933 platform_bus_params
.platform_bus_size
);
934 qdev_init_nofail(dev
);
935 s
= SYS_BUS_DEVICE(dev
);
937 for (i
= 0; i
< platform_bus_params
.platform_bus_num_irqs
; i
++) {
938 int irqn
= platform_bus_params
.platform_bus_first_irq
+ i
;
939 sysbus_connect_irq(s
, i
, pic
[irqn
]);
942 memory_region_add_subregion(sysmem
,
943 platform_bus_params
.platform_bus_base
,
944 sysbus_mmio_get_region(s
, 0));
947 static void *machvirt_dtb(const struct arm_boot_info
*binfo
, int *fdt_size
)
949 const VirtBoardInfo
*board
= (const VirtBoardInfo
*)binfo
;
951 *fdt_size
= board
->fdt_size
;
955 static void virt_build_smbios(VirtGuestInfo
*guest_info
)
957 FWCfgState
*fw_cfg
= guest_info
->fw_cfg
;
958 uint8_t *smbios_tables
, *smbios_anchor
;
959 size_t smbios_tables_len
, smbios_anchor_len
;
960 const char *product
= "QEMU Virtual Machine";
967 product
= "KVM Virtual Machine";
970 smbios_set_defaults("QEMU", product
,
971 "1.0", false, true, SMBIOS_ENTRY_POINT_30
);
973 smbios_get_tables(NULL
, 0, &smbios_tables
, &smbios_tables_len
,
974 &smbios_anchor
, &smbios_anchor_len
);
977 fw_cfg_add_file(fw_cfg
, "etc/smbios/smbios-tables",
978 smbios_tables
, smbios_tables_len
);
979 fw_cfg_add_file(fw_cfg
, "etc/smbios/smbios-anchor",
980 smbios_anchor
, smbios_anchor_len
);
985 void virt_guest_info_machine_done(Notifier
*notifier
, void *data
)
987 VirtGuestInfoState
*guest_info_state
= container_of(notifier
,
988 VirtGuestInfoState
, machine_done
);
989 virt_acpi_setup(&guest_info_state
->info
);
990 virt_build_smbios(&guest_info_state
->info
);
993 static void machvirt_init(MachineState
*machine
)
995 VirtMachineState
*vms
= VIRT_MACHINE(machine
);
996 qemu_irq pic
[NUM_IRQS
];
997 MemoryRegion
*sysmem
= get_system_memory();
998 int gic_version
= vms
->gic_version
;
1000 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
1001 const char *cpu_model
= machine
->cpu_model
;
1003 VirtGuestInfoState
*guest_info_state
= g_malloc0(sizeof *guest_info_state
);
1004 VirtGuestInfo
*guest_info
= &guest_info_state
->info
;
1008 cpu_model
= "cortex-a15";
1011 /* We can probe only here because during property set
1012 * KVM is not available yet
1015 gic_version
= kvm_arm_vgic_probe();
1017 error_report("Unable to determine GIC version supported by host");
1018 error_printf("KVM acceleration is probably not supported\n");
1023 /* Separate the actual CPU model name from any appended features */
1024 cpustr
= g_strsplit(cpu_model
, ",", 2);
1026 vbi
= find_machine_info(cpustr
[0]);
1029 error_report("mach-virt: CPU %s not supported", cpustr
[0]);
1033 /* The maximum number of CPUs depends on the GIC version, or on how
1034 * many redistributors we can fit into the memory map.
1036 if (gic_version
== 3) {
1037 max_cpus
= vbi
->memmap
[VIRT_GIC_REDIST
].size
/ 0x20000;
1039 max_cpus
= GIC_NCPU
;
1042 if (smp_cpus
> max_cpus
) {
1043 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
1044 "supported by machine 'mach-virt' (%d)",
1045 smp_cpus
, max_cpus
);
1049 vbi
->smp_cpus
= smp_cpus
;
1051 if (machine
->ram_size
> vbi
->memmap
[VIRT_MEM
].size
) {
1052 error_report("mach-virt: cannot model more than 30GB RAM");
1058 for (n
= 0; n
< smp_cpus
; n
++) {
1059 ObjectClass
*oc
= cpu_class_by_name(TYPE_ARM_CPU
, cpustr
[0]);
1060 CPUClass
*cc
= CPU_CLASS(oc
);
1063 char *cpuopts
= g_strdup(cpustr
[1]);
1066 error_report("Unable to find CPU definition");
1069 cpuobj
= object_new(object_class_get_name(oc
));
1071 /* Handle any CPU options specified by the user */
1072 cc
->parse_features(CPU(cpuobj
), cpuopts
, &err
);
1075 error_report_err(err
);
1080 object_property_set_bool(cpuobj
, false, "has_el3", NULL
);
1083 object_property_set_int(cpuobj
, QEMU_PSCI_CONDUIT_HVC
, "psci-conduit",
1086 /* Secondary CPUs start in PSCI powered-down state */
1088 object_property_set_bool(cpuobj
, true, "start-powered-off", NULL
);
1091 if (object_property_find(cpuobj
, "reset-cbar", NULL
)) {
1092 object_property_set_int(cpuobj
, vbi
->memmap
[VIRT_CPUPERIPHS
].base
,
1093 "reset-cbar", &error_abort
);
1096 object_property_set_bool(cpuobj
, true, "realized", NULL
);
1099 fdt_add_timer_nodes(vbi
, gic_version
);
1100 fdt_add_cpu_nodes(vbi
);
1101 fdt_add_psci_node(vbi
);
1103 memory_region_allocate_system_memory(ram
, NULL
, "mach-virt.ram",
1105 memory_region_add_subregion(sysmem
, vbi
->memmap
[VIRT_MEM
].base
, ram
);
1109 create_gic(vbi
, pic
, gic_version
, vms
->secure
);
1111 create_uart(vbi
, pic
);
1113 create_rtc(vbi
, pic
);
1115 create_pcie(vbi
, pic
, vms
->highmem
);
1117 create_gpio(vbi
, pic
);
1119 /* Create mmio transports, so the user can create virtio backends
1120 * (which will be automatically plugged in to the transports). If
1121 * no backend is created the transport will just sit harmlessly idle.
1123 create_virtio_devices(vbi
, pic
);
1125 create_fw_cfg(vbi
, &address_space_memory
);
1126 rom_set_fw(fw_cfg_find());
1128 guest_info
->smp_cpus
= smp_cpus
;
1129 guest_info
->fw_cfg
= fw_cfg_find();
1130 guest_info
->memmap
= vbi
->memmap
;
1131 guest_info
->irqmap
= vbi
->irqmap
;
1132 guest_info
->use_highmem
= vms
->highmem
;
1133 guest_info
->gic_version
= gic_version
;
1134 guest_info_state
->machine_done
.notify
= virt_guest_info_machine_done
;
1135 qemu_add_machine_init_done_notifier(&guest_info_state
->machine_done
);
1137 vbi
->bootinfo
.ram_size
= machine
->ram_size
;
1138 vbi
->bootinfo
.kernel_filename
= machine
->kernel_filename
;
1139 vbi
->bootinfo
.kernel_cmdline
= machine
->kernel_cmdline
;
1140 vbi
->bootinfo
.initrd_filename
= machine
->initrd_filename
;
1141 vbi
->bootinfo
.nb_cpus
= smp_cpus
;
1142 vbi
->bootinfo
.board_id
= -1;
1143 vbi
->bootinfo
.loader_start
= vbi
->memmap
[VIRT_MEM
].base
;
1144 vbi
->bootinfo
.get_dtb
= machvirt_dtb
;
1145 vbi
->bootinfo
.firmware_loaded
= bios_name
|| drive_get(IF_PFLASH
, 0, 0);
1146 arm_load_kernel(ARM_CPU(first_cpu
), &vbi
->bootinfo
);
1149 * arm_load_kernel machine init done notifier registration must
1150 * happen before the platform_bus_create call. In this latter,
1151 * another notifier is registered which adds platform bus nodes.
1152 * Notifiers are executed in registration reverse order.
1154 create_platform_bus(vbi
, pic
);
1157 static bool virt_get_secure(Object
*obj
, Error
**errp
)
1159 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1164 static void virt_set_secure(Object
*obj
, bool value
, Error
**errp
)
1166 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1168 vms
->secure
= value
;
1171 static bool virt_get_highmem(Object
*obj
, Error
**errp
)
1173 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1175 return vms
->highmem
;
1178 static void virt_set_highmem(Object
*obj
, bool value
, Error
**errp
)
1180 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1182 vms
->highmem
= value
;
1185 static char *virt_get_gic_version(Object
*obj
, Error
**errp
)
1187 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1188 const char *val
= vms
->gic_version
== 3 ? "3" : "2";
1190 return g_strdup(val
);
1193 static void virt_set_gic_version(Object
*obj
, const char *value
, Error
**errp
)
1195 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1197 if (!strcmp(value
, "3")) {
1198 vms
->gic_version
= 3;
1199 } else if (!strcmp(value
, "2")) {
1200 vms
->gic_version
= 2;
1201 } else if (!strcmp(value
, "host")) {
1202 vms
->gic_version
= 0; /* Will probe later */
1204 error_setg(errp
, "Invalid gic-version value");
1205 error_append_hint(errp
, "Valid values are 3, 2, host.\n");
1209 static void virt_instance_init(Object
*obj
)
1211 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1213 /* EL3 is disabled by default on virt: this makes us consistent
1214 * between KVM and TCG for this board, and it also allows us to
1215 * boot UEFI blobs which assume no TrustZone support.
1217 vms
->secure
= false;
1218 object_property_add_bool(obj
, "secure", virt_get_secure
,
1219 virt_set_secure
, NULL
);
1220 object_property_set_description(obj
, "secure",
1221 "Set on/off to enable/disable the ARM "
1222 "Security Extensions (TrustZone)",
1225 /* High memory is enabled by default */
1226 vms
->highmem
= true;
1227 object_property_add_bool(obj
, "highmem", virt_get_highmem
,
1228 virt_set_highmem
, NULL
);
1229 object_property_set_description(obj
, "highmem",
1230 "Set on/off to enable/disable using "
1231 "physical address space above 32 bits",
1233 /* Default GIC type is v2 */
1234 vms
->gic_version
= 2;
1235 object_property_add_str(obj
, "gic-version", virt_get_gic_version
,
1236 virt_set_gic_version
, NULL
);
1237 object_property_set_description(obj
, "gic-version",
1239 "Valid values are 2, 3 and host", NULL
);
1242 static void virt_class_init(ObjectClass
*oc
, void *data
)
1244 MachineClass
*mc
= MACHINE_CLASS(oc
);
1246 mc
->desc
= "ARM Virtual Machine",
1247 mc
->init
= machvirt_init
;
1248 /* Start max_cpus at the maximum QEMU supports. We'll further restrict
1249 * it later in machvirt_init, where we have more information about the
1250 * configuration of the particular instance.
1252 mc
->max_cpus
= MAX_CPUMASK_BITS
;
1253 mc
->has_dynamic_sysbus
= true;
1254 mc
->block_default_type
= IF_VIRTIO
;
1256 mc
->pci_allow_0_address
= true;
1259 static const TypeInfo machvirt_info
= {
1260 .name
= TYPE_VIRT_MACHINE
,
1261 .parent
= TYPE_MACHINE
,
1262 .instance_size
= sizeof(VirtMachineState
),
1263 .instance_init
= virt_instance_init
,
1264 .class_size
= sizeof(VirtMachineClass
),
1265 .class_init
= virt_class_init
,
1268 static void machvirt_machine_init(void)
1270 type_register_static(&machvirt_info
);
1273 machine_init(machvirt_machine_init
);