hw/ppc/pnv_psi.c

   1 /*
   2  * QEMU PowerPC PowerNV Processor Service Interface (PSI) model
   3  *
   4  * Copyright (c) 2015-2017, IBM Corporation.
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "hw/hw.h"
  22 #include "target/ppc/cpu.h"
  23 #include "qemu/log.h"
  24 #include "qapi/error.h"
  25 #include "monitor/monitor.h"
  26
  27 #include "exec/address-spaces.h"
  28
  29 #include "hw/ppc/fdt.h"
  30 #include "hw/ppc/pnv.h"
  31 #include "hw/ppc/pnv_xscom.h"
  32 #include "hw/ppc/pnv_psi.h"
  33
  34 #include <libfdt.h>
  35
  36 #define PSIHB_XSCOM_FIR_RW      0x00
  37 #define PSIHB_XSCOM_FIR_AND     0x01
  38 #define PSIHB_XSCOM_FIR_OR      0x02
  39 #define PSIHB_XSCOM_FIRMASK_RW  0x03
  40 #define PSIHB_XSCOM_FIRMASK_AND 0x04
  41 #define PSIHB_XSCOM_FIRMASK_OR  0x05
  42 #define PSIHB_XSCOM_FIRACT0     0x06
  43 #define PSIHB_XSCOM_FIRACT1     0x07
  44
  45 /* Host Bridge Base Address Register */
  46 #define PSIHB_XSCOM_BAR         0x0a
  47 #define   PSIHB_BAR_EN                  0x0000000000000001ull
  48
  49 /* FSP Base Address Register */
  50 #define PSIHB_XSCOM_FSPBAR      0x0b
  51
  52 /* PSI Host Bridge Control/Status Register */
  53 #define PSIHB_XSCOM_CR          0x0e
  54 #define   PSIHB_CR_FSP_CMD_ENABLE       0x8000000000000000ull
  55 #define   PSIHB_CR_FSP_MMIO_ENABLE      0x4000000000000000ull
  56 #define   PSIHB_CR_FSP_IRQ_ENABLE       0x1000000000000000ull
  57 #define   PSIHB_CR_FSP_ERR_RSP_ENABLE   0x0800000000000000ull
  58 #define   PSIHB_CR_PSI_LINK_ENABLE      0x0400000000000000ull
  59 #define   PSIHB_CR_FSP_RESET            0x0200000000000000ull
  60 #define   PSIHB_CR_PSIHB_RESET          0x0100000000000000ull
  61 #define   PSIHB_CR_PSI_IRQ              0x0000800000000000ull
  62 #define   PSIHB_CR_FSP_IRQ              0x0000400000000000ull
  63 #define   PSIHB_CR_FSP_LINK_ACTIVE      0x0000200000000000ull
  64 #define   PSIHB_CR_IRQ_CMD_EXPECT       0x0000010000000000ull
  65           /* and more ... */
  66
  67 /* PSIHB Status / Error Mask Register */
  68 #define PSIHB_XSCOM_SEMR        0x0f
  69
  70 /* XIVR, to signal interrupts to the CEC firmware. more XIVR below. */
  71 #define PSIHB_XSCOM_XIVR_FSP    0x10
  72 #define   PSIHB_XIVR_SERVER_SH          40
  73 #define   PSIHB_XIVR_SERVER_MSK         (0xffffull << PSIHB_XIVR_SERVER_SH)
  74 #define   PSIHB_XIVR_PRIO_SH            32
  75 #define   PSIHB_XIVR_PRIO_MSK           (0xffull << PSIHB_XIVR_PRIO_SH)
  76 #define   PSIHB_XIVR_SRC_SH             29
  77 #define   PSIHB_XIVR_SRC_MSK            (0x7ull << PSIHB_XIVR_SRC_SH)
  78 #define   PSIHB_XIVR_PENDING            0x01000000ull
  79
  80 /* PSI Host Bridge Set Control/ Status Register */
  81 #define PSIHB_XSCOM_SCR         0x12
  82
  83 /* PSI Host Bridge Clear Control/ Status Register */
  84 #define PSIHB_XSCOM_CCR         0x13
  85
  86 /* DMA Upper Address Register */
  87 #define PSIHB_XSCOM_DMA_UPADD   0x14
  88
  89 /* Interrupt Status */
  90 #define PSIHB_XSCOM_IRQ_STAT    0x15
  91 #define   PSIHB_IRQ_STAT_OCC            0x0000001000000000ull
  92 #define   PSIHB_IRQ_STAT_FSI            0x0000000800000000ull
  93 #define   PSIHB_IRQ_STAT_LPCI2C         0x0000000400000000ull
  94 #define   PSIHB_IRQ_STAT_LOCERR         0x0000000200000000ull
  95 #define   PSIHB_IRQ_STAT_EXT            0x0000000100000000ull
  96
  97 /* remaining XIVR */
  98 #define PSIHB_XSCOM_XIVR_OCC    0x16
  99 #define PSIHB_XSCOM_XIVR_FSI    0x17
 100 #define PSIHB_XSCOM_XIVR_LPCI2C 0x18
 101 #define PSIHB_XSCOM_XIVR_LOCERR 0x19
 102 #define PSIHB_XSCOM_XIVR_EXT    0x1a
 103
 104 /* Interrupt Requester Source Compare Register */
 105 #define PSIHB_XSCOM_IRSN        0x1b
 106 #define   PSIHB_IRSN_COMP_SH            45
 107 #define   PSIHB_IRSN_COMP_MSK           (0x7ffffull << PSIHB_IRSN_COMP_SH)
 108 #define   PSIHB_IRSN_IRQ_MUX            0x0000000800000000ull
 109 #define   PSIHB_IRSN_IRQ_RESET          0x0000000400000000ull
 110 #define   PSIHB_IRSN_DOWNSTREAM_EN      0x0000000200000000ull
 111 #define   PSIHB_IRSN_UPSTREAM_EN        0x0000000100000000ull
 112 #define   PSIHB_IRSN_COMPMASK_SH        13
 113 #define   PSIHB_IRSN_COMPMASK_MSK       (0x7ffffull << PSIHB_IRSN_COMPMASK_SH)
 114
 115 #define PSIHB_BAR_MASK                  0x0003fffffff00000ull
 116 #define PSIHB_FSPBAR_MASK               0x0003ffff00000000ull
 117
 118 #define PSIHB9_BAR_MASK                 0x00fffffffff00000ull
 119 #define PSIHB9_FSPBAR_MASK              0x00ffffff00000000ull
 120
 121 #define PSIHB_REG(addr) (((addr) >> 3) + PSIHB_XSCOM_BAR)
 122
 123 static void pnv_psi_set_bar(PnvPsi *psi, uint64_t bar)
 124 {
 125     PnvPsiClass *ppc = PNV_PSI_GET_CLASS(psi);
 126     MemoryRegion *sysmem = get_system_memory();
 127     uint64_t old = psi->regs[PSIHB_XSCOM_BAR];
 128
 129     psi->regs[PSIHB_XSCOM_BAR] = bar & (ppc->bar_mask | PSIHB_BAR_EN);
 130
 131     /* Update MR, always remove it first */
 132     if (old & PSIHB_BAR_EN) {
 133         memory_region_del_subregion(sysmem, &psi->regs_mr);
 134     }
 135
 136     /* Then add it back if needed */
 137     if (bar & PSIHB_BAR_EN) {
 138         uint64_t addr = bar & ppc->bar_mask;
 139         memory_region_add_subregion(sysmem, addr, &psi->regs_mr);
 140     }
 141 }
 142
 143 static void pnv_psi_update_fsp_mr(PnvPsi *psi)
 144 {
 145     /* TODO: Update FSP MR if/when we support FSP BAR */
 146 }
 147
 148 static void pnv_psi_set_cr(PnvPsi *psi, uint64_t cr)
 149 {
 150     uint64_t old = psi->regs[PSIHB_XSCOM_CR];
 151
 152     psi->regs[PSIHB_XSCOM_CR] = cr;
 153
 154     /* Check some bit changes */
 155     if ((old ^ psi->regs[PSIHB_XSCOM_CR]) & PSIHB_CR_FSP_MMIO_ENABLE) {
 156         pnv_psi_update_fsp_mr(psi);
 157     }
 158 }
 159
 160 static void pnv_psi_set_irsn(PnvPsi *psi, uint64_t val)
 161 {
 162     ICSState *ics = &PNV8_PSI(psi)->ics;
 163
 164     /* In this model we ignore the up/down enable bits for now
 165      * as SW doesn't use them (other than setting them at boot).
 166      * We ignore IRQ_MUX, its meaning isn't clear and we don't use
 167      * it and finally we ignore reset (XXX fix that ?)
 168      */
 169     psi->regs[PSIHB_XSCOM_IRSN] = val & (PSIHB_IRSN_COMP_MSK |
 170                                          PSIHB_IRSN_IRQ_MUX |
 171                                          PSIHB_IRSN_IRQ_RESET |
 172                                          PSIHB_IRSN_DOWNSTREAM_EN |
 173                                          PSIHB_IRSN_UPSTREAM_EN);
 174
 175     /* We ignore the compare mask as well, our ICS emulation is too
 176      * simplistic to make any use if it, and we extract the offset
 177      * from the compare value
 178      */
 179     ics->offset = (val & PSIHB_IRSN_COMP_MSK) >> PSIHB_IRSN_COMP_SH;
 180 }
 181
 182 /*
 183  * FSP and PSI interrupts are muxed under the same number.
 184  */
 185 static const uint32_t xivr_regs[] = {
 186     [PSIHB_IRQ_PSI]       = PSIHB_XSCOM_XIVR_FSP,
 187     [PSIHB_IRQ_FSP]       = PSIHB_XSCOM_XIVR_FSP,
 188     [PSIHB_IRQ_OCC]       = PSIHB_XSCOM_XIVR_OCC,
 189     [PSIHB_IRQ_FSI]       = PSIHB_XSCOM_XIVR_FSI,
 190     [PSIHB_IRQ_LPC_I2C]   = PSIHB_XSCOM_XIVR_LPCI2C,
 191     [PSIHB_IRQ_LOCAL_ERR] = PSIHB_XSCOM_XIVR_LOCERR,
 192     [PSIHB_IRQ_EXTERNAL]  = PSIHB_XSCOM_XIVR_EXT,
 193 };
 194
 195 static const uint32_t stat_regs[] = {
 196     [PSIHB_IRQ_PSI]       = PSIHB_XSCOM_CR,
 197     [PSIHB_IRQ_FSP]       = PSIHB_XSCOM_CR,
 198     [PSIHB_IRQ_OCC]       = PSIHB_XSCOM_IRQ_STAT,
 199     [PSIHB_IRQ_FSI]       = PSIHB_XSCOM_IRQ_STAT,
 200     [PSIHB_IRQ_LPC_I2C]   = PSIHB_XSCOM_IRQ_STAT,
 201     [PSIHB_IRQ_LOCAL_ERR] = PSIHB_XSCOM_IRQ_STAT,
 202     [PSIHB_IRQ_EXTERNAL]  = PSIHB_XSCOM_IRQ_STAT,
 203 };
 204
 205 static const uint64_t stat_bits[] = {
 206     [PSIHB_IRQ_PSI]       = PSIHB_CR_PSI_IRQ,
 207     [PSIHB_IRQ_FSP]       = PSIHB_CR_FSP_IRQ,
 208     [PSIHB_IRQ_OCC]       = PSIHB_IRQ_STAT_OCC,
 209     [PSIHB_IRQ_FSI]       = PSIHB_IRQ_STAT_FSI,
 210     [PSIHB_IRQ_LPC_I2C]   = PSIHB_IRQ_STAT_LPCI2C,
 211     [PSIHB_IRQ_LOCAL_ERR] = PSIHB_IRQ_STAT_LOCERR,
 212     [PSIHB_IRQ_EXTERNAL]  = PSIHB_IRQ_STAT_EXT,
 213 };
 214
 215 void pnv_psi_irq_set(PnvPsi *psi, int irq, bool state)
 216 {
 217     PNV_PSI_GET_CLASS(psi)->irq_set(psi, irq, state);
 218 }
 219
 220 static void pnv_psi_power8_irq_set(PnvPsi *psi, int irq, bool state)
 221 {
 222     uint32_t xivr_reg;
 223     uint32_t stat_reg;
 224     uint32_t src;
 225     bool masked;
 226
 227     if (irq > PSIHB_IRQ_EXTERNAL) {
 228         qemu_log_mask(LOG_GUEST_ERROR, "PSI: Unsupported irq %d\n", irq);
 229         return;
 230     }
 231
 232     xivr_reg = xivr_regs[irq];
 233     stat_reg = stat_regs[irq];
 234
 235     src = (psi->regs[xivr_reg] & PSIHB_XIVR_SRC_MSK) >> PSIHB_XIVR_SRC_SH;
 236     if (state) {
 237         psi->regs[stat_reg] |= stat_bits[irq];
 238         /* TODO: optimization, check mask here. That means
 239          * re-evaluating when unmasking
 240          */
 241         qemu_irq_raise(psi->qirqs[src]);
 242     } else {
 243         psi->regs[stat_reg] &= ~stat_bits[irq];
 244
 245         /* FSP and PSI are muxed so don't lower if either is still set */
 246         if (stat_reg != PSIHB_XSCOM_CR ||
 247             !(psi->regs[stat_reg] & (PSIHB_CR_PSI_IRQ | PSIHB_CR_FSP_IRQ))) {
 248             qemu_irq_lower(psi->qirqs[src]);
 249         } else {
 250             state = true;
 251         }
 252     }
 253
 254     /* Note about the emulation of the pending bit: This isn't
 255      * entirely correct. The pending bit should be cleared when the
 256      * EOI has been received. However, we don't have callbacks on EOI
 257      * (especially not under KVM) so no way to emulate that properly,
 258      * so instead we just set that bit as the logical "output" of the
 259      * XIVR (ie pending & !masked)
 260      *
 261      * CLG: We could define a new ICS object with a custom eoi()
 262      * handler to clear the pending bit. But I am not sure this would
 263      * be useful for the software anyhow.
 264      */
 265     masked = (psi->regs[xivr_reg] & PSIHB_XIVR_PRIO_MSK) == PSIHB_XIVR_PRIO_MSK;
 266     if (state && !masked) {
 267         psi->regs[xivr_reg] |= PSIHB_XIVR_PENDING;
 268     } else {
 269         psi->regs[xivr_reg] &= ~PSIHB_XIVR_PENDING;
 270     }
 271 }
 272
 273 static void pnv_psi_set_xivr(PnvPsi *psi, uint32_t reg, uint64_t val)
 274 {
 275     ICSState *ics = &PNV8_PSI(psi)->ics;
 276     uint16_t server;
 277     uint8_t prio;
 278     uint8_t src;
 279
 280     psi->regs[reg] = (psi->regs[reg] & PSIHB_XIVR_PENDING) |
 281             (val & (PSIHB_XIVR_SERVER_MSK |
 282                     PSIHB_XIVR_PRIO_MSK |
 283                     PSIHB_XIVR_SRC_MSK));
 284     val = psi->regs[reg];
 285     server = (val & PSIHB_XIVR_SERVER_MSK) >> PSIHB_XIVR_SERVER_SH;
 286     prio = (val & PSIHB_XIVR_PRIO_MSK) >> PSIHB_XIVR_PRIO_SH;
 287     src = (val & PSIHB_XIVR_SRC_MSK) >> PSIHB_XIVR_SRC_SH;
 288
 289     if (src >= PSI_NUM_INTERRUPTS) {
 290         qemu_log_mask(LOG_GUEST_ERROR, "PSI: Unsupported irq %d\n", src);
 291         return;
 292     }
 293
 294     /* Remove pending bit if the IRQ is masked */
 295     if ((psi->regs[reg] & PSIHB_XIVR_PRIO_MSK) == PSIHB_XIVR_PRIO_MSK) {
 296         psi->regs[reg] &= ~PSIHB_XIVR_PENDING;
 297     }
 298
 299     /* The low order 2 bits are the link pointer (Type II interrupts).
 300      * Shift back to get a valid IRQ server.
 301      */
 302     server >>= 2;
 303
 304     /* Now because of source remapping, weird things can happen
 305      * if you change the source number dynamically, our simple ICS
 306      * doesn't deal with remapping. So we just poke a different
 307      * ICS entry based on what source number was written. This will
 308      * do for now but a more accurate implementation would instead
 309      * use a fixed server/prio and a remapper of the generated irq.
 310      */
 311     ics_simple_write_xive(ics, src, server, prio, prio);
 312 }
 313
 314 static uint64_t pnv_psi_reg_read(PnvPsi *psi, uint32_t offset, bool mmio)
 315 {
 316     uint64_t val = 0xffffffffffffffffull;
 317
 318     switch (offset) {
 319     case PSIHB_XSCOM_FIR_RW:
 320     case PSIHB_XSCOM_FIRACT0:
 321     case PSIHB_XSCOM_FIRACT1:
 322     case PSIHB_XSCOM_BAR:
 323     case PSIHB_XSCOM_FSPBAR:
 324     case PSIHB_XSCOM_CR:
 325     case PSIHB_XSCOM_XIVR_FSP:
 326     case PSIHB_XSCOM_XIVR_OCC:
 327     case PSIHB_XSCOM_XIVR_FSI:
 328     case PSIHB_XSCOM_XIVR_LPCI2C:
 329     case PSIHB_XSCOM_XIVR_LOCERR:
 330     case PSIHB_XSCOM_XIVR_EXT:
 331     case PSIHB_XSCOM_IRQ_STAT:
 332     case PSIHB_XSCOM_SEMR:
 333     case PSIHB_XSCOM_DMA_UPADD:
 334     case PSIHB_XSCOM_IRSN:
 335         val = psi->regs[offset];
 336         break;
 337     default:
 338         qemu_log_mask(LOG_UNIMP, "PSI: read at 0x%" PRIx32 "\n", offset);
 339     }
 340     return val;
 341 }
 342
 343 static void pnv_psi_reg_write(PnvPsi *psi, uint32_t offset, uint64_t val,
 344                               bool mmio)
 345 {
 346     switch (offset) {
 347     case PSIHB_XSCOM_FIR_RW:
 348     case PSIHB_XSCOM_FIRACT0:
 349     case PSIHB_XSCOM_FIRACT1:
 350     case PSIHB_XSCOM_SEMR:
 351     case PSIHB_XSCOM_DMA_UPADD:
 352         psi->regs[offset] = val;
 353         break;
 354     case PSIHB_XSCOM_FIR_OR:
 355         psi->regs[PSIHB_XSCOM_FIR_RW] |= val;
 356         break;
 357     case PSIHB_XSCOM_FIR_AND:
 358         psi->regs[PSIHB_XSCOM_FIR_RW] &= val;
 359         break;
 360     case PSIHB_XSCOM_BAR:
 361         /* Only XSCOM can write this one */
 362         if (!mmio) {
 363             pnv_psi_set_bar(psi, val);
 364         } else {
 365             qemu_log_mask(LOG_GUEST_ERROR, "PSI: invalid write of BAR\n");
 366         }
 367         break;
 368     case PSIHB_XSCOM_FSPBAR:
 369         psi->regs[PSIHB_XSCOM_FSPBAR] = val & PSIHB_FSPBAR_MASK;
 370         pnv_psi_update_fsp_mr(psi);
 371         break;
 372     case PSIHB_XSCOM_CR:
 373         pnv_psi_set_cr(psi, val);
 374         break;
 375     case PSIHB_XSCOM_SCR:
 376         pnv_psi_set_cr(psi, psi->regs[PSIHB_XSCOM_CR] | val);
 377         break;
 378     case PSIHB_XSCOM_CCR:
 379         pnv_psi_set_cr(psi, psi->regs[PSIHB_XSCOM_CR] & ~val);
 380         break;
 381     case PSIHB_XSCOM_XIVR_FSP:
 382     case PSIHB_XSCOM_XIVR_OCC:
 383     case PSIHB_XSCOM_XIVR_FSI:
 384     case PSIHB_XSCOM_XIVR_LPCI2C:
 385     case PSIHB_XSCOM_XIVR_LOCERR:
 386     case PSIHB_XSCOM_XIVR_EXT:
 387         pnv_psi_set_xivr(psi, offset, val);
 388         break;
 389     case PSIHB_XSCOM_IRQ_STAT:
 390         /* Read only */
 391         qemu_log_mask(LOG_GUEST_ERROR, "PSI: invalid write of IRQ_STAT\n");
 392         break;
 393     case PSIHB_XSCOM_IRSN:
 394         pnv_psi_set_irsn(psi, val);
 395         break;
 396     default:
 397         qemu_log_mask(LOG_UNIMP, "PSI: write at 0x%" PRIx32 "\n", offset);
 398     }
 399 }
 400
 401 /*
 402  * The values of the registers when accessed through the MMIO region
 403  * follow the relation : xscom = (mmio + 0x50) >> 3
 404  */
 405 static uint64_t pnv_psi_mmio_read(void *opaque, hwaddr addr, unsigned size)
 406 {
 407     return pnv_psi_reg_read(opaque, PSIHB_REG(addr), true);
 408 }
 409
 410 static void pnv_psi_mmio_write(void *opaque, hwaddr addr,
 411                               uint64_t val, unsigned size)
 412 {
 413     pnv_psi_reg_write(opaque, PSIHB_REG(addr), val, true);
 414 }
 415
 416 static const MemoryRegionOps psi_mmio_ops = {
 417     .read = pnv_psi_mmio_read,
 418     .write = pnv_psi_mmio_write,
 419     .endianness = DEVICE_BIG_ENDIAN,
 420     .valid = {
 421         .min_access_size = 8,
 422         .max_access_size = 8,
 423     },
 424     .impl = {
 425         .min_access_size = 8,
 426         .max_access_size = 8,
 427     },
 428 };
 429
 430 static uint64_t pnv_psi_xscom_read(void *opaque, hwaddr addr, unsigned size)
 431 {
 432     return pnv_psi_reg_read(opaque, addr >> 3, false);
 433 }
 434
 435 static void pnv_psi_xscom_write(void *opaque, hwaddr addr,
 436                                 uint64_t val, unsigned size)
 437 {
 438     pnv_psi_reg_write(opaque, addr >> 3, val, false);
 439 }
 440
 441 static const MemoryRegionOps pnv_psi_xscom_ops = {
 442     .read = pnv_psi_xscom_read,
 443     .write = pnv_psi_xscom_write,
 444     .endianness = DEVICE_BIG_ENDIAN,
 445     .valid = {
 446         .min_access_size = 8,
 447         .max_access_size = 8,
 448     },
 449     .impl = {
 450         .min_access_size = 8,
 451         .max_access_size = 8,
 452     }
 453 };
 454
 455 static void pnv_psi_reset(void *dev)
 456 {
 457     PnvPsi *psi = PNV_PSI(dev);
 458
 459     memset(psi->regs, 0x0, sizeof(psi->regs));
 460
 461     psi->regs[PSIHB_XSCOM_BAR] = psi->bar | PSIHB_BAR_EN;
 462 }
 463
 464 static void pnv_psi_power8_instance_init(Object *obj)
 465 {
 466     Pnv8Psi *psi8 = PNV8_PSI(obj);
 467
 468     object_initialize_child(obj, "ics-psi",  &psi8->ics, sizeof(psi8->ics),
 469                             TYPE_ICS_SIMPLE, &error_abort, NULL);
 470 }
 471
 472 static const uint8_t irq_to_xivr[] = {
 473     PSIHB_XSCOM_XIVR_FSP,
 474     PSIHB_XSCOM_XIVR_OCC,
 475     PSIHB_XSCOM_XIVR_FSI,
 476     PSIHB_XSCOM_XIVR_LPCI2C,
 477     PSIHB_XSCOM_XIVR_LOCERR,
 478     PSIHB_XSCOM_XIVR_EXT,
 479 };
 480
 481 static void pnv_psi_power8_realize(DeviceState *dev, Error **errp)
 482 {
 483     PnvPsi *psi = PNV_PSI(dev);
 484     ICSState *ics = &PNV8_PSI(psi)->ics;
 485     Object *obj;
 486     Error *err = NULL;
 487     unsigned int i;
 488
 489     obj = object_property_get_link(OBJECT(dev), "xics", &err);
 490     if (!obj) {
 491         error_setg(errp, "%s: required link 'xics' not found: %s",
 492                    __func__, error_get_pretty(err));
 493         return;
 494     }
 495
 496     /* Create PSI interrupt control source */
 497     object_property_add_const_link(OBJECT(ics), ICS_PROP_XICS, obj,
 498                                    &error_abort);
 499     object_property_set_int(OBJECT(ics), PSI_NUM_INTERRUPTS, "nr-irqs", &err);
 500     if (err) {
 501         error_propagate(errp, err);
 502         return;
 503     }
 504     object_property_set_bool(OBJECT(ics), true, "realized",  &err);
 505     if (err) {
 506         error_propagate(errp, err);
 507         return;
 508     }
 509
 510     for (i = 0; i < ics->nr_irqs; i++) {
 511         ics_set_irq_type(ics, i, true);
 512     }
 513
 514     psi->qirqs = qemu_allocate_irqs(ics_simple_set_irq, ics, ics->nr_irqs);
 515
 516     /* XSCOM region for PSI registers */
 517     pnv_xscom_region_init(&psi->xscom_regs, OBJECT(dev), &pnv_psi_xscom_ops,
 518                 psi, "xscom-psi", PNV_XSCOM_PSIHB_SIZE);
 519
 520     /* Initialize MMIO region */
 521     memory_region_init_io(&psi->regs_mr, OBJECT(dev), &psi_mmio_ops, psi,
 522                           "psihb", PNV_PSIHB_SIZE);
 523
 524     /* Default BAR for MMIO region */
 525     pnv_psi_set_bar(psi, psi->bar | PSIHB_BAR_EN);
 526
 527     /* Default sources in XIVR */
 528     for (i = 0; i < PSI_NUM_INTERRUPTS; i++) {
 529         uint8_t xivr = irq_to_xivr[i];
 530         psi->regs[xivr] = PSIHB_XIVR_PRIO_MSK |
 531             ((uint64_t) i << PSIHB_XIVR_SRC_SH);
 532     }
 533
 534     qemu_register_reset(pnv_psi_reset, dev);
 535 }
 536
 537 static const char compat_p8[] = "ibm,power8-psihb-x\0ibm,psihb-x";
 538 static const char compat_p9[] = "ibm,power9-psihb-x\0ibm,psihb-x";
 539
 540 static int pnv_psi_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset)
 541 {
 542     PnvPsiClass *ppc = PNV_PSI_GET_CLASS(dev);
 543     char *name;
 544     int offset;
 545     uint32_t reg[] = {
 546         cpu_to_be32(ppc->xscom_pcba),
 547         cpu_to_be32(ppc->xscom_size)
 548     };
 549
 550     name = g_strdup_printf("psihb@%x", ppc->xscom_pcba);
 551     offset = fdt_add_subnode(fdt, xscom_offset, name);
 552     _FDT(offset);
 553     g_free(name);
 554
 555     _FDT(fdt_setprop(fdt, offset, "reg", reg, sizeof(reg)));
 556     _FDT(fdt_setprop_cell(fdt, offset, "#address-cells", 2));
 557     _FDT(fdt_setprop_cell(fdt, offset, "#size-cells", 1));
 558     if (ppc->chip_type == PNV_CHIP_POWER9) {
 559         _FDT(fdt_setprop(fdt, offset, "compatible", compat_p9,
 560                          sizeof(compat_p9)));
 561     } else {
 562         _FDT(fdt_setprop(fdt, offset, "compatible", compat_p8,
 563                          sizeof(compat_p8)));
 564     }
 565     return 0;
 566 }
 567
 568 static Property pnv_psi_properties[] = {
 569     DEFINE_PROP_UINT64("bar", PnvPsi, bar, 0),
 570     DEFINE_PROP_UINT64("fsp-bar", PnvPsi, fsp_bar, 0),
 571     DEFINE_PROP_END_OF_LIST(),
 572 };
 573
 574 static void pnv_psi_power8_class_init(ObjectClass *klass, void *data)
 575 {
 576     DeviceClass *dc = DEVICE_CLASS(klass);
 577     PnvPsiClass *ppc = PNV_PSI_CLASS(klass);
 578
 579     dc->desc    = "PowerNV PSI Controller POWER8";
 580     dc->realize = pnv_psi_power8_realize;
 581
 582     ppc->chip_type =  PNV_CHIP_POWER8;
 583     ppc->xscom_pcba = PNV_XSCOM_PSIHB_BASE;
 584     ppc->xscom_size = PNV_XSCOM_PSIHB_SIZE;
 585     ppc->bar_mask   = PSIHB_BAR_MASK;
 586     ppc->irq_set    = pnv_psi_power8_irq_set;
 587 }
 588
 589 static const TypeInfo pnv_psi_power8_info = {
 590     .name          = TYPE_PNV8_PSI,
 591     .parent        = TYPE_PNV_PSI,
 592     .instance_size = sizeof(Pnv8Psi),
 593     .instance_init = pnv_psi_power8_instance_init,
 594     .class_init    = pnv_psi_power8_class_init,
 595 };
 596
 597
 598 /* Common registers */
 599
 600 #define PSIHB9_CR                       0x20
 601 #define PSIHB9_SEMR                     0x28
 602
 603 /* P9 registers */
 604
 605 #define PSIHB9_INTERRUPT_CONTROL        0x58
 606 #define   PSIHB9_IRQ_METHOD             PPC_BIT(0)
 607 #define   PSIHB9_IRQ_RESET              PPC_BIT(1)
 608 #define PSIHB9_ESB_CI_BASE              0x60
 609 #define   PSIHB9_ESB_CI_VALID           1
 610 #define PSIHB9_ESB_NOTIF_ADDR           0x68
 611 #define   PSIHB9_ESB_NOTIF_VALID        1
 612 #define PSIHB9_IVT_OFFSET               0x70
 613 #define   PSIHB9_IVT_OFF_SHIFT          32
 614
 615 #define PSIHB9_IRQ_LEVEL                0x78 /* assertion */
 616 #define   PSIHB9_IRQ_LEVEL_PSI          PPC_BIT(0)
 617 #define   PSIHB9_IRQ_LEVEL_OCC          PPC_BIT(1)
 618 #define   PSIHB9_IRQ_LEVEL_FSI          PPC_BIT(2)
 619 #define   PSIHB9_IRQ_LEVEL_LPCHC        PPC_BIT(3)
 620 #define   PSIHB9_IRQ_LEVEL_LOCAL_ERR    PPC_BIT(4)
 621 #define   PSIHB9_IRQ_LEVEL_GLOBAL_ERR   PPC_BIT(5)
 622 #define   PSIHB9_IRQ_LEVEL_TPM          PPC_BIT(6)
 623 #define   PSIHB9_IRQ_LEVEL_LPC_SIRQ1    PPC_BIT(7)
 624 #define   PSIHB9_IRQ_LEVEL_LPC_SIRQ2    PPC_BIT(8)
 625 #define   PSIHB9_IRQ_LEVEL_LPC_SIRQ3    PPC_BIT(9)
 626 #define   PSIHB9_IRQ_LEVEL_LPC_SIRQ4    PPC_BIT(10)
 627 #define   PSIHB9_IRQ_LEVEL_SBE_I2C      PPC_BIT(11)
 628 #define   PSIHB9_IRQ_LEVEL_DIO          PPC_BIT(12)
 629 #define   PSIHB9_IRQ_LEVEL_PSU          PPC_BIT(13)
 630 #define   PSIHB9_IRQ_LEVEL_I2C_C        PPC_BIT(14)
 631 #define   PSIHB9_IRQ_LEVEL_I2C_D        PPC_BIT(15)
 632 #define   PSIHB9_IRQ_LEVEL_I2C_E        PPC_BIT(16)
 633 #define   PSIHB9_IRQ_LEVEL_SBE          PPC_BIT(19)
 634
 635 #define PSIHB9_IRQ_STAT                 0x80 /* P bit */
 636 #define   PSIHB9_IRQ_STAT_PSI           PPC_BIT(0)
 637 #define   PSIHB9_IRQ_STAT_OCC           PPC_BIT(1)
 638 #define   PSIHB9_IRQ_STAT_FSI           PPC_BIT(2)
 639 #define   PSIHB9_IRQ_STAT_LPCHC         PPC_BIT(3)
 640 #define   PSIHB9_IRQ_STAT_LOCAL_ERR     PPC_BIT(4)
 641 #define   PSIHB9_IRQ_STAT_GLOBAL_ERR    PPC_BIT(5)
 642 #define   PSIHB9_IRQ_STAT_TPM           PPC_BIT(6)
 643 #define   PSIHB9_IRQ_STAT_LPC_SIRQ1     PPC_BIT(7)
 644 #define   PSIHB9_IRQ_STAT_LPC_SIRQ2     PPC_BIT(8)
 645 #define   PSIHB9_IRQ_STAT_LPC_SIRQ3     PPC_BIT(9)
 646 #define   PSIHB9_IRQ_STAT_LPC_SIRQ4     PPC_BIT(10)
 647 #define   PSIHB9_IRQ_STAT_SBE_I2C       PPC_BIT(11)
 648 #define   PSIHB9_IRQ_STAT_DIO           PPC_BIT(12)
 649 #define   PSIHB9_IRQ_STAT_PSU           PPC_BIT(13)
 650
 651 static void pnv_psi_notify(XiveNotifier *xf, uint32_t srcno)
 652 {
 653     PnvPsi *psi = PNV_PSI(xf);
 654     uint64_t notif_port = psi->regs[PSIHB_REG(PSIHB9_ESB_NOTIF_ADDR)];
 655     bool valid = notif_port & PSIHB9_ESB_NOTIF_VALID;
 656     uint64_t notify_addr = notif_port & ~PSIHB9_ESB_NOTIF_VALID;
 657
 658     uint32_t offset =
 659         (psi->regs[PSIHB_REG(PSIHB9_IVT_OFFSET)] >> PSIHB9_IVT_OFF_SHIFT);
 660     uint64_t lisn = cpu_to_be64(offset + srcno);
 661
 662     if (valid) {
 663         cpu_physical_memory_write(notify_addr, &lisn, sizeof(lisn));
 664     }
 665 }
 666
 667 static uint64_t pnv_psi_p9_mmio_read(void *opaque, hwaddr addr, unsigned size)
 668 {
 669     PnvPsi *psi = PNV_PSI(opaque);
 670     uint32_t reg = PSIHB_REG(addr);
 671     uint64_t val = -1;
 672
 673     switch (addr) {
 674     case PSIHB9_CR:
 675     case PSIHB9_SEMR:
 676         /* FSP stuff */
 677     case PSIHB9_INTERRUPT_CONTROL:
 678     case PSIHB9_ESB_CI_BASE:
 679     case PSIHB9_ESB_NOTIF_ADDR:
 680     case PSIHB9_IVT_OFFSET:
 681         val = psi->regs[reg];
 682         break;
 683     default:
 684         qemu_log_mask(LOG_GUEST_ERROR, "PSI: read at 0x%" PRIx64 "\n", addr);
 685     }
 686
 687     return val;
 688 }
 689
 690 static void pnv_psi_p9_mmio_write(void *opaque, hwaddr addr,
 691                                   uint64_t val, unsigned size)
 692 {
 693     PnvPsi *psi = PNV_PSI(opaque);
 694     Pnv9Psi *psi9 = PNV9_PSI(psi);
 695     uint32_t reg = PSIHB_REG(addr);
 696     MemoryRegion *sysmem = get_system_memory();
 697
 698     switch (addr) {
 699     case PSIHB9_CR:
 700     case PSIHB9_SEMR:
 701         /* FSP stuff */
 702         break;
 703     case PSIHB9_INTERRUPT_CONTROL:
 704         if (val & PSIHB9_IRQ_RESET) {
 705             device_reset(DEVICE(&psi9->source));
 706         }
 707         psi->regs[reg] = val;
 708         break;
 709
 710     case PSIHB9_ESB_CI_BASE:
 711         if (!(val & PSIHB9_ESB_CI_VALID)) {
 712             if (psi->regs[reg] & PSIHB9_ESB_CI_VALID) {
 713                 memory_region_del_subregion(sysmem, &psi9->source.esb_mmio);
 714             }
 715         } else {
 716             if (!(psi->regs[reg] & PSIHB9_ESB_CI_VALID)) {
 717                 memory_region_add_subregion(sysmem,
 718                                         val & ~PSIHB9_ESB_CI_VALID,
 719                                         &psi9->source.esb_mmio);
 720             }
 721         }
 722         psi->regs[reg] = val;
 723         break;
 724
 725     case PSIHB9_ESB_NOTIF_ADDR:
 726         psi->regs[reg] = val;
 727         break;
 728     case PSIHB9_IVT_OFFSET:
 729         psi->regs[reg] = val;
 730         break;
 731     default:
 732         qemu_log_mask(LOG_GUEST_ERROR, "PSI: write at 0x%" PRIx64 "\n", addr);
 733     }
 734 }
 735
 736 static const MemoryRegionOps pnv_psi_p9_mmio_ops = {
 737     .read = pnv_psi_p9_mmio_read,
 738     .write = pnv_psi_p9_mmio_write,
 739     .endianness = DEVICE_BIG_ENDIAN,
 740     .valid = {
 741         .min_access_size = 8,
 742         .max_access_size = 8,
 743     },
 744     .impl = {
 745         .min_access_size = 8,
 746         .max_access_size = 8,
 747     },
 748 };
 749
 750 static uint64_t pnv_psi_p9_xscom_read(void *opaque, hwaddr addr, unsigned size)
 751 {
 752     /* No read are expected */
 753     qemu_log_mask(LOG_GUEST_ERROR, "PSI: xscom read at 0x%" PRIx64 "\n", addr);
 754     return -1;
 755 }
 756
 757 static void pnv_psi_p9_xscom_write(void *opaque, hwaddr addr,
 758                                 uint64_t val, unsigned size)
 759 {
 760     PnvPsi *psi = PNV_PSI(opaque);
 761
 762     /* XSCOM is only used to set the PSIHB MMIO region */
 763     switch (addr >> 3) {
 764     case PSIHB_XSCOM_BAR:
 765         pnv_psi_set_bar(psi, val);
 766         break;
 767     default:
 768         qemu_log_mask(LOG_GUEST_ERROR, "PSI: xscom write at 0x%" PRIx64 "\n",
 769                       addr);
 770     }
 771 }
 772
 773 static const MemoryRegionOps pnv_psi_p9_xscom_ops = {
 774     .read = pnv_psi_p9_xscom_read,
 775     .write = pnv_psi_p9_xscom_write,
 776     .endianness = DEVICE_BIG_ENDIAN,
 777     .valid = {
 778         .min_access_size = 8,
 779         .max_access_size = 8,
 780     },
 781     .impl = {
 782         .min_access_size = 8,
 783         .max_access_size = 8,
 784     }
 785 };
 786
 787 static void pnv_psi_power9_irq_set(PnvPsi *psi, int irq, bool state)
 788 {
 789     uint64_t irq_method = psi->regs[PSIHB_REG(PSIHB9_INTERRUPT_CONTROL)];
 790
 791     if (irq > PSIHB9_NUM_IRQS) {
 792         qemu_log_mask(LOG_GUEST_ERROR, "PSI: Unsupported irq %d\n", irq);
 793         return;
 794     }
 795
 796     if (irq_method & PSIHB9_IRQ_METHOD) {
 797         qemu_log_mask(LOG_GUEST_ERROR, "PSI: LSI IRQ method no supported\n");
 798         return;
 799     }
 800
 801     /* Update LSI levels */
 802     if (state) {
 803         psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] |= PPC_BIT(irq);
 804     } else {
 805         psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] &= ~PPC_BIT(irq);
 806     }
 807
 808     qemu_set_irq(psi->qirqs[irq], state);
 809 }
 810
 811 static void pnv_psi_power9_reset(void *dev)
 812 {
 813     Pnv9Psi *psi = PNV9_PSI(dev);
 814
 815     pnv_psi_reset(dev);
 816
 817     if (memory_region_is_mapped(&psi->source.esb_mmio)) {
 818         memory_region_del_subregion(get_system_memory(), &psi->source.esb_mmio);
 819     }
 820 }
 821
 822 static void pnv_psi_power9_instance_init(Object *obj)
 823 {
 824     Pnv9Psi *psi = PNV9_PSI(obj);
 825
 826     object_initialize_child(obj, "source", &psi->source, sizeof(psi->source),
 827                             TYPE_XIVE_SOURCE, &error_abort, NULL);
 828 }
 829
 830 static void pnv_psi_power9_realize(DeviceState *dev, Error **errp)
 831 {
 832     PnvPsi *psi = PNV_PSI(dev);
 833     XiveSource *xsrc = &PNV9_PSI(psi)->source;
 834     Error *local_err = NULL;
 835     int i;
 836
 837     /* This is the only device with 4k ESB pages */
 838     object_property_set_int(OBJECT(xsrc), XIVE_ESB_4K, "shift",
 839                             &error_fatal);
 840     object_property_set_int(OBJECT(xsrc), PSIHB9_NUM_IRQS, "nr-irqs",
 841                             &error_fatal);
 842     object_property_add_const_link(OBJECT(xsrc), "xive", OBJECT(psi),
 843                                    &error_fatal);
 844     object_property_set_bool(OBJECT(xsrc), true, "realized", &local_err);
 845     if (local_err) {
 846         error_propagate(errp, local_err);
 847         return;
 848     }
 849
 850     for (i = 0; i < xsrc->nr_irqs; i++) {
 851         xive_source_irq_set_lsi(xsrc, i);
 852     }
 853
 854     psi->qirqs = qemu_allocate_irqs(xive_source_set_irq, xsrc, xsrc->nr_irqs);
 855
 856     /* XSCOM region for PSI registers */
 857     pnv_xscom_region_init(&psi->xscom_regs, OBJECT(dev), &pnv_psi_p9_xscom_ops,
 858                 psi, "xscom-psi", PNV9_XSCOM_PSIHB_SIZE);
 859
 860     /* MMIO region for PSI registers */
 861     memory_region_init_io(&psi->regs_mr, OBJECT(dev), &pnv_psi_p9_mmio_ops, psi,
 862                           "psihb", PNV9_PSIHB_SIZE);
 863
 864     pnv_psi_set_bar(psi, psi->bar | PSIHB_BAR_EN);
 865
 866     qemu_register_reset(pnv_psi_power9_reset, dev);
 867 }
 868
 869 static void pnv_psi_power9_class_init(ObjectClass *klass, void *data)
 870 {
 871     DeviceClass *dc = DEVICE_CLASS(klass);
 872     PnvPsiClass *ppc = PNV_PSI_CLASS(klass);
 873     XiveNotifierClass *xfc = XIVE_NOTIFIER_CLASS(klass);
 874
 875     dc->desc    = "PowerNV PSI Controller POWER9";
 876     dc->realize = pnv_psi_power9_realize;
 877
 878     ppc->chip_type  = PNV_CHIP_POWER9;
 879     ppc->xscom_pcba = PNV9_XSCOM_PSIHB_BASE;
 880     ppc->xscom_size = PNV9_XSCOM_PSIHB_SIZE;
 881     ppc->bar_mask   = PSIHB9_BAR_MASK;
 882     ppc->irq_set    = pnv_psi_power9_irq_set;
 883
 884     xfc->notify      = pnv_psi_notify;
 885 }
 886
 887 static const TypeInfo pnv_psi_power9_info = {
 888     .name          = TYPE_PNV9_PSI,
 889     .parent        = TYPE_PNV_PSI,
 890     .instance_size = sizeof(Pnv9Psi),
 891     .instance_init = pnv_psi_power9_instance_init,
 892     .class_init    = pnv_psi_power9_class_init,
 893     .interfaces = (InterfaceInfo[]) {
 894             { TYPE_XIVE_NOTIFIER },
 895             { },
 896     },
 897 };
 898
 899 static void pnv_psi_class_init(ObjectClass *klass, void *data)
 900 {
 901     DeviceClass *dc = DEVICE_CLASS(klass);
 902     PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass);
 903
 904     xdc->dt_xscom = pnv_psi_dt_xscom;
 905
 906     dc->desc = "PowerNV PSI Controller";
 907     dc->props = pnv_psi_properties;
 908 }
 909
 910 static const TypeInfo pnv_psi_info = {
 911     .name          = TYPE_PNV_PSI,
 912     .parent        = TYPE_SYS_BUS_DEVICE,
 913     .instance_size = sizeof(PnvPsi),
 914     .class_init    = pnv_psi_class_init,
 915     .class_size    = sizeof(PnvPsiClass),
 916     .abstract      = true,
 917     .interfaces    = (InterfaceInfo[]) {
 918         { TYPE_PNV_XSCOM_INTERFACE },
 919         { }
 920     }
 921 };
 922
 923 static void pnv_psi_register_types(void)
 924 {
 925     type_register_static(&pnv_psi_info);
 926     type_register_static(&pnv_psi_power8_info);
 927     type_register_static(&pnv_psi_power9_info);
 928 }
 929
 930 type_init(pnv_psi_register_types);
 931
 932 void pnv_psi_pic_print_info(Pnv9Psi *psi9, Monitor *mon)
 933 {
 934     PnvPsi *psi = PNV_PSI(psi9);
 935
 936     uint32_t offset =
 937         (psi->regs[PSIHB_REG(PSIHB9_IVT_OFFSET)] >> PSIHB9_IVT_OFF_SHIFT);
 938
 939     monitor_printf(mon, "PSIHB Source %08x .. %08x\n",
 940                   offset, offset + psi9->source.nr_irqs - 1);
 941     xive_source_pic_print_info(&psi9->source, offset, mon);
 942 }