2 * Copyright (c) 2015 Jean-Christophe Dubois <jcd@tribudubois.net>
6 * Based on hw/arm/fsl-imx31.c
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
22 #include "qemu/osdep.h"
23 #include "qapi/error.h"
24 #include "hw/arm/fsl-imx6.h"
25 #include "hw/usb/imx-usb-phy.h"
26 #include "hw/boards.h"
27 #include "hw/qdev-properties.h"
28 #include "sysemu/sysemu.h"
29 #include "chardev/char.h"
30 #include "qemu/error-report.h"
31 #include "qemu/module.h"
33 #define IMX6_ESDHC_CAPABILITIES 0x057834b4
37 static void fsl_imx6_init(Object
*obj
)
39 MachineState
*ms
= MACHINE(qdev_get_machine());
40 FslIMX6State
*s
= FSL_IMX6(obj
);
44 for (i
= 0; i
< MIN(ms
->smp
.cpus
, FSL_IMX6_NUM_CPUS
); i
++) {
45 snprintf(name
, NAME_SIZE
, "cpu%d", i
);
46 object_initialize_child(obj
, name
, &s
->cpu
[i
],
47 ARM_CPU_TYPE_NAME("cortex-a9"));
50 object_initialize_child(obj
, "a9mpcore", &s
->a9mpcore
, TYPE_A9MPCORE_PRIV
);
52 object_initialize_child(obj
, "ccm", &s
->ccm
, TYPE_IMX6_CCM
);
54 object_initialize_child(obj
, "src", &s
->src
, TYPE_IMX6_SRC
);
56 for (i
= 0; i
< FSL_IMX6_NUM_UARTS
; i
++) {
57 snprintf(name
, NAME_SIZE
, "uart%d", i
+ 1);
58 object_initialize_child(obj
, name
, &s
->uart
[i
], TYPE_IMX_SERIAL
);
61 object_initialize_child(obj
, "gpt", &s
->gpt
, TYPE_IMX6_GPT
);
63 for (i
= 0; i
< FSL_IMX6_NUM_EPITS
; i
++) {
64 snprintf(name
, NAME_SIZE
, "epit%d", i
+ 1);
65 object_initialize_child(obj
, name
, &s
->epit
[i
], TYPE_IMX_EPIT
);
68 for (i
= 0; i
< FSL_IMX6_NUM_I2CS
; i
++) {
69 snprintf(name
, NAME_SIZE
, "i2c%d", i
+ 1);
70 object_initialize_child(obj
, name
, &s
->i2c
[i
], TYPE_IMX_I2C
);
73 for (i
= 0; i
< FSL_IMX6_NUM_GPIOS
; i
++) {
74 snprintf(name
, NAME_SIZE
, "gpio%d", i
+ 1);
75 object_initialize_child(obj
, name
, &s
->gpio
[i
], TYPE_IMX_GPIO
);
78 for (i
= 0; i
< FSL_IMX6_NUM_ESDHCS
; i
++) {
79 snprintf(name
, NAME_SIZE
, "sdhc%d", i
+ 1);
80 object_initialize_child(obj
, name
, &s
->esdhc
[i
], TYPE_IMX_USDHC
);
83 for (i
= 0; i
< FSL_IMX6_NUM_USB_PHYS
; i
++) {
84 snprintf(name
, NAME_SIZE
, "usbphy%d", i
);
85 object_initialize_child(obj
, name
, &s
->usbphy
[i
], TYPE_IMX_USBPHY
);
87 for (i
= 0; i
< FSL_IMX6_NUM_USBS
; i
++) {
88 snprintf(name
, NAME_SIZE
, "usb%d", i
);
89 object_initialize_child(obj
, name
, &s
->usb
[i
], TYPE_CHIPIDEA
);
92 for (i
= 0; i
< FSL_IMX6_NUM_ECSPIS
; i
++) {
93 snprintf(name
, NAME_SIZE
, "spi%d", i
+ 1);
94 object_initialize_child(obj
, name
, &s
->spi
[i
], TYPE_IMX_SPI
);
96 for (i
= 0; i
< FSL_IMX6_NUM_WDTS
; i
++) {
97 snprintf(name
, NAME_SIZE
, "wdt%d", i
);
98 object_initialize_child(obj
, name
, &s
->wdt
[i
], TYPE_IMX2_WDT
);
102 object_initialize_child(obj
, "eth", &s
->eth
, TYPE_IMX_ENET
);
105 static void fsl_imx6_realize(DeviceState
*dev
, Error
**errp
)
107 MachineState
*ms
= MACHINE(qdev_get_machine());
108 FslIMX6State
*s
= FSL_IMX6(dev
);
111 unsigned int smp_cpus
= ms
->smp
.cpus
;
113 if (smp_cpus
> FSL_IMX6_NUM_CPUS
) {
114 error_setg(errp
, "%s: Only %d CPUs are supported (%d requested)",
115 TYPE_FSL_IMX6
, FSL_IMX6_NUM_CPUS
, smp_cpus
);
119 for (i
= 0; i
< smp_cpus
; i
++) {
121 /* On uniprocessor, the CBAR is set to 0 */
123 object_property_set_int(OBJECT(&s
->cpu
[i
]), FSL_IMX6_A9MPCORE_ADDR
,
124 "reset-cbar", &error_abort
);
127 /* All CPU but CPU 0 start in power off mode */
129 object_property_set_bool(OBJECT(&s
->cpu
[i
]), true,
130 "start-powered-off", &error_abort
);
133 qdev_realize(DEVICE(&s
->cpu
[i
]), NULL
, &err
);
135 error_propagate(errp
, err
);
140 object_property_set_int(OBJECT(&s
->a9mpcore
), smp_cpus
, "num-cpu",
143 object_property_set_int(OBJECT(&s
->a9mpcore
),
144 FSL_IMX6_MAX_IRQ
+ GIC_INTERNAL
, "num-irq",
147 sysbus_realize(SYS_BUS_DEVICE(&s
->a9mpcore
), &err
);
149 error_propagate(errp
, err
);
152 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->a9mpcore
), 0, FSL_IMX6_A9MPCORE_ADDR
);
154 for (i
= 0; i
< smp_cpus
; i
++) {
155 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->a9mpcore
), i
,
156 qdev_get_gpio_in(DEVICE(&s
->cpu
[i
]), ARM_CPU_IRQ
));
157 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->a9mpcore
), i
+ smp_cpus
,
158 qdev_get_gpio_in(DEVICE(&s
->cpu
[i
]), ARM_CPU_FIQ
));
161 sysbus_realize(SYS_BUS_DEVICE(&s
->ccm
), &err
);
163 error_propagate(errp
, err
);
166 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->ccm
), 0, FSL_IMX6_CCM_ADDR
);
168 sysbus_realize(SYS_BUS_DEVICE(&s
->src
), &err
);
170 error_propagate(errp
, err
);
173 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->src
), 0, FSL_IMX6_SRC_ADDR
);
175 /* Initialize all UARTs */
176 for (i
= 0; i
< FSL_IMX6_NUM_UARTS
; i
++) {
177 static const struct {
180 } serial_table
[FSL_IMX6_NUM_UARTS
] = {
181 { FSL_IMX6_UART1_ADDR
, FSL_IMX6_UART1_IRQ
},
182 { FSL_IMX6_UART2_ADDR
, FSL_IMX6_UART2_IRQ
},
183 { FSL_IMX6_UART3_ADDR
, FSL_IMX6_UART3_IRQ
},
184 { FSL_IMX6_UART4_ADDR
, FSL_IMX6_UART4_IRQ
},
185 { FSL_IMX6_UART5_ADDR
, FSL_IMX6_UART5_IRQ
},
188 qdev_prop_set_chr(DEVICE(&s
->uart
[i
]), "chardev", serial_hd(i
));
190 sysbus_realize(SYS_BUS_DEVICE(&s
->uart
[i
]), &err
);
192 error_propagate(errp
, err
);
196 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->uart
[i
]), 0, serial_table
[i
].addr
);
197 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->uart
[i
]), 0,
198 qdev_get_gpio_in(DEVICE(&s
->a9mpcore
),
199 serial_table
[i
].irq
));
202 s
->gpt
.ccm
= IMX_CCM(&s
->ccm
);
204 sysbus_realize(SYS_BUS_DEVICE(&s
->gpt
), &err
);
206 error_propagate(errp
, err
);
210 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->gpt
), 0, FSL_IMX6_GPT_ADDR
);
211 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gpt
), 0,
212 qdev_get_gpio_in(DEVICE(&s
->a9mpcore
),
215 /* Initialize all EPIT timers */
216 for (i
= 0; i
< FSL_IMX6_NUM_EPITS
; i
++) {
217 static const struct {
220 } epit_table
[FSL_IMX6_NUM_EPITS
] = {
221 { FSL_IMX6_EPIT1_ADDR
, FSL_IMX6_EPIT1_IRQ
},
222 { FSL_IMX6_EPIT2_ADDR
, FSL_IMX6_EPIT2_IRQ
},
225 s
->epit
[i
].ccm
= IMX_CCM(&s
->ccm
);
227 sysbus_realize(SYS_BUS_DEVICE(&s
->epit
[i
]), &err
);
229 error_propagate(errp
, err
);
233 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->epit
[i
]), 0, epit_table
[i
].addr
);
234 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->epit
[i
]), 0,
235 qdev_get_gpio_in(DEVICE(&s
->a9mpcore
),
239 /* Initialize all I2C */
240 for (i
= 0; i
< FSL_IMX6_NUM_I2CS
; i
++) {
241 static const struct {
244 } i2c_table
[FSL_IMX6_NUM_I2CS
] = {
245 { FSL_IMX6_I2C1_ADDR
, FSL_IMX6_I2C1_IRQ
},
246 { FSL_IMX6_I2C2_ADDR
, FSL_IMX6_I2C2_IRQ
},
247 { FSL_IMX6_I2C3_ADDR
, FSL_IMX6_I2C3_IRQ
}
250 sysbus_realize(SYS_BUS_DEVICE(&s
->i2c
[i
]), &err
);
252 error_propagate(errp
, err
);
256 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->i2c
[i
]), 0, i2c_table
[i
].addr
);
257 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->i2c
[i
]), 0,
258 qdev_get_gpio_in(DEVICE(&s
->a9mpcore
),
262 /* Initialize all GPIOs */
263 for (i
= 0; i
< FSL_IMX6_NUM_GPIOS
; i
++) {
264 static const struct {
266 unsigned int irq_low
;
267 unsigned int irq_high
;
268 } gpio_table
[FSL_IMX6_NUM_GPIOS
] = {
271 FSL_IMX6_GPIO1_LOW_IRQ
,
272 FSL_IMX6_GPIO1_HIGH_IRQ
276 FSL_IMX6_GPIO2_LOW_IRQ
,
277 FSL_IMX6_GPIO2_HIGH_IRQ
281 FSL_IMX6_GPIO3_LOW_IRQ
,
282 FSL_IMX6_GPIO3_HIGH_IRQ
286 FSL_IMX6_GPIO4_LOW_IRQ
,
287 FSL_IMX6_GPIO4_HIGH_IRQ
291 FSL_IMX6_GPIO5_LOW_IRQ
,
292 FSL_IMX6_GPIO5_HIGH_IRQ
296 FSL_IMX6_GPIO6_LOW_IRQ
,
297 FSL_IMX6_GPIO6_HIGH_IRQ
301 FSL_IMX6_GPIO7_LOW_IRQ
,
302 FSL_IMX6_GPIO7_HIGH_IRQ
306 object_property_set_bool(OBJECT(&s
->gpio
[i
]), true, "has-edge-sel",
308 object_property_set_bool(OBJECT(&s
->gpio
[i
]), true, "has-upper-pin-irq",
310 sysbus_realize(SYS_BUS_DEVICE(&s
->gpio
[i
]), &err
);
312 error_propagate(errp
, err
);
316 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->gpio
[i
]), 0, gpio_table
[i
].addr
);
317 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gpio
[i
]), 0,
318 qdev_get_gpio_in(DEVICE(&s
->a9mpcore
),
319 gpio_table
[i
].irq_low
));
320 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gpio
[i
]), 1,
321 qdev_get_gpio_in(DEVICE(&s
->a9mpcore
),
322 gpio_table
[i
].irq_high
));
325 /* Initialize all SDHC */
326 for (i
= 0; i
< FSL_IMX6_NUM_ESDHCS
; i
++) {
327 static const struct {
330 } esdhc_table
[FSL_IMX6_NUM_ESDHCS
] = {
331 { FSL_IMX6_uSDHC1_ADDR
, FSL_IMX6_uSDHC1_IRQ
},
332 { FSL_IMX6_uSDHC2_ADDR
, FSL_IMX6_uSDHC2_IRQ
},
333 { FSL_IMX6_uSDHC3_ADDR
, FSL_IMX6_uSDHC3_IRQ
},
334 { FSL_IMX6_uSDHC4_ADDR
, FSL_IMX6_uSDHC4_IRQ
},
337 /* UHS-I SDIO3.0 SDR104 1.8V ADMA */
338 object_property_set_uint(OBJECT(&s
->esdhc
[i
]), 3, "sd-spec-version",
340 object_property_set_uint(OBJECT(&s
->esdhc
[i
]), IMX6_ESDHC_CAPABILITIES
,
343 object_property_set_uint(OBJECT(&s
->esdhc
[i
]), SDHCI_VENDOR_IMX
,
346 sysbus_realize(SYS_BUS_DEVICE(&s
->esdhc
[i
]), &err
);
348 error_propagate(errp
, err
);
351 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->esdhc
[i
]), 0, esdhc_table
[i
].addr
);
352 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->esdhc
[i
]), 0,
353 qdev_get_gpio_in(DEVICE(&s
->a9mpcore
),
354 esdhc_table
[i
].irq
));
358 for (i
= 0; i
< FSL_IMX6_NUM_USB_PHYS
; i
++) {
359 sysbus_realize(SYS_BUS_DEVICE(&s
->usbphy
[i
]), &error_abort
);
360 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->usbphy
[i
]), 0,
361 FSL_IMX6_USBPHY1_ADDR
+ i
* 0x1000);
363 for (i
= 0; i
< FSL_IMX6_NUM_USBS
; i
++) {
364 static const int FSL_IMX6_USBn_IRQ
[] = {
365 FSL_IMX6_USB_OTG_IRQ
,
366 FSL_IMX6_USB_HOST1_IRQ
,
367 FSL_IMX6_USB_HOST2_IRQ
,
368 FSL_IMX6_USB_HOST3_IRQ
,
371 sysbus_realize(SYS_BUS_DEVICE(&s
->usb
[i
]), &error_abort
);
372 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->usb
[i
]), 0,
373 FSL_IMX6_USBOH3_USB_ADDR
+ i
* 0x200);
374 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->usb
[i
]), 0,
375 qdev_get_gpio_in(DEVICE(&s
->a9mpcore
),
376 FSL_IMX6_USBn_IRQ
[i
]));
379 /* Initialize all ECSPI */
380 for (i
= 0; i
< FSL_IMX6_NUM_ECSPIS
; i
++) {
381 static const struct {
384 } spi_table
[FSL_IMX6_NUM_ECSPIS
] = {
385 { FSL_IMX6_eCSPI1_ADDR
, FSL_IMX6_ECSPI1_IRQ
},
386 { FSL_IMX6_eCSPI2_ADDR
, FSL_IMX6_ECSPI2_IRQ
},
387 { FSL_IMX6_eCSPI3_ADDR
, FSL_IMX6_ECSPI3_IRQ
},
388 { FSL_IMX6_eCSPI4_ADDR
, FSL_IMX6_ECSPI4_IRQ
},
389 { FSL_IMX6_eCSPI5_ADDR
, FSL_IMX6_ECSPI5_IRQ
},
392 /* Initialize the SPI */
393 sysbus_realize(SYS_BUS_DEVICE(&s
->spi
[i
]), &err
);
395 error_propagate(errp
, err
);
399 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->spi
[i
]), 0, spi_table
[i
].addr
);
400 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->spi
[i
]), 0,
401 qdev_get_gpio_in(DEVICE(&s
->a9mpcore
),
405 qdev_set_nic_properties(DEVICE(&s
->eth
), &nd_table
[0]);
406 sysbus_realize(SYS_BUS_DEVICE(&s
->eth
), &err
);
408 error_propagate(errp
, err
);
411 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->eth
), 0, FSL_IMX6_ENET_ADDR
);
412 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->eth
), 0,
413 qdev_get_gpio_in(DEVICE(&s
->a9mpcore
),
414 FSL_IMX6_ENET_MAC_IRQ
));
415 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->eth
), 1,
416 qdev_get_gpio_in(DEVICE(&s
->a9mpcore
),
417 FSL_IMX6_ENET_MAC_1588_IRQ
));
422 for (i
= 0; i
< FSL_IMX6_NUM_WDTS
; i
++) {
423 static const hwaddr FSL_IMX6_WDOGn_ADDR
[FSL_IMX6_NUM_WDTS
] = {
427 static const int FSL_IMX6_WDOGn_IRQ
[FSL_IMX6_NUM_WDTS
] = {
432 object_property_set_bool(OBJECT(&s
->wdt
[i
]), true, "pretimeout-support",
434 sysbus_realize(SYS_BUS_DEVICE(&s
->wdt
[i
]), &error_abort
);
436 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->wdt
[i
]), 0, FSL_IMX6_WDOGn_ADDR
[i
]);
437 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->wdt
[i
]), 0,
438 qdev_get_gpio_in(DEVICE(&s
->a9mpcore
),
439 FSL_IMX6_WDOGn_IRQ
[i
]));
443 memory_region_init_rom(&s
->rom
, OBJECT(dev
), "imx6.rom",
444 FSL_IMX6_ROM_SIZE
, &err
);
446 error_propagate(errp
, err
);
449 memory_region_add_subregion(get_system_memory(), FSL_IMX6_ROM_ADDR
,
453 memory_region_init_rom(&s
->caam
, OBJECT(dev
), "imx6.caam",
454 FSL_IMX6_CAAM_MEM_SIZE
, &err
);
456 error_propagate(errp
, err
);
459 memory_region_add_subregion(get_system_memory(), FSL_IMX6_CAAM_MEM_ADDR
,
463 memory_region_init_ram(&s
->ocram
, NULL
, "imx6.ocram", FSL_IMX6_OCRAM_SIZE
,
466 error_propagate(errp
, err
);
469 memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ADDR
,
472 /* internal OCRAM (256 KB) is aliased over 1 MB */
473 memory_region_init_alias(&s
->ocram_alias
, OBJECT(dev
), "imx6.ocram_alias",
474 &s
->ocram
, 0, FSL_IMX6_OCRAM_ALIAS_SIZE
);
475 memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ALIAS_ADDR
,
479 static void fsl_imx6_class_init(ObjectClass
*oc
, void *data
)
481 DeviceClass
*dc
= DEVICE_CLASS(oc
);
483 dc
->realize
= fsl_imx6_realize
;
484 dc
->desc
= "i.MX6 SOC";
485 /* Reason: Uses serial_hd() in the realize() function */
486 dc
->user_creatable
= false;
489 static const TypeInfo fsl_imx6_type_info
= {
490 .name
= TYPE_FSL_IMX6
,
491 .parent
= TYPE_DEVICE
,
492 .instance_size
= sizeof(FslIMX6State
),
493 .instance_init
= fsl_imx6_init
,
494 .class_init
= fsl_imx6_class_init
,
497 static void fsl_imx6_register_types(void)
499 type_register_static(&fsl_imx6_type_info
);
502 type_init(fsl_imx6_register_types
)