hw/arm/fsl-imx25.c

   1 /*
   2  * Copyright (c) 2013 Jean-Christophe Dubois <jcd@tribudubois.net>
   3  *
   4  * i.MX25 SOC emulation.
   5  *
   6  * Based on hw/arm/xlnx-zynqmp.c
   7  *
   8  * Copyright (C) 2015 Xilinx Inc
   9  * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the
  13  *  Free Software Foundation; either version 2 of the License, or
  14  *  (at your option) any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  19  *  for more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along
  22  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qapi/error.h"
  27 #include "cpu.h"
  28 #include "hw/arm/fsl-imx25.h"
  29 #include "sysemu/sysemu.h"
  30 #include "exec/address-spaces.h"
  31 #include "hw/qdev-properties.h"
  32 #include "chardev/char.h"
  33
  34 #define IMX25_ESDHC_CAPABILITIES     0x07e20000
  35
  36 static void fsl_imx25_init(Object *obj)
  37 {
  38     FslIMX25State *s = FSL_IMX25(obj);
  39     int i;
  40
  41     object_initialize_child(obj, "cpu", &s->cpu, ARM_CPU_TYPE_NAME("arm926"));
  42
  43     object_initialize_child(obj, "avic", &s->avic, TYPE_IMX_AVIC);
  44
  45     object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX25_CCM);
  46
  47     for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) {
  48         object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_IMX_SERIAL);
  49     }
  50
  51     for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) {
  52         object_initialize_child(obj, "gpt[*]", &s->gpt[i], TYPE_IMX25_GPT);
  53     }
  54
  55     for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) {
  56         object_initialize_child(obj, "epit[*]", &s->epit[i], TYPE_IMX_EPIT);
  57     }
  58
  59     object_initialize_child(obj, "fec", &s->fec, TYPE_IMX_FEC);
  60
  61     object_initialize_child(obj, "rngc", &s->rngc, TYPE_IMX_RNGC);
  62
  63     for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) {
  64         object_initialize_child(obj, "i2c[*]", &s->i2c[i], TYPE_IMX_I2C);
  65     }
  66
  67     for (i = 0; i < FSL_IMX25_NUM_GPIOS; i++) {
  68         object_initialize_child(obj, "gpio[*]", &s->gpio[i], TYPE_IMX_GPIO);
  69     }
  70
  71     for (i = 0; i < FSL_IMX25_NUM_ESDHCS; i++) {
  72         object_initialize_child(obj, "sdhc[*]", &s->esdhc[i], TYPE_IMX_USDHC);
  73     }
  74
  75     for (i = 0; i < FSL_IMX25_NUM_USBS; i++) {
  76         object_initialize_child(obj, "usb[*]", &s->usb[i], TYPE_CHIPIDEA);
  77     }
  78
  79     object_initialize_child(obj, "wdt", &s->wdt, TYPE_IMX2_WDT);
  80 }
  81
  82 static void fsl_imx25_realize(DeviceState *dev, Error **errp)
  83 {
  84     FslIMX25State *s = FSL_IMX25(dev);
  85     uint8_t i;
  86     Error *err = NULL;
  87
  88     qdev_realize(DEVICE(&s->cpu), NULL, &err);
  89     if (err) {
  90         error_propagate(errp, err);
  91         return;
  92     }
  93
  94     sysbus_realize(SYS_BUS_DEVICE(&s->avic), &err);
  95     if (err) {
  96         error_propagate(errp, err);
  97         return;
  98     }
  99     sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX25_AVIC_ADDR);
 100     sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0,
 101                        qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
 102     sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1,
 103                        qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
 104
 105     sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &err);
 106     if (err) {
 107         error_propagate(errp, err);
 108         return;
 109     }
 110     sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX25_CCM_ADDR);
 111
 112     /* Initialize all UARTs */
 113     for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) {
 114         static const struct {
 115             hwaddr addr;
 116             unsigned int irq;
 117         } serial_table[FSL_IMX25_NUM_UARTS] = {
 118             { FSL_IMX25_UART1_ADDR, FSL_IMX25_UART1_IRQ },
 119             { FSL_IMX25_UART2_ADDR, FSL_IMX25_UART2_IRQ },
 120             { FSL_IMX25_UART3_ADDR, FSL_IMX25_UART3_IRQ },
 121             { FSL_IMX25_UART4_ADDR, FSL_IMX25_UART4_IRQ },
 122             { FSL_IMX25_UART5_ADDR, FSL_IMX25_UART5_IRQ }
 123         };
 124
 125         qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
 126
 127         sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), &err);
 128         if (err) {
 129             error_propagate(errp, err);
 130             return;
 131         }
 132         sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
 133         sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
 134                            qdev_get_gpio_in(DEVICE(&s->avic),
 135                                             serial_table[i].irq));
 136     }
 137
 138     /* Initialize all GPT timers */
 139     for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) {
 140         static const struct {
 141             hwaddr addr;
 142             unsigned int irq;
 143         } gpt_table[FSL_IMX25_NUM_GPTS] = {
 144             { FSL_IMX25_GPT1_ADDR, FSL_IMX25_GPT1_IRQ },
 145             { FSL_IMX25_GPT2_ADDR, FSL_IMX25_GPT2_IRQ },
 146             { FSL_IMX25_GPT3_ADDR, FSL_IMX25_GPT3_IRQ },
 147             { FSL_IMX25_GPT4_ADDR, FSL_IMX25_GPT4_IRQ }
 148         };
 149
 150         s->gpt[i].ccm = IMX_CCM(&s->ccm);
 151
 152         sysbus_realize(SYS_BUS_DEVICE(&s->gpt[i]), &err);
 153         if (err) {
 154             error_propagate(errp, err);
 155             return;
 156         }
 157         sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, gpt_table[i].addr);
 158         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0,
 159                            qdev_get_gpio_in(DEVICE(&s->avic),
 160                                             gpt_table[i].irq));
 161     }
 162
 163     /* Initialize all EPIT timers */
 164     for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) {
 165         static const struct {
 166             hwaddr addr;
 167             unsigned int irq;
 168         } epit_table[FSL_IMX25_NUM_EPITS] = {
 169             { FSL_IMX25_EPIT1_ADDR, FSL_IMX25_EPIT1_IRQ },
 170             { FSL_IMX25_EPIT2_ADDR, FSL_IMX25_EPIT2_IRQ }
 171         };
 172
 173         s->epit[i].ccm = IMX_CCM(&s->ccm);
 174
 175         sysbus_realize(SYS_BUS_DEVICE(&s->epit[i]), &err);
 176         if (err) {
 177             error_propagate(errp, err);
 178             return;
 179         }
 180         sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr);
 181         sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
 182                            qdev_get_gpio_in(DEVICE(&s->avic),
 183                                             epit_table[i].irq));
 184     }
 185
 186     qdev_set_nic_properties(DEVICE(&s->fec), &nd_table[0]);
 187
 188     sysbus_realize(SYS_BUS_DEVICE(&s->fec), &err);
 189     if (err) {
 190         error_propagate(errp, err);
 191         return;
 192     }
 193     sysbus_mmio_map(SYS_BUS_DEVICE(&s->fec), 0, FSL_IMX25_FEC_ADDR);
 194     sysbus_connect_irq(SYS_BUS_DEVICE(&s->fec), 0,
 195                        qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX25_FEC_IRQ));
 196
 197     sysbus_realize(SYS_BUS_DEVICE(&s->rngc), &err);
 198     if (err) {
 199         error_propagate(errp, err);
 200         return;
 201     }
 202     sysbus_mmio_map(SYS_BUS_DEVICE(&s->rngc), 0, FSL_IMX25_RNGC_ADDR);
 203     sysbus_connect_irq(SYS_BUS_DEVICE(&s->rngc), 0,
 204                        qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX25_RNGC_IRQ));
 205
 206     /* Initialize all I2C */
 207     for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) {
 208         static const struct {
 209             hwaddr addr;
 210             unsigned int irq;
 211         } i2c_table[FSL_IMX25_NUM_I2CS] = {
 212             { FSL_IMX25_I2C1_ADDR, FSL_IMX25_I2C1_IRQ },
 213             { FSL_IMX25_I2C2_ADDR, FSL_IMX25_I2C2_IRQ },
 214             { FSL_IMX25_I2C3_ADDR, FSL_IMX25_I2C3_IRQ }
 215         };
 216
 217         sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), &err);
 218         if (err) {
 219             error_propagate(errp, err);
 220             return;
 221         }
 222         sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
 223         sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
 224                            qdev_get_gpio_in(DEVICE(&s->avic),
 225                                             i2c_table[i].irq));
 226     }
 227
 228     /* Initialize all GPIOs */
 229     for (i = 0; i < FSL_IMX25_NUM_GPIOS; i++) {
 230         static const struct {
 231             hwaddr addr;
 232             unsigned int irq;
 233         } gpio_table[FSL_IMX25_NUM_GPIOS] = {
 234             { FSL_IMX25_GPIO1_ADDR, FSL_IMX25_GPIO1_IRQ },
 235             { FSL_IMX25_GPIO2_ADDR, FSL_IMX25_GPIO2_IRQ },
 236             { FSL_IMX25_GPIO3_ADDR, FSL_IMX25_GPIO3_IRQ },
 237             { FSL_IMX25_GPIO4_ADDR, FSL_IMX25_GPIO4_IRQ }
 238         };
 239
 240         sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), &err);
 241         if (err) {
 242             error_propagate(errp, err);
 243             return;
 244         }
 245         sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
 246         /* Connect GPIO IRQ to PIC */
 247         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
 248                            qdev_get_gpio_in(DEVICE(&s->avic),
 249                                             gpio_table[i].irq));
 250     }
 251
 252     /* Initialize all SDHC */
 253     for (i = 0; i < FSL_IMX25_NUM_ESDHCS; i++) {
 254         static const struct {
 255             hwaddr addr;
 256             unsigned int irq;
 257         } esdhc_table[FSL_IMX25_NUM_ESDHCS] = {
 258             { FSL_IMX25_ESDHC1_ADDR, FSL_IMX25_ESDHC1_IRQ },
 259             { FSL_IMX25_ESDHC2_ADDR, FSL_IMX25_ESDHC2_IRQ },
 260         };
 261
 262         object_property_set_uint(OBJECT(&s->esdhc[i]), 2, "sd-spec-version",
 263                                  &error_abort);
 264         object_property_set_uint(OBJECT(&s->esdhc[i]), IMX25_ESDHC_CAPABILITIES,
 265                                  "capareg",
 266                                  &error_abort);
 267         object_property_set_uint(OBJECT(&s->esdhc[i]), SDHCI_VENDOR_IMX,
 268                                  "vendor",
 269                                  &error_abort);
 270         sysbus_realize(SYS_BUS_DEVICE(&s->esdhc[i]), &err);
 271         if (err) {
 272             error_propagate(errp, err);
 273             return;
 274         }
 275         sysbus_mmio_map(SYS_BUS_DEVICE(&s->esdhc[i]), 0, esdhc_table[i].addr);
 276         sysbus_connect_irq(SYS_BUS_DEVICE(&s->esdhc[i]), 0,
 277                            qdev_get_gpio_in(DEVICE(&s->avic),
 278                                             esdhc_table[i].irq));
 279     }
 280
 281     /* USB */
 282     for (i = 0; i < FSL_IMX25_NUM_USBS; i++) {
 283         static const struct {
 284             hwaddr addr;
 285             unsigned int irq;
 286         } usb_table[FSL_IMX25_NUM_USBS] = {
 287             { FSL_IMX25_USB1_ADDR, FSL_IMX25_USB1_IRQ },
 288             { FSL_IMX25_USB2_ADDR, FSL_IMX25_USB2_IRQ },
 289         };
 290
 291         sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort);
 292         sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, usb_table[i].addr);
 293         sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
 294                            qdev_get_gpio_in(DEVICE(&s->avic),
 295                                             usb_table[i].irq));
 296     }
 297
 298     /* Watchdog */
 299     object_property_set_bool(OBJECT(&s->wdt), true, "pretimeout-support",
 300                              &error_abort);
 301     sysbus_realize(SYS_BUS_DEVICE(&s->wdt), &error_abort);
 302     sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt), 0, FSL_IMX25_WDT_ADDR);
 303     sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt), 0,
 304                                       qdev_get_gpio_in(DEVICE(&s->avic),
 305                                                        FSL_IMX25_WDT_IRQ));
 306
 307     /* initialize 2 x 16 KB ROM */
 308     memory_region_init_rom(&s->rom[0], OBJECT(dev), "imx25.rom0",
 309                            FSL_IMX25_ROM0_SIZE, &err);
 310     if (err) {
 311         error_propagate(errp, err);
 312         return;
 313     }
 314     memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM0_ADDR,
 315                                 &s->rom[0]);
 316     memory_region_init_rom(&s->rom[1], OBJECT(dev), "imx25.rom1",
 317                            FSL_IMX25_ROM1_SIZE, &err);
 318     if (err) {
 319         error_propagate(errp, err);
 320         return;
 321     }
 322     memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM1_ADDR,
 323                                 &s->rom[1]);
 324
 325     /* initialize internal RAM (128 KB) */
 326     memory_region_init_ram(&s->iram, NULL, "imx25.iram", FSL_IMX25_IRAM_SIZE,
 327                            &err);
 328     if (err) {
 329         error_propagate(errp, err);
 330         return;
 331     }
 332     memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ADDR,
 333                                 &s->iram);
 334
 335     /* internal RAM (128 KB) is aliased over 128 MB - 128 KB */
 336     memory_region_init_alias(&s->iram_alias, OBJECT(dev), "imx25.iram_alias",
 337                              &s->iram, 0, FSL_IMX25_IRAM_ALIAS_SIZE);
 338     memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ALIAS_ADDR,
 339                                 &s->iram_alias);
 340 }
 341
 342 static void fsl_imx25_class_init(ObjectClass *oc, void *data)
 343 {
 344     DeviceClass *dc = DEVICE_CLASS(oc);
 345
 346     dc->realize = fsl_imx25_realize;
 347     dc->desc = "i.MX25 SOC";
 348     /*
 349      * Reason: uses serial_hds in realize and the imx25 board does not
 350      * support multiple CPUs
 351      */
 352     dc->user_creatable = false;
 353 }
 354
 355 static const TypeInfo fsl_imx25_type_info = {
 356     .name = TYPE_FSL_IMX25,
 357     .parent = TYPE_DEVICE,
 358     .instance_size = sizeof(FslIMX25State),
 359     .instance_init = fsl_imx25_init,
 360     .class_init = fsl_imx25_class_init,
 361 };
 362
 363 static void fsl_imx25_register_types(void)
 364 {
 365     type_register_static(&fsl_imx25_type_info);
 366 }
 367
 368 type_init(fsl_imx25_register_types)