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Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-dec-16-2019' into...
[qemu/ar7.git] / hw / ppc / pnv.c
blob627c08e5b98529ee26b9244e9b61d584ca5a0976
1 /*
2 * QEMU PowerPC PowerNV machine model
3 *
4 * Copyright (c) 2016, IBM Corporation.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu-common.h"
22 #include "qemu/units.h"
23 #include "qapi/error.h"
24 #include "sysemu/sysemu.h"
25 #include "sysemu/numa.h"
26 #include "sysemu/reset.h"
27 #include "sysemu/runstate.h"
28 #include "sysemu/cpus.h"
29 #include "sysemu/device_tree.h"
30 #include "target/ppc/cpu.h"
31 #include "qemu/log.h"
32 #include "hw/ppc/fdt.h"
33 #include "hw/ppc/ppc.h"
34 #include "hw/ppc/pnv.h"
35 #include "hw/ppc/pnv_core.h"
36 #include "hw/loader.h"
37 #include "exec/address-spaces.h"
38 #include "qapi/visitor.h"
39 #include "monitor/monitor.h"
40 #include "hw/intc/intc.h"
41 #include "hw/ipmi/ipmi.h"
42 #include "target/ppc/mmu-hash64.h"
43
44 #include "hw/ppc/xics.h"
45 #include "hw/qdev-properties.h"
46 #include "hw/ppc/pnv_xscom.h"
47
48 #include "hw/isa/isa.h"
49 #include "hw/boards.h"
50 #include "hw/char/serial.h"
51 #include "hw/rtc/mc146818rtc.h"
52
53 #include <libfdt.h>
54
55 #define FDT_MAX_SIZE (1 * MiB)
56
57 #define FW_FILE_NAME "skiboot.lid"
58 #define FW_LOAD_ADDR 0x0
59 #define FW_MAX_SIZE (4 * MiB)
60
61 #define KERNEL_LOAD_ADDR 0x20000000
62 #define KERNEL_MAX_SIZE (256 * MiB)
63 #define INITRD_LOAD_ADDR 0x60000000
64 #define INITRD_MAX_SIZE (256 * MiB)
65
66 static const char *pnv_chip_core_typename(const PnvChip *o)
67 {
68 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o)));
69 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX);
70 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type);
71 const char *core_type = object_class_get_name(object_class_by_name(s));
72 g_free(s);
73 return core_type;
74 }
75
76 /*
77 * On Power Systems E880 (POWER8), the max cpus (threads) should be :
78 * 4 * 4 sockets * 12 cores * 8 threads = 1536
79 * Let's make it 2^11
80 */
81 #define MAX_CPUS 2048
82
83 /*
84 * Memory nodes are created by hostboot, one for each range of memory
85 * that has a different "affinity". In practice, it means one range
86 * per chip.
87 */
88 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size)
89 {
90 char *mem_name;
91 uint64_t mem_reg_property[2];
92 int off;
93
94 mem_reg_property[0] = cpu_to_be64(start);
95 mem_reg_property[1] = cpu_to_be64(size);
96
97 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start);
98 off = fdt_add_subnode(fdt, 0, mem_name);
99 g_free(mem_name);
100
101 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
102 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
103 sizeof(mem_reg_property))));
104 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id)));
105 }
106
107 static int get_cpus_node(void *fdt)
108 {
109 int cpus_offset = fdt_path_offset(fdt, "/cpus");
110
111 if (cpus_offset < 0) {
112 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
113 if (cpus_offset) {
114 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
115 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
116 }
117 }
118 _FDT(cpus_offset);
119 return cpus_offset;
120 }
121
122 /*
123 * The PowerNV cores (and threads) need to use real HW ids and not an
124 * incremental index like it has been done on other platforms. This HW
125 * id is stored in the CPU PIR, it is used to create cpu nodes in the
126 * device tree, used in XSCOM to address cores and in interrupt
127 * servers.
128 */
129 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
130 {
131 PowerPCCPU *cpu = pc->threads[0];
132 CPUState *cs = CPU(cpu);
133 DeviceClass *dc = DEVICE_GET_CLASS(cs);
134 int smt_threads = CPU_CORE(pc)->nr_threads;
135 CPUPPCState *env = &cpu->env;
136 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
137 uint32_t servers_prop[smt_threads];
138 int i;
139 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
140 0xffffffff, 0xffffffff};
141 uint32_t tbfreq = PNV_TIMEBASE_FREQ;
142 uint32_t cpufreq = 1000000000;
143 uint32_t page_sizes_prop[64];
144 size_t page_sizes_prop_size;
145 const uint8_t pa_features[] = { 24, 0,
146 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0,
147 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
148 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
149 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
150 int offset;
151 char *nodename;
152 int cpus_offset = get_cpus_node(fdt);
153
154 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir);
155 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
156 _FDT(offset);
157 g_free(nodename);
158
159 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id)));
160
161 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir)));
162 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir)));
163 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
164
165 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
166 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
167 env->dcache_line_size)));
168 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
169 env->dcache_line_size)));
170 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
171 env->icache_line_size)));
172 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
173 env->icache_line_size)));
174
175 if (pcc->l1_dcache_size) {
176 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
177 pcc->l1_dcache_size)));
178 } else {
179 warn_report("Unknown L1 dcache size for cpu");
180 }
181 if (pcc->l1_icache_size) {
182 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
183 pcc->l1_icache_size)));
184 } else {
185 warn_report("Unknown L1 icache size for cpu");
186 }
187
188 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
189 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
190 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size",
191 cpu->hash64_opts->slb_size)));
192 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
193 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
194
195 if (env->spr_cb[SPR_PURR].oea_read) {
196 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
197 }
198
199 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) {
200 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
201 segs, sizeof(segs))));
202 }
203
204 /*
205 * Advertise VMX/VSX (vector extensions) if available
206 * 0 / no property == no vector extensions
207 * 1 == VMX / Altivec available
208 * 2 == VSX available
209 */
210 if (env->insns_flags & PPC_ALTIVEC) {
211 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
212
213 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
214 }
215
216 /*
217 * Advertise DFP (Decimal Floating Point) if available
218 * 0 / no property == no DFP
219 * 1 == DFP available
220 */
221 if (env->insns_flags2 & PPC2_DFP) {
222 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
223 }
224
225 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop,
226 sizeof(page_sizes_prop));
227 if (page_sizes_prop_size) {
228 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
229 page_sizes_prop, page_sizes_prop_size)));
230 }
231
232 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
233 pa_features, sizeof(pa_features))));
234
235 /* Build interrupt servers properties */
236 for (i = 0; i < smt_threads; i++) {
237 servers_prop[i] = cpu_to_be32(pc->pir + i);
238 }
239 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
240 servers_prop, sizeof(servers_prop))));
241 }
242
243 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir,
244 uint32_t nr_threads)
245 {
246 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12);
247 char *name;
248 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp";
249 uint32_t irange[2], i, rsize;
250 uint64_t *reg;
251 int offset;
252
253 irange[0] = cpu_to_be32(pir);
254 irange[1] = cpu_to_be32(nr_threads);
255
256 rsize = sizeof(uint64_t) * 2 * nr_threads;
257 reg = g_malloc(rsize);
258 for (i = 0; i < nr_threads; i++) {
259 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000));
260 reg[i * 2 + 1] = cpu_to_be64(0x1000);
261 }
262
263 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr);
264 offset = fdt_add_subnode(fdt, 0, name);
265 _FDT(offset);
266 g_free(name);
267
268 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat))));
269 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize)));
270 _FDT((fdt_setprop_string(fdt, offset, "device_type",
271 "PowerPC-External-Interrupt-Presentation")));
272 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0)));
273 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges",
274 irange, sizeof(irange))));
275 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1)));
276 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0)));
277 g_free(reg);
278 }
279
280 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt)
281 {
282 const char *typename = pnv_chip_core_typename(chip);
283 size_t typesize = object_type_get_instance_size(typename);
284 int i;
285
286 pnv_dt_xscom(chip, fdt, 0);
287
288 for (i = 0; i < chip->nr_cores; i++) {
289 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize);
290
291 pnv_dt_core(chip, pnv_core, fdt);
292
293 /* Interrupt Control Presenters (ICP). One per core. */
294 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads);
295 }
296
297 if (chip->ram_size) {
298 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
299 }
300 }
301
302 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
303 {
304 const char *typename = pnv_chip_core_typename(chip);
305 size_t typesize = object_type_get_instance_size(typename);
306 int i;
307
308 pnv_dt_xscom(chip, fdt, 0);
309
310 for (i = 0; i < chip->nr_cores; i++) {
311 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize);
312
313 pnv_dt_core(chip, pnv_core, fdt);
314 }
315
316 if (chip->ram_size) {
317 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
318 }
319
320 pnv_dt_lpc(chip, fdt, 0);
321 }
322
323 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off)
324 {
325 uint32_t io_base = d->ioport_id;
326 uint32_t io_regs[] = {
327 cpu_to_be32(1),
328 cpu_to_be32(io_base),
329 cpu_to_be32(2)
330 };
331 char *name;
332 int node;
333
334 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
335 node = fdt_add_subnode(fdt, lpc_off, name);
336 _FDT(node);
337 g_free(name);
338
339 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
340 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00")));
341 }
342
343 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off)
344 {
345 const char compatible[] = "ns16550\0pnpPNP,501";
346 uint32_t io_base = d->ioport_id;
347 uint32_t io_regs[] = {
348 cpu_to_be32(1),
349 cpu_to_be32(io_base),
350 cpu_to_be32(8)
351 };
352 char *name;
353 int node;
354
355 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
356 node = fdt_add_subnode(fdt, lpc_off, name);
357 _FDT(node);
358 g_free(name);
359
360 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
361 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
362 sizeof(compatible))));
363
364 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200)));
365 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200)));
366 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0])));
367 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
368 fdt_get_phandle(fdt, lpc_off))));
369
370 /* This is needed by Linux */
371 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial")));
372 }
373
374 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off)
375 {
376 const char compatible[] = "bt\0ipmi-bt";
377 uint32_t io_base;
378 uint32_t io_regs[] = {
379 cpu_to_be32(1),
380 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */
381 cpu_to_be32(3)
382 };
383 uint32_t irq;
384 char *name;
385 int node;
386
387 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal);
388 io_regs[1] = cpu_to_be32(io_base);
389
390 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal);
391
392 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
393 node = fdt_add_subnode(fdt, lpc_off, name);
394 _FDT(node);
395 g_free(name);
396
397 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
398 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
399 sizeof(compatible))));
400
401 /* Mark it as reserved to avoid Linux trying to claim it */
402 _FDT((fdt_setprop_string(fdt, node, "status", "reserved")));
403 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq)));
404 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
405 fdt_get_phandle(fdt, lpc_off))));
406 }
407
408 typedef struct ForeachPopulateArgs {
409 void *fdt;
410 int offset;
411 } ForeachPopulateArgs;
412
413 static int pnv_dt_isa_device(DeviceState *dev, void *opaque)
414 {
415 ForeachPopulateArgs *args = opaque;
416 ISADevice *d = ISA_DEVICE(dev);
417
418 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) {
419 pnv_dt_rtc(d, args->fdt, args->offset);
420 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) {
421 pnv_dt_serial(d, args->fdt, args->offset);
422 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) {
423 pnv_dt_ipmi_bt(d, args->fdt, args->offset);
424 } else {
425 error_report("unknown isa device %s@i%x", qdev_fw_name(dev),
426 d->ioport_id);
427 }
428
429 return 0;
430 }
431
432 /*
433 * The default LPC bus of a multichip system is on chip 0. It's
434 * recognized by the firmware (skiboot) using a "primary" property.
435 */
436 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt)
437 {
438 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename);
439 ForeachPopulateArgs args = {
440 .fdt = fdt,
441 .offset = isa_offset,
442 };
443 uint32_t phandle;
444
445 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0)));
446
447 phandle = qemu_fdt_alloc_phandle(fdt);
448 assert(phandle > 0);
449 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle)));
450
451 /*
452 * ISA devices are not necessarily parented to the ISA bus so we
453 * can not use object_child_foreach()
454 */
455 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL,
456 &args);
457 }
458
459 static void pnv_dt_power_mgt(void *fdt)
460 {
461 int off;
462
463 off = fdt_add_subnode(fdt, 0, "ibm,opal");
464 off = fdt_add_subnode(fdt, off, "power-mgt");
465
466 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000));
467 }
468
469 static void *pnv_dt_create(MachineState *machine)
470 {
471 const char plat_compat8[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv";
472 const char plat_compat9[] = "qemu,powernv9\0ibm,powernv";
473 PnvMachineState *pnv = PNV_MACHINE(machine);
474 void *fdt;
475 char *buf;
476 int off;
477 int i;
478
479 fdt = g_malloc0(FDT_MAX_SIZE);
480 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
481
482 /* Root node */
483 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2)));
484 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2)));
485 _FDT((fdt_setprop_string(fdt, 0, "model",
486 "IBM PowerNV (emulated by qemu)")));
487 if (pnv_is_power9(pnv)) {
488 _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat9,
489 sizeof(plat_compat9))));
490 } else {
491 _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat8,
492 sizeof(plat_compat8))));
493 }
494
495
496 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
497 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf)));
498 if (qemu_uuid_set) {
499 _FDT((fdt_property_string(fdt, "system-id", buf)));
500 }
501 g_free(buf);
502
503 off = fdt_add_subnode(fdt, 0, "chosen");
504 if (machine->kernel_cmdline) {
505 _FDT((fdt_setprop_string(fdt, off, "bootargs",
506 machine->kernel_cmdline)));
507 }
508
509 if (pnv->initrd_size) {
510 uint32_t start_prop = cpu_to_be32(pnv->initrd_base);
511 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size);
512
513 _FDT((fdt_setprop(fdt, off, "linux,initrd-start",
514 &start_prop, sizeof(start_prop))));
515 _FDT((fdt_setprop(fdt, off, "linux,initrd-end",
516 &end_prop, sizeof(end_prop))));
517 }
518
519 /* Populate device tree for each chip */
520 for (i = 0; i < pnv->num_chips; i++) {
521 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt);
522 }
523
524 /* Populate ISA devices on chip 0 */
525 pnv_dt_isa(pnv, fdt);
526
527 if (pnv->bmc) {
528 pnv_dt_bmc_sensors(pnv->bmc, fdt);
529 }
530
531 /* Create an extra node for power management on Power9 */
532 if (pnv_is_power9(pnv)) {
533 pnv_dt_power_mgt(fdt);
534 }
535
536 return fdt;
537 }
538
539 static void pnv_powerdown_notify(Notifier *n, void *opaque)
540 {
541 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
542
543 if (pnv->bmc) {
544 pnv_bmc_powerdown(pnv->bmc);
545 }
546 }
547
548 static void pnv_reset(MachineState *machine)
549 {
550 PnvMachineState *pnv = PNV_MACHINE(machine);
551 void *fdt;
552 Object *obj;
553
554 qemu_devices_reset();
555
556 /*
557 * OpenPOWER systems have a BMC, which can be defined on the
558 * command line with:
559 *
560 * -device ipmi-bmc-sim,id=bmc0
561 *
562 * This is the internal simulator but it could also be an external
563 * BMC.
564 */
565 obj = object_resolve_path_type("", "ipmi-bmc-sim", NULL);
566 if (obj) {
567 pnv->bmc = IPMI_BMC(obj);
568 }
569
570 fdt = pnv_dt_create(machine);
571
572 /* Pack resulting tree */
573 _FDT((fdt_pack(fdt)));
574
575 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
576 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt));
577 }
578
579 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp)
580 {
581 Pnv8Chip *chip8 = PNV8_CHIP(chip);
582 return pnv_lpc_isa_create(&chip8->lpc, true, errp);
583 }
584
585 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp)
586 {
587 Pnv8Chip *chip8 = PNV8_CHIP(chip);
588 return pnv_lpc_isa_create(&chip8->lpc, false, errp);
589 }
590
591 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp)
592 {
593 Pnv9Chip *chip9 = PNV9_CHIP(chip);
594 return pnv_lpc_isa_create(&chip9->lpc, false, errp);
595 }
596
597 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp)
598 {
599 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp);
600 }
601
602 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon)
603 {
604 Pnv8Chip *chip8 = PNV8_CHIP(chip);
605
606 ics_pic_print_info(&chip8->psi.ics, mon);
607 }
608
609 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon)
610 {
611 Pnv9Chip *chip9 = PNV9_CHIP(chip);
612
613 pnv_xive_pic_print_info(&chip9->xive, mon);
614 pnv_psi_pic_print_info(&chip9->psi, mon);
615 }
616
617 static bool pnv_match_cpu(const char *default_type, const char *cpu_type)
618 {
619 PowerPCCPUClass *ppc_default =
620 POWERPC_CPU_CLASS(object_class_by_name(default_type));
621 PowerPCCPUClass *ppc =
622 POWERPC_CPU_CLASS(object_class_by_name(cpu_type));
623
624 return ppc_default->pvr_match(ppc_default, ppc->pvr);
625 }
626
627 static void pnv_init(MachineState *machine)
628 {
629 PnvMachineState *pnv = PNV_MACHINE(machine);
630 MachineClass *mc = MACHINE_GET_CLASS(machine);
631 MemoryRegion *ram;
632 char *fw_filename;
633 long fw_size;
634 int i;
635 char *chip_typename;
636
637 /* allocate RAM */
638 if (machine->ram_size < (1 * GiB)) {
639 warn_report("skiboot may not work with < 1GB of RAM");
640 }
641
642 ram = g_new(MemoryRegion, 1);
643 memory_region_allocate_system_memory(ram, NULL, "pnv.ram",
644 machine->ram_size);
645 memory_region_add_subregion(get_system_memory(), 0, ram);
646
647 /* load skiboot firmware */
648 if (bios_name == NULL) {
649 bios_name = FW_FILE_NAME;
650 }
651
652 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
653 if (!fw_filename) {
654 error_report("Could not find OPAL firmware '%s'", bios_name);
655 exit(1);
656 }
657
658 fw_size = load_image_targphys(fw_filename, FW_LOAD_ADDR, FW_MAX_SIZE);
659 if (fw_size < 0) {
660 error_report("Could not load OPAL firmware '%s'", fw_filename);
661 exit(1);
662 }
663 g_free(fw_filename);
664
665 /* load kernel */
666 if (machine->kernel_filename) {
667 long kernel_size;
668
669 kernel_size = load_image_targphys(machine->kernel_filename,
670 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE);
671 if (kernel_size < 0) {
672 error_report("Could not load kernel '%s'",
673 machine->kernel_filename);
674 exit(1);
675 }
676 }
677
678 /* load initrd */
679 if (machine->initrd_filename) {
680 pnv->initrd_base = INITRD_LOAD_ADDR;
681 pnv->initrd_size = load_image_targphys(machine->initrd_filename,
682 pnv->initrd_base, INITRD_MAX_SIZE);
683 if (pnv->initrd_size < 0) {
684 error_report("Could not load initial ram disk '%s'",
685 machine->initrd_filename);
686 exit(1);
687 }
688 }
689
690 /*
691 * Check compatibility of the specified CPU with the machine
692 * default.
693 */
694 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) {
695 error_report("invalid CPU model '%s' for %s machine",
696 machine->cpu_type, mc->name);
697 exit(1);
698 }
699
700 /* Create the processor chips */
701 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX);
702 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"),
703 i, machine->cpu_type);
704 if (!object_class_by_name(chip_typename)) {
705 error_report("invalid chip model '%.*s' for %s machine",
706 i, machine->cpu_type, mc->name);
707 exit(1);
708 }
709
710 pnv->chips = g_new0(PnvChip *, pnv->num_chips);
711 for (i = 0; i < pnv->num_chips; i++) {
712 char chip_name[32];
713 Object *chip = object_new(chip_typename);
714
715 pnv->chips[i] = PNV_CHIP(chip);
716
717 /*
718 * TODO: put all the memory in one node on chip 0 until we find a
719 * way to specify different ranges for each chip
720 */
721 if (i == 0) {
722 object_property_set_int(chip, machine->ram_size, "ram-size",
723 &error_fatal);
724 }
725
726 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i));
727 object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal);
728 object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id",
729 &error_fatal);
730 object_property_set_int(chip, machine->smp.cores,
731 "nr-cores", &error_fatal);
732 object_property_set_bool(chip, true, "realized", &error_fatal);
733 }
734 g_free(chip_typename);
735
736 /* Instantiate ISA bus on chip 0 */
737 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal);
738
739 /* Create serial port */
740 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS);
741
742 /* Create an RTC ISA device too */
743 mc146818_rtc_init(pnv->isa_bus, 2000, NULL);
744
745 /*
746 * OpenPOWER systems use a IPMI SEL Event message to notify the
747 * host to powerdown
748 */
749 pnv->powerdown_notifier.notify = pnv_powerdown_notify;
750 qemu_register_powerdown_notifier(&pnv->powerdown_notifier);
751 }
752
753 /*
754 * 0:21 Reserved - Read as zeros
755 * 22:24 Chip ID
756 * 25:28 Core number
757 * 29:31 Thread ID
758 */
759 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id)
760 {
761 return (chip->chip_id << 7) | (core_id << 3);
762 }
763
764 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu,
765 Error **errp)
766 {
767 Error *local_err = NULL;
768 Object *obj;
769 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
770
771 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, XICS_FABRIC(qdev_get_machine()),
772 &local_err);
773 if (local_err) {
774 error_propagate(errp, local_err);
775 return;
776 }
777
778 pnv_cpu->intc = obj;
779 }
780
781
782 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
783 {
784 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
785
786 icp_reset(ICP(pnv_cpu->intc));
787 }
788
789 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
790 {
791 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
792
793 icp_destroy(ICP(pnv_cpu->intc));
794 pnv_cpu->intc = NULL;
795 }
796
797 /*
798 * 0:48 Reserved - Read as zeroes
799 * 49:52 Node ID
800 * 53:55 Chip ID
801 * 56 Reserved - Read as zero
802 * 57:61 Core number
803 * 62:63 Thread ID
804 *
805 * We only care about the lower bits. uint32_t is fine for the moment.
806 */
807 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id)
808 {
809 return (chip->chip_id << 8) | (core_id << 2);
810 }
811
812 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu,
813 Error **errp)
814 {
815 Pnv9Chip *chip9 = PNV9_CHIP(chip);
816 Error *local_err = NULL;
817 Object *obj;
818 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
819
820 /*
821 * The core creates its interrupt presenter but the XIVE interrupt
822 * controller object is initialized afterwards. Hopefully, it's
823 * only used at runtime.
824 */
825 obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(&chip9->xive), &local_err);
826 if (local_err) {
827 error_propagate(errp, local_err);
828 return;
829 }
830
831 pnv_cpu->intc = obj;
832 }
833
834 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
835 {
836 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
837
838 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc));
839 }
840
841 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
842 {
843 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
844
845 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc));
846 pnv_cpu->intc = NULL;
847 }
848
849 /*
850 * Allowed core identifiers on a POWER8 Processor Chip :
851 *
852 * <EX0 reserved>
853 * EX1 - Venice only
854 * EX2 - Venice only
855 * EX3 - Venice only
856 * EX4
857 * EX5
858 * EX6
859 * <EX7,8 reserved> <reserved>
860 * EX9 - Venice only
861 * EX10 - Venice only
862 * EX11 - Venice only
863 * EX12
864 * EX13
865 * EX14
866 * <EX15 reserved>
867 */
868 #define POWER8E_CORE_MASK (0x7070ull)
869 #define POWER8_CORE_MASK (0x7e7eull)
870
871 /*
872 * POWER9 has 24 cores, ids starting at 0x0
873 */
874 #define POWER9_CORE_MASK (0xffffffffffffffull)
875
876 static void pnv_chip_power8_instance_init(Object *obj)
877 {
878 Pnv8Chip *chip8 = PNV8_CHIP(obj);
879
880 object_initialize_child(obj, "psi", &chip8->psi, sizeof(chip8->psi),
881 TYPE_PNV8_PSI, &error_abort, NULL);
882 object_property_add_const_link(OBJECT(&chip8->psi), "xics",
883 OBJECT(qdev_get_machine()), &error_abort);
884
885 object_initialize_child(obj, "lpc", &chip8->lpc, sizeof(chip8->lpc),
886 TYPE_PNV8_LPC, &error_abort, NULL);
887 object_property_add_const_link(OBJECT(&chip8->lpc), "psi",
888 OBJECT(&chip8->psi), &error_abort);
889
890 object_initialize_child(obj, "occ", &chip8->occ, sizeof(chip8->occ),
891 TYPE_PNV8_OCC, &error_abort, NULL);
892 object_property_add_const_link(OBJECT(&chip8->occ), "psi",
893 OBJECT(&chip8->psi), &error_abort);
894
895 object_initialize_child(obj, "homer", &chip8->homer, sizeof(chip8->homer),
896 TYPE_PNV8_HOMER, &error_abort, NULL);
897 object_property_add_const_link(OBJECT(&chip8->homer), "chip", obj,
898 &error_abort);
899 }
900
901 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
902 {
903 PnvChip *chip = PNV_CHIP(chip8);
904 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
905 const char *typename = pnv_chip_core_typename(chip);
906 size_t typesize = object_type_get_instance_size(typename);
907 int i, j;
908 char *name;
909 XICSFabric *xi = XICS_FABRIC(qdev_get_machine());
910
911 name = g_strdup_printf("icp-%x", chip->chip_id);
912 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE);
913 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio);
914 g_free(name);
915
916 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip));
917
918 /* Map the ICP registers for each thread */
919 for (i = 0; i < chip->nr_cores; i++) {
920 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize);
921 int core_hwid = CPU_CORE(pnv_core)->core_id;
922
923 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) {
924 uint32_t pir = pcc->core_pir(chip, core_hwid) + j;
925 PnvICPState *icp = PNV_ICP(xics_icp_get(xi, pir));
926
927 memory_region_add_subregion(&chip8->icp_mmio, pir << 12,
928 &icp->mmio);
929 }
930 }
931 }
932
933 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
934 {
935 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
936 PnvChip *chip = PNV_CHIP(dev);
937 Pnv8Chip *chip8 = PNV8_CHIP(dev);
938 Pnv8Psi *psi8 = &chip8->psi;
939 Error *local_err = NULL;
940
941 /* XSCOM bridge is first */
942 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err);
943 if (local_err) {
944 error_propagate(errp, local_err);
945 return;
946 }
947 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip));
948
949 pcc->parent_realize(dev, &local_err);
950 if (local_err) {
951 error_propagate(errp, local_err);
952 return;
953 }
954
955 /* Processor Service Interface (PSI) Host Bridge */
956 object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip),
957 "bar", &error_fatal);
958 object_property_set_bool(OBJECT(&chip8->psi), true, "realized", &local_err);
959 if (local_err) {
960 error_propagate(errp, local_err);
961 return;
962 }
963 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE,
964 &PNV_PSI(psi8)->xscom_regs);
965
966 /* Create LPC controller */
967 object_property_set_bool(OBJECT(&chip8->lpc), true, "realized",
968 &error_fatal);
969 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs);
970
971 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x",
972 (uint64_t) PNV_XSCOM_BASE(chip),
973 PNV_XSCOM_LPC_BASE);
974
975 /*
976 * Interrupt Management Area. This is the memory region holding
977 * all the Interrupt Control Presenter (ICP) registers
978 */
979 pnv_chip_icp_realize(chip8, &local_err);
980 if (local_err) {
981 error_propagate(errp, local_err);
982 return;
983 }
984
985 /* Create the simplified OCC model */
986 object_property_set_bool(OBJECT(&chip8->occ), true, "realized", &local_err);
987 if (local_err) {
988 error_propagate(errp, local_err);
989 return;
990 }
991 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs);
992
993 /* OCC SRAM model */
994 memory_region_add_subregion(get_system_memory(), PNV_OCC_COMMON_AREA(chip),
995 &chip8->occ.sram_regs);
996
997 /* HOMER */
998 object_property_set_bool(OBJECT(&chip8->homer), true, "realized",
999 &local_err);
1000 if (local_err) {
1001 error_propagate(errp, local_err);
1002 return;
1003 }
1004 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip),
1005 &chip8->homer.regs);
1006 }
1007
1008 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
1009 {
1010 DeviceClass *dc = DEVICE_CLASS(klass);
1011 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1012
1013 k->chip_type = PNV_CHIP_POWER8E;
1014 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */
1015 k->cores_mask = POWER8E_CORE_MASK;
1016 k->core_pir = pnv_chip_core_pir_p8;
1017 k->intc_create = pnv_chip_power8_intc_create;
1018 k->intc_reset = pnv_chip_power8_intc_reset;
1019 k->intc_destroy = pnv_chip_power8_intc_destroy;
1020 k->isa_create = pnv_chip_power8_isa_create;
1021 k->dt_populate = pnv_chip_power8_dt_populate;
1022 k->pic_print_info = pnv_chip_power8_pic_print_info;
1023 dc->desc = "PowerNV Chip POWER8E";
1024
1025 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1026 &k->parent_realize);
1027 }
1028
1029 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
1030 {
1031 DeviceClass *dc = DEVICE_CLASS(klass);
1032 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1033
1034 k->chip_type = PNV_CHIP_POWER8;
1035 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */
1036 k->cores_mask = POWER8_CORE_MASK;
1037 k->core_pir = pnv_chip_core_pir_p8;
1038 k->intc_create = pnv_chip_power8_intc_create;
1039 k->intc_reset = pnv_chip_power8_intc_reset;
1040 k->intc_destroy = pnv_chip_power8_intc_destroy;
1041 k->isa_create = pnv_chip_power8_isa_create;
1042 k->dt_populate = pnv_chip_power8_dt_populate;
1043 k->pic_print_info = pnv_chip_power8_pic_print_info;
1044 dc->desc = "PowerNV Chip POWER8";
1045
1046 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1047 &k->parent_realize);
1048 }
1049
1050 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
1051 {
1052 DeviceClass *dc = DEVICE_CLASS(klass);
1053 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1054
1055 k->chip_type = PNV_CHIP_POWER8NVL;
1056 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */
1057 k->cores_mask = POWER8_CORE_MASK;
1058 k->core_pir = pnv_chip_core_pir_p8;
1059 k->intc_create = pnv_chip_power8_intc_create;
1060 k->intc_reset = pnv_chip_power8_intc_reset;
1061 k->intc_destroy = pnv_chip_power8_intc_destroy;
1062 k->isa_create = pnv_chip_power8nvl_isa_create;
1063 k->dt_populate = pnv_chip_power8_dt_populate;
1064 k->pic_print_info = pnv_chip_power8_pic_print_info;
1065 dc->desc = "PowerNV Chip POWER8NVL";
1066
1067 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1068 &k->parent_realize);
1069 }
1070
1071 static void pnv_chip_power9_instance_init(Object *obj)
1072 {
1073 Pnv9Chip *chip9 = PNV9_CHIP(obj);
1074
1075 object_initialize_child(obj, "xive", &chip9->xive, sizeof(chip9->xive),
1076 TYPE_PNV_XIVE, &error_abort, NULL);
1077 object_property_add_const_link(OBJECT(&chip9->xive), "chip", obj,
1078 &error_abort);
1079
1080 object_initialize_child(obj, "psi", &chip9->psi, sizeof(chip9->psi),
1081 TYPE_PNV9_PSI, &error_abort, NULL);
1082 object_property_add_const_link(OBJECT(&chip9->psi), "chip", obj,
1083 &error_abort);
1084
1085 object_initialize_child(obj, "lpc", &chip9->lpc, sizeof(chip9->lpc),
1086 TYPE_PNV9_LPC, &error_abort, NULL);
1087 object_property_add_const_link(OBJECT(&chip9->lpc), "psi",
1088 OBJECT(&chip9->psi), &error_abort);
1089
1090 object_initialize_child(obj, "occ", &chip9->occ, sizeof(chip9->occ),
1091 TYPE_PNV9_OCC, &error_abort, NULL);
1092 object_property_add_const_link(OBJECT(&chip9->occ), "psi",
1093 OBJECT(&chip9->psi), &error_abort);
1094
1095 object_initialize_child(obj, "homer", &chip9->homer, sizeof(chip9->homer),
1096 TYPE_PNV9_HOMER, &error_abort, NULL);
1097 object_property_add_const_link(OBJECT(&chip9->homer), "chip", obj,
1098 &error_abort);
1099 }
1100
1101 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp)
1102 {
1103 PnvChip *chip = PNV_CHIP(chip9);
1104 const char *typename = pnv_chip_core_typename(chip);
1105 size_t typesize = object_type_get_instance_size(typename);
1106 int i;
1107
1108 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4);
1109 chip9->quads = g_new0(PnvQuad, chip9->nr_quads);
1110
1111 for (i = 0; i < chip9->nr_quads; i++) {
1112 char eq_name[32];
1113 PnvQuad *eq = &chip9->quads[i];
1114 PnvCore *pnv_core = PNV_CORE(chip->cores + (i * 4) * typesize);
1115 int core_id = CPU_CORE(pnv_core)->core_id;
1116
1117 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id);
1118 object_initialize_child(OBJECT(chip), eq_name, eq, sizeof(*eq),
1119 TYPE_PNV_QUAD, &error_fatal, NULL);
1120
1121 object_property_set_int(OBJECT(eq), core_id, "id", &error_fatal);
1122 object_property_set_bool(OBJECT(eq), true, "realized", &error_fatal);
1123
1124 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->id),
1125 &eq->xscom_regs);
1126 }
1127 }
1128
1129 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
1130 {
1131 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1132 Pnv9Chip *chip9 = PNV9_CHIP(dev);
1133 PnvChip *chip = PNV_CHIP(dev);
1134 Pnv9Psi *psi9 = &chip9->psi;
1135 Error *local_err = NULL;
1136
1137 /* XSCOM bridge is first */
1138 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err);
1139 if (local_err) {
1140 error_propagate(errp, local_err);
1141 return;
1142 }
1143 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip));
1144
1145 pcc->parent_realize(dev, &local_err);
1146 if (local_err) {
1147 error_propagate(errp, local_err);
1148 return;
1149 }
1150
1151 pnv_chip_quad_realize(chip9, &local_err);
1152 if (local_err) {
1153 error_propagate(errp, local_err);
1154 return;
1155 }
1156
1157 /* XIVE interrupt controller (POWER9) */
1158 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_IC_BASE(chip),
1159 "ic-bar", &error_fatal);
1160 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_VC_BASE(chip),
1161 "vc-bar", &error_fatal);
1162 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_PC_BASE(chip),
1163 "pc-bar", &error_fatal);
1164 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_TM_BASE(chip),
1165 "tm-bar", &error_fatal);
1166 object_property_set_bool(OBJECT(&chip9->xive), true, "realized",
1167 &local_err);
1168 if (local_err) {
1169 error_propagate(errp, local_err);
1170 return;
1171 }
1172 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE,
1173 &chip9->xive.xscom_regs);
1174
1175 /* Processor Service Interface (PSI) Host Bridge */
1176 object_property_set_int(OBJECT(&chip9->psi), PNV9_PSIHB_BASE(chip),
1177 "bar", &error_fatal);
1178 object_property_set_bool(OBJECT(&chip9->psi), true, "realized", &local_err);
1179 if (local_err) {
1180 error_propagate(errp, local_err);
1181 return;
1182 }
1183 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE,
1184 &PNV_PSI(psi9)->xscom_regs);
1185
1186 /* LPC */
1187 object_property_set_bool(OBJECT(&chip9->lpc), true, "realized", &local_err);
1188 if (local_err) {
1189 error_propagate(errp, local_err);
1190 return;
1191 }
1192 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip),
1193 &chip9->lpc.xscom_regs);
1194
1195 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
1196 (uint64_t) PNV9_LPCM_BASE(chip));
1197
1198 /* Create the simplified OCC model */
1199 object_property_set_bool(OBJECT(&chip9->occ), true, "realized", &local_err);
1200 if (local_err) {
1201 error_propagate(errp, local_err);
1202 return;
1203 }
1204 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs);
1205
1206 /* OCC SRAM model */
1207 memory_region_add_subregion(get_system_memory(), PNV9_OCC_COMMON_AREA(chip),
1208 &chip9->occ.sram_regs);
1209
1210 /* HOMER */
1211 object_property_set_bool(OBJECT(&chip9->homer), true, "realized",
1212 &local_err);
1213 if (local_err) {
1214 error_propagate(errp, local_err);
1215 return;
1216 }
1217 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip),
1218 &chip9->homer.regs);
1219 }
1220
1221 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
1222 {
1223 DeviceClass *dc = DEVICE_CLASS(klass);
1224 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1225
1226 k->chip_type = PNV_CHIP_POWER9;
1227 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */
1228 k->cores_mask = POWER9_CORE_MASK;
1229 k->core_pir = pnv_chip_core_pir_p9;
1230 k->intc_create = pnv_chip_power9_intc_create;
1231 k->intc_reset = pnv_chip_power9_intc_reset;
1232 k->intc_destroy = pnv_chip_power9_intc_destroy;
1233 k->isa_create = pnv_chip_power9_isa_create;
1234 k->dt_populate = pnv_chip_power9_dt_populate;
1235 k->pic_print_info = pnv_chip_power9_pic_print_info;
1236 dc->desc = "PowerNV Chip POWER9";
1237
1238 device_class_set_parent_realize(dc, pnv_chip_power9_realize,
1239 &k->parent_realize);
1240 }
1241
1242 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp)
1243 {
1244 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1245 int cores_max;
1246
1247 /*
1248 * No custom mask for this chip, let's use the default one from *
1249 * the chip class
1250 */
1251 if (!chip->cores_mask) {
1252 chip->cores_mask = pcc->cores_mask;
1253 }
1254
1255 /* filter alien core ids ! some are reserved */
1256 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) {
1257 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !",
1258 chip->cores_mask);
1259 return;
1260 }
1261 chip->cores_mask &= pcc->cores_mask;
1262
1263 /* now that we have a sane layout, let check the number of cores */
1264 cores_max = ctpop64(chip->cores_mask);
1265 if (chip->nr_cores > cores_max) {
1266 error_setg(errp, "warning: too many cores for chip ! Limit is %d",
1267 cores_max);
1268 return;
1269 }
1270 }
1271
1272 static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
1273 {
1274 MachineState *ms = MACHINE(qdev_get_machine());
1275 Error *error = NULL;
1276 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1277 const char *typename = pnv_chip_core_typename(chip);
1278 size_t typesize = object_type_get_instance_size(typename);
1279 int i, core_hwid;
1280
1281 if (!object_class_by_name(typename)) {
1282 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename);
1283 return;
1284 }
1285
1286 /* Cores */
1287 pnv_chip_core_sanitize(chip, &error);
1288 if (error) {
1289 error_propagate(errp, error);
1290 return;
1291 }
1292
1293 chip->cores = g_malloc0(typesize * chip->nr_cores);
1294
1295 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8)
1296 && (i < chip->nr_cores); core_hwid++) {
1297 char core_name[32];
1298 void *pnv_core = chip->cores + i * typesize;
1299 uint64_t xscom_core_base;
1300
1301 if (!(chip->cores_mask & (1ull << core_hwid))) {
1302 continue;
1303 }
1304
1305 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid);
1306 object_initialize_child(OBJECT(chip), core_name, pnv_core, typesize,
1307 typename, &error_fatal, NULL);
1308 object_property_set_int(OBJECT(pnv_core), ms->smp.threads, "nr-threads",
1309 &error_fatal);
1310 object_property_set_int(OBJECT(pnv_core), core_hwid,
1311 CPU_CORE_PROP_CORE_ID, &error_fatal);
1312 object_property_set_int(OBJECT(pnv_core),
1313 pcc->core_pir(chip, core_hwid),
1314 "pir", &error_fatal);
1315 object_property_add_const_link(OBJECT(pnv_core), "chip",
1316 OBJECT(chip), &error_fatal);
1317 object_property_set_bool(OBJECT(pnv_core), true, "realized",
1318 &error_fatal);
1319
1320 /* Each core has an XSCOM MMIO region */
1321 if (!pnv_chip_is_power9(chip)) {
1322 xscom_core_base = PNV_XSCOM_EX_BASE(core_hwid);
1323 } else {
1324 xscom_core_base = PNV9_XSCOM_EC_BASE(core_hwid);
1325 }
1326
1327 pnv_xscom_add_subregion(chip, xscom_core_base,
1328 &PNV_CORE(pnv_core)->xscom_regs);
1329 i++;
1330 }
1331 }
1332
1333 static void pnv_chip_realize(DeviceState *dev, Error **errp)
1334 {
1335 PnvChip *chip = PNV_CHIP(dev);
1336 Error *error = NULL;
1337
1338 /* Cores */
1339 pnv_chip_core_realize(chip, &error);
1340 if (error) {
1341 error_propagate(errp, error);
1342 return;
1343 }
1344 }
1345
1346 static Property pnv_chip_properties[] = {
1347 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0),
1348 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0),
1349 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0),
1350 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1),
1351 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0),
1352 DEFINE_PROP_END_OF_LIST(),
1353 };
1354
1355 static void pnv_chip_class_init(ObjectClass *klass, void *data)
1356 {
1357 DeviceClass *dc = DEVICE_CLASS(klass);
1358
1359 set_bit(DEVICE_CATEGORY_CPU, dc->categories);
1360 dc->realize = pnv_chip_realize;
1361 dc->props = pnv_chip_properties;
1362 dc->desc = "PowerNV Chip";
1363 }
1364
1365 static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
1366 {
1367 PnvMachineState *pnv = PNV_MACHINE(xi);
1368 int i;
1369
1370 for (i = 0; i < pnv->num_chips; i++) {
1371 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
1372
1373 if (ics_valid_irq(&chip8->psi.ics, irq)) {
1374 return &chip8->psi.ics;
1375 }
1376 }
1377 return NULL;
1378 }
1379
1380 static void pnv_ics_resend(XICSFabric *xi)
1381 {
1382 PnvMachineState *pnv = PNV_MACHINE(xi);
1383 int i;
1384
1385 for (i = 0; i < pnv->num_chips; i++) {
1386 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
1387 ics_resend(&chip8->psi.ics);
1388 }
1389 }
1390
1391 static ICPState *pnv_icp_get(XICSFabric *xi, int pir)
1392 {
1393 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir);
1394
1395 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL;
1396 }
1397
1398 static void pnv_pic_print_info(InterruptStatsProvider *obj,
1399 Monitor *mon)
1400 {
1401 PnvMachineState *pnv = PNV_MACHINE(obj);
1402 int i;
1403 CPUState *cs;
1404
1405 CPU_FOREACH(cs) {
1406 PowerPCCPU *cpu = POWERPC_CPU(cs);
1407
1408 if (pnv_chip_is_power9(pnv->chips[0])) {
1409 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon);
1410 } else {
1411 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon);
1412 }
1413 }
1414
1415 for (i = 0; i < pnv->num_chips; i++) {
1416 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon);
1417 }
1418 }
1419
1420 static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name,
1421 void *opaque, Error **errp)
1422 {
1423 visit_type_uint32(v, name, &PNV_MACHINE(obj)->num_chips, errp);
1424 }
1425
1426 static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name,
1427 void *opaque, Error **errp)
1428 {
1429 PnvMachineState *pnv = PNV_MACHINE(obj);
1430 uint32_t num_chips;
1431 Error *local_err = NULL;
1432
1433 visit_type_uint32(v, name, &num_chips, &local_err);
1434 if (local_err) {
1435 error_propagate(errp, local_err);
1436 return;
1437 }
1438
1439 /*
1440 * TODO: should we decide on how many chips we can create based
1441 * on #cores and Venice vs. Murano vs. Naples chip type etc...,
1442 */
1443 if (!is_power_of_2(num_chips) || num_chips > 4) {
1444 error_setg(errp, "invalid number of chips: '%d'", num_chips);
1445 return;
1446 }
1447
1448 pnv->num_chips = num_chips;
1449 }
1450
1451 static void pnv_machine_instance_init(Object *obj)
1452 {
1453 PnvMachineState *pnv = PNV_MACHINE(obj);
1454 pnv->num_chips = 1;
1455 }
1456
1457 static void pnv_machine_class_props_init(ObjectClass *oc)
1458 {
1459 object_class_property_add(oc, "num-chips", "uint32",
1460 pnv_get_num_chips, pnv_set_num_chips,
1461 NULL, NULL, NULL);
1462 object_class_property_set_description(oc, "num-chips",
1463 "Specifies the number of processor chips",
1464 NULL);
1465 }
1466
1467 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data)
1468 {
1469 MachineClass *mc = MACHINE_CLASS(oc);
1470 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
1471
1472 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8";
1473 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
1474
1475 xic->icp_get = pnv_icp_get;
1476 xic->ics_get = pnv_ics_get;
1477 xic->ics_resend = pnv_ics_resend;
1478 }
1479
1480 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data)
1481 {
1482 MachineClass *mc = MACHINE_CLASS(oc);
1483
1484 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9";
1485 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0");
1486
1487 mc->alias = "powernv";
1488 }
1489
1490 static void pnv_machine_class_init(ObjectClass *oc, void *data)
1491 {
1492 MachineClass *mc = MACHINE_CLASS(oc);
1493 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
1494
1495 mc->desc = "IBM PowerNV (Non-Virtualized)";
1496 mc->init = pnv_init;
1497 mc->reset = pnv_reset;
1498 mc->max_cpus = MAX_CPUS;
1499 /* Pnv provides a AHCI device for storage */
1500 mc->block_default_type = IF_IDE;
1501 mc->no_parallel = 1;
1502 mc->default_boot_order = NULL;
1503 /*
1504 * RAM defaults to less than 2048 for 32-bit hosts, and large
1505 * enough to fit the maximum initrd size at it's load address
1506 */
1507 mc->default_ram_size = INITRD_LOAD_ADDR + INITRD_MAX_SIZE;
1508 ispc->print_info = pnv_pic_print_info;
1509
1510 pnv_machine_class_props_init(oc);
1511 }
1512
1513 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \
1514 { \
1515 .name = type, \
1516 .class_init = class_initfn, \
1517 .parent = TYPE_PNV8_CHIP, \
1518 }
1519
1520 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \
1521 { \
1522 .name = type, \
1523 .class_init = class_initfn, \
1524 .parent = TYPE_PNV9_CHIP, \
1525 }
1526
1527 static const TypeInfo types[] = {
1528 {
1529 .name = MACHINE_TYPE_NAME("powernv9"),
1530 .parent = TYPE_PNV_MACHINE,
1531 .class_init = pnv_machine_power9_class_init,
1532 },
1533 {
1534 .name = MACHINE_TYPE_NAME("powernv8"),
1535 .parent = TYPE_PNV_MACHINE,
1536 .class_init = pnv_machine_power8_class_init,
1537 .interfaces = (InterfaceInfo[]) {
1538 { TYPE_XICS_FABRIC },
1539 { },
1540 },
1541 },
1542 {
1543 .name = TYPE_PNV_MACHINE,
1544 .parent = TYPE_MACHINE,
1545 .abstract = true,
1546 .instance_size = sizeof(PnvMachineState),
1547 .instance_init = pnv_machine_instance_init,
1548 .class_init = pnv_machine_class_init,
1549 .interfaces = (InterfaceInfo[]) {
1550 { TYPE_INTERRUPT_STATS_PROVIDER },
1551 { },
1552 },
1553 },
1554 {
1555 .name = TYPE_PNV_CHIP,
1556 .parent = TYPE_SYS_BUS_DEVICE,
1557 .class_init = pnv_chip_class_init,
1558 .instance_size = sizeof(PnvChip),
1559 .class_size = sizeof(PnvChipClass),
1560 .abstract = true,
1561 },
1562
1563 /*
1564 * P9 chip and variants
1565 */
1566 {
1567 .name = TYPE_PNV9_CHIP,
1568 .parent = TYPE_PNV_CHIP,
1569 .instance_init = pnv_chip_power9_instance_init,
1570 .instance_size = sizeof(Pnv9Chip),
1571 },
1572 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init),
1573
1574 /*
1575 * P8 chip and variants
1576 */
1577 {
1578 .name = TYPE_PNV8_CHIP,
1579 .parent = TYPE_PNV_CHIP,
1580 .instance_init = pnv_chip_power8_instance_init,
1581 .instance_size = sizeof(Pnv8Chip),
1582 },
1583 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init),
1584 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init),
1585 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL,
1586 pnv_chip_power8nvl_class_init),
1587 };
1588
1589 DEFINE_TYPES(types)
AR7 emulation for QEMU