hw/arm/xlnx-zynqmp.c

   1 /*
   2  * Xilinx Zynq MPSoC emulation
   3  *
   4  * Copyright (C) 2015 Xilinx Inc
   5  * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  15  * for more details.
  16  */
  17
  18 #include "qemu/osdep.h"
  19 #include "qapi/error.h"
  20 #include "qemu-common.h"
  21 #include "cpu.h"
  22 #include "hw/arm/xlnx-zynqmp.h"
  23 #include "hw/intc/arm_gic_common.h"
  24 #include "exec/address-spaces.h"
  25 #include "sysemu/kvm.h"
  26 #include "kvm_arm.h"
  27
  28 #define GIC_NUM_SPI_INTR 160
  29
  30 #define ARM_PHYS_TIMER_PPI  30
  31 #define ARM_VIRT_TIMER_PPI  27
  32
  33 #define GIC_BASE_ADDR       0xf9000000
  34 #define GIC_DIST_ADDR       0xf9010000
  35 #define GIC_CPU_ADDR        0xf9020000
  36
  37 #define SATA_INTR           133
  38 #define SATA_ADDR           0xFD0C0000
  39 #define SATA_NUM_PORTS      2
  40
  41 #define DP_ADDR             0xfd4a0000
  42 #define DP_IRQ              113
  43
  44 #define DPDMA_ADDR          0xfd4c0000
  45 #define DPDMA_IRQ           116
  46
  47 static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
  48     0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
  49 };
  50
  51 static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = {
  52     57, 59, 61, 63,
  53 };
  54
  55 static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = {
  56     0xFF000000, 0xFF010000,
  57 };
  58
  59 static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
  60     21, 22,
  61 };
  62
  63 static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = {
  64     0xFF160000, 0xFF170000,
  65 };
  66
  67 static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = {
  68     48, 49,
  69 };
  70
  71 static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = {
  72     0xFF040000, 0xFF050000,
  73 };
  74
  75 static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = {
  76     19, 20,
  77 };
  78
  79 typedef struct XlnxZynqMPGICRegion {
  80     int region_index;
  81     uint32_t address;
  82 } XlnxZynqMPGICRegion;
  83
  84 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = {
  85     { .region_index = 0, .address = GIC_DIST_ADDR, },
  86     { .region_index = 1, .address = GIC_CPU_ADDR,  },
  87 };
  88
  89 static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
  90 {
  91     return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index;
  92 }
  93
  94 static void xlnx_zynqmp_create_rpu(XlnxZynqMPState *s, const char *boot_cpu,
  95                                    Error **errp)
  96 {
  97     Error *err = NULL;
  98     int i;
  99
 100     for (i = 0; i < XLNX_ZYNQMP_NUM_RPU_CPUS; i++) {
 101         char *name;
 102
 103         object_initialize(&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]),
 104                           "cortex-r5-" TYPE_ARM_CPU);
 105         object_property_add_child(OBJECT(s), "rpu-cpu[*]",
 106                                   OBJECT(&s->rpu_cpu[i]), &error_abort);
 107
 108         name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i]));
 109         if (strcmp(name, boot_cpu)) {
 110             /* Secondary CPUs start in PSCI powered-down state */
 111             object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true,
 112                                      "start-powered-off", &error_abort);
 113         } else {
 114             s->boot_cpu_ptr = &s->rpu_cpu[i];
 115         }
 116         g_free(name);
 117
 118         object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "reset-hivecs",
 119                                  &error_abort);
 120         object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "realized",
 121                                  &err);
 122         if (err) {
 123             error_propagate(errp, err);
 124             return;
 125         }
 126     }
 127 }
 128
 129 static void xlnx_zynqmp_init(Object *obj)
 130 {
 131     XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
 132     int i;
 133
 134     for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
 135         object_initialize(&s->apu_cpu[i], sizeof(s->apu_cpu[i]),
 136                           "cortex-a53-" TYPE_ARM_CPU);
 137         object_property_add_child(obj, "apu-cpu[*]", OBJECT(&s->apu_cpu[i]),
 138                                   &error_abort);
 139     }
 140
 141     object_property_add_link(obj, "ddr-ram", TYPE_MEMORY_REGION,
 142                              (Object **)&s->ddr_ram,
 143                              qdev_prop_allow_set_link_before_realize,
 144                              OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort);
 145
 146     object_initialize(&s->gic, sizeof(s->gic), gic_class_name());
 147     qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());
 148
 149     for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
 150         object_initialize(&s->gem[i], sizeof(s->gem[i]), TYPE_CADENCE_GEM);
 151         qdev_set_parent_bus(DEVICE(&s->gem[i]), sysbus_get_default());
 152     }
 153
 154     for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
 155         object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_CADENCE_UART);
 156         qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
 157     }
 158
 159     object_initialize(&s->sata, sizeof(s->sata), TYPE_SYSBUS_AHCI);
 160     qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default());
 161
 162     for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
 163         object_initialize(&s->sdhci[i], sizeof(s->sdhci[i]),
 164                           TYPE_SYSBUS_SDHCI);
 165         qdev_set_parent_bus(DEVICE(&s->sdhci[i]),
 166                             sysbus_get_default());
 167     }
 168
 169     for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
 170         object_initialize(&s->spi[i], sizeof(s->spi[i]),
 171                           TYPE_XILINX_SPIPS);
 172         qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
 173     }
 174
 175     object_initialize(&s->dp, sizeof(s->dp), TYPE_XLNX_DP);
 176     qdev_set_parent_bus(DEVICE(&s->dp), sysbus_get_default());
 177
 178     object_initialize(&s->dpdma, sizeof(s->dpdma), TYPE_XLNX_DPDMA);
 179     qdev_set_parent_bus(DEVICE(&s->dpdma), sysbus_get_default());
 180 }
 181
 182 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
 183 {
 184     XlnxZynqMPState *s = XLNX_ZYNQMP(dev);
 185     MemoryRegion *system_memory = get_system_memory();
 186     uint8_t i;
 187     uint64_t ram_size;
 188     const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]";
 189     ram_addr_t ddr_low_size, ddr_high_size;
 190     qemu_irq gic_spi[GIC_NUM_SPI_INTR];
 191     Error *err = NULL;
 192
 193     ram_size = memory_region_size(s->ddr_ram);
 194
 195     /* Create the DDR Memory Regions. User friendly checks should happen at
 196      * the board level
 197      */
 198     if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) {
 199         /* The RAM size is above the maximum available for the low DDR.
 200          * Create the high DDR memory region as well.
 201          */
 202         assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE);
 203         ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
 204         ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
 205
 206         memory_region_init_alias(&s->ddr_ram_high, NULL,
 207                                  "ddr-ram-high", s->ddr_ram,
 208                                   ddr_low_size, ddr_high_size);
 209         memory_region_add_subregion(get_system_memory(),
 210                                     XLNX_ZYNQMP_HIGH_RAM_START,
 211                                     &s->ddr_ram_high);
 212     } else {
 213         /* RAM must be non-zero */
 214         assert(ram_size);
 215         ddr_low_size = ram_size;
 216     }
 217
 218     memory_region_init_alias(&s->ddr_ram_low, NULL,
 219                              "ddr-ram-low", s->ddr_ram,
 220                               0, ddr_low_size);
 221     memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low);
 222
 223     /* Create the four OCM banks */
 224     for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) {
 225         char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i);
 226
 227         memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name,
 228                                XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal);
 229         vmstate_register_ram_global(&s->ocm_ram[i]);
 230         memory_region_add_subregion(get_system_memory(),
 231                                     XLNX_ZYNQMP_OCM_RAM_0_ADDRESS +
 232                                         i * XLNX_ZYNQMP_OCM_RAM_SIZE,
 233                                     &s->ocm_ram[i]);
 234
 235         g_free(ocm_name);
 236     }
 237
 238     qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
 239     qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
 240     qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", XLNX_ZYNQMP_NUM_APU_CPUS);
 241
 242     /* Realize APUs before realizing the GIC. KVM requires this.  */
 243     for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
 244         char *name;
 245
 246         object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC,
 247                                 "psci-conduit", &error_abort);
 248
 249         name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i]));
 250         if (strcmp(name, boot_cpu)) {
 251             /* Secondary CPUs start in PSCI powered-down state */
 252             object_property_set_bool(OBJECT(&s->apu_cpu[i]), true,
 253                                      "start-powered-off", &error_abort);
 254         } else {
 255             s->boot_cpu_ptr = &s->apu_cpu[i];
 256         }
 257         g_free(name);
 258
 259         object_property_set_bool(OBJECT(&s->apu_cpu[i]),
 260                                  s->secure, "has_el3", NULL);
 261         object_property_set_bool(OBJECT(&s->apu_cpu[i]),
 262                                  false, "has_el2", NULL);
 263         object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR,
 264                                 "reset-cbar", &error_abort);
 265         object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized",
 266                                  &err);
 267         if (err) {
 268             error_propagate(errp, err);
 269             return;
 270         }
 271     }
 272
 273     object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
 274     if (err) {
 275         error_propagate(errp, err);
 276         return;
 277     }
 278
 279     assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS);
 280     for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) {
 281         SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic);
 282         const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i];
 283         MemoryRegion *mr = sysbus_mmio_get_region(gic, r->region_index);
 284         uint32_t addr = r->address;
 285         int j;
 286
 287         sysbus_mmio_map(gic, r->region_index, addr);
 288
 289         for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) {
 290             MemoryRegion *alias = &s->gic_mr[i][j];
 291
 292             addr += XLNX_ZYNQMP_GIC_REGION_SIZE;
 293             memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr,
 294                                      0, XLNX_ZYNQMP_GIC_REGION_SIZE);
 295             memory_region_add_subregion(system_memory, addr, alias);
 296         }
 297     }
 298
 299     for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
 300         qemu_irq irq;
 301
 302         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
 303                            qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
 304                                             ARM_CPU_IRQ));
 305         irq = qdev_get_gpio_in(DEVICE(&s->gic),
 306                                arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI));
 307         qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 0, irq);
 308         irq = qdev_get_gpio_in(DEVICE(&s->gic),
 309                                arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI));
 310         qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 1, irq);
 311     }
 312
 313     if (s->has_rpu) {
 314         xlnx_zynqmp_create_rpu(s, boot_cpu, &err);
 315         if (err) {
 316             error_propagate(errp, err);
 317             return;
 318         }
 319     }
 320
 321     if (!s->boot_cpu_ptr) {
 322         error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu);
 323         return;
 324     }
 325
 326     for (i = 0; i < GIC_NUM_SPI_INTR; i++) {
 327         gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i);
 328     }
 329
 330     for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
 331         NICInfo *nd = &nd_table[i];
 332
 333         if (nd->used) {
 334             qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
 335             qdev_set_nic_properties(DEVICE(&s->gem[i]), nd);
 336         }
 337         object_property_set_int(OBJECT(&s->gem[i]), 2, "num-priority-queues",
 338                                   &error_abort);
 339         object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err);
 340         if (err) {
 341             error_propagate(errp, err);
 342             return;
 343         }
 344         sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]);
 345         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0,
 346                            gic_spi[gem_intr[i]]);
 347     }
 348
 349     for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
 350         qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hds[i]);
 351         object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
 352         if (err) {
 353             error_propagate(errp, err);
 354             return;
 355         }
 356         sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]);
 357         sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
 358                            gic_spi[uart_intr[i]]);
 359     }
 360
 361     object_property_set_int(OBJECT(&s->sata), SATA_NUM_PORTS, "num-ports",
 362                             &error_abort);
 363     object_property_set_bool(OBJECT(&s->sata), true, "realized", &err);
 364     if (err) {
 365         error_propagate(errp, err);
 366         return;
 367     }
 368
 369     sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR);
 370     sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]);
 371
 372     for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
 373         char *bus_name;
 374
 375         object_property_set_bool(OBJECT(&s->sdhci[i]), true,
 376                                  "realized", &err);
 377         if (err) {
 378             error_propagate(errp, err);
 379             return;
 380         }
 381         sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci[i]), 0,
 382                         sdhci_addr[i]);
 383         sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci[i]), 0,
 384                            gic_spi[sdhci_intr[i]]);
 385         /* Alias controller SD bus to the SoC itself */
 386         bus_name = g_strdup_printf("sd-bus%d", i);
 387         object_property_add_alias(OBJECT(s), bus_name,
 388                                   OBJECT(&s->sdhci[i]), "sd-bus",
 389                                   &error_abort);
 390         g_free(bus_name);
 391     }
 392
 393     for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
 394         gchar *bus_name;
 395
 396         object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
 397
 398         sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
 399         sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
 400                            gic_spi[spi_intr[i]]);
 401
 402         /* Alias controller SPI bus to the SoC itself */
 403         bus_name = g_strdup_printf("spi%d", i);
 404         object_property_add_alias(OBJECT(s), bus_name,
 405                                   OBJECT(&s->spi[i]), "spi0",
 406                                   &error_abort);
 407         g_free(bus_name);
 408     }
 409
 410     object_property_set_bool(OBJECT(&s->dp), true, "realized", &err);
 411     if (err) {
 412         error_propagate(errp, err);
 413         return;
 414     }
 415     sysbus_mmio_map(SYS_BUS_DEVICE(&s->dp), 0, DP_ADDR);
 416     sysbus_connect_irq(SYS_BUS_DEVICE(&s->dp), 0, gic_spi[DP_IRQ]);
 417
 418     object_property_set_bool(OBJECT(&s->dpdma), true, "realized", &err);
 419     if (err) {
 420         error_propagate(errp, err);
 421         return;
 422     }
 423     object_property_set_link(OBJECT(&s->dp), OBJECT(&s->dpdma), "dpdma",
 424                              &error_abort);
 425     sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR);
 426     sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]);
 427 }
 428
 429 static Property xlnx_zynqmp_props[] = {
 430     DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu),
 431     DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false),
 432     DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false),
 433     DEFINE_PROP_END_OF_LIST()
 434 };
 435
 436 static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data)
 437 {
 438     DeviceClass *dc = DEVICE_CLASS(oc);
 439
 440     dc->props = xlnx_zynqmp_props;
 441     dc->realize = xlnx_zynqmp_realize;
 442
 443     /*
 444      * Reason: creates an ARM CPU, thus use after free(), see
 445      * arm_cpu_class_init()
 446      */
 447     dc->cannot_destroy_with_object_finalize_yet = true;
 448 }
 449
 450 static const TypeInfo xlnx_zynqmp_type_info = {
 451     .name = TYPE_XLNX_ZYNQMP,
 452     .parent = TYPE_DEVICE,
 453     .instance_size = sizeof(XlnxZynqMPState),
 454     .instance_init = xlnx_zynqmp_init,
 455     .class_init = xlnx_zynqmp_class_init,
 456 };
 457
 458 static void xlnx_zynqmp_register_types(void)
 459 {
 460     type_register_static(&xlnx_zynqmp_type_info);
 461 }
 462
 463 type_init(xlnx_zynqmp_register_types)